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Macpaul Linb9725ae2011-09-23 16:49:59 +08001/*
2 * Copyright (C) 2011 Andes Technology Corporation
3 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef __CONFIG_H
24#define __CONFIG_H
25
26#include <asm/arch/ag102.h>
27
28/*
29 * CPU and Board Configuration Options
30 */
31#define CONFIG_ADP_AG102
32
33#define CONFIG_USE_INTERRUPT
34
35#define CONFIG_SKIP_LOWLEVEL_INIT
36
37#ifndef CONFIG_SKIP_LOWLEVEL_INIT
38#define CONFIG_MEM_REMAP
39#endif
40
41#ifdef CONFIG_SKIP_LOWLEVEL_INIT
42#define CONFIG_SYS_TEXT_BASE 0x04200000
43#else
44#define CONFIG_SYS_TEXT_BASE 0x00000000
45#endif
46
47/*
48 * Timer
49 */
50
51/*
52 * According to the discussion in u-boot mailing list before,
53 * CONFIG_SYS_HZ at 1000 is mandatory.
54 */
55#define CONFIG_SYS_HZ 1000
56#define CONFIG_SYS_CLK_FREQ (66000000 * 2)
57#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
58
59/*
60 * Use Externel CLOCK or PCLK
61 */
62#undef CONFIG_FTRTC010_EXTCLK
63
64#ifndef CONFIG_FTRTC010_EXTCLK
65#define CONFIG_FTRTC010_PCLK
66#endif
67
68#ifdef CONFIG_FTRTC010_EXTCLK
69#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
70#else
71#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
72#endif
73
74#define TIMER_LOAD_VAL 0xffffffff
75
76/*
77 * Real Time Clock
78 */
79#define CONFIG_RTC_FTRTC010
80
81/*
82 * Real Time Clock Divider
83 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
84 */
85#define OSC_5MHZ (5*1000000)
86#define OSC_CLK (2*OSC_5MHZ)
87#define RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
88
89/*
90 * Serial console configuration
91 */
92
93/* FTUART is a high speed NS 16C550A compatible UART */
94#define CONFIG_BAUDRATE 38400
95#define CONFIG_CONS_INDEX 1
96#define CONFIG_SYS_NS16550
97#define CONFIG_SYS_NS16550_SERIAL
98#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_01_BASE
99#define CONFIG_SYS_NS16550_REG_SIZE -4
100#define CONFIG_SYS_NS16550_CLK 33000000 /* AG102 */
101
Macpaul Linb9725ae2011-09-23 16:49:59 +0800102/*
103 * Ethernet
104 */
105#define CONFIG_NET_MULTI
106#define CONFIG_PHY_MAX_ADDR 32 /* this comes from <linux/phy.h> */
107#define CONFIG_SYS_DISCOVER_PHY
108#define CONFIG_FTGMAC100
109#define CONFIG_FTGMAC100_EGIGA
110
111#define CONFIG_BOOTDELAY 3
112
113/*
114 * SD (MMC) controller
115 */
116#define CONFIG_MMC
117#define CONFIG_CMD_MMC
118#define CONFIG_GENERIC_MMC
119#define CONFIG_DOS_PARTITION
120#define CONFIG_FTSDC010
121#define CONFIG_FTSDC010_NUMBER 1
122#define CONFIG_FTSDC010_SDIO
123#define CONFIG_CMD_FAT
124#define CONFIG_CMD_EXT2
125
126/*
127 * Command line configuration.
128 */
129#include <config_cmd_default.h>
130
131#define CONFIG_CMD_CACHE
132#define CONFIG_CMD_DATE
133#define CONFIG_CMD_PING
134#define CONFIG_CMD_IDE
135#define CONFIG_CMD_FAT
136#define CONFIG_CMD_ELF
137
138#undef CONFIG_CMD_FLASH
139#undef CONFIG_CMD_IMLS
140
141/*
142 * PCI
143 */
144#define CONFIG_PCI
145#define CONFIG_FTPCI100
146#define CONFIG_FTPCI100_MEM_BASE 0xa0000000
147#define CONFIG_FTPCI100_IO_SIZE FTPCI100_BASE_IO_SIZE(256) /* 256M */
148#define CONFIG_FTPCI100_MEM_SIZE FTPCI100_MEM_SIZE(128) /* 128M */
149#define CONFIG_FTPCI100_MEM_BASE_SIZE1 0x50
150
151#define CONFIG_PCI_MEM_BUS 0xa0000000
152#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
153#define CONFIG_PCI_MEM_SIZE 0x01000000 /* 256M */
154
155#define CONFIG_PCI_IO_BUS 0x90000000
156#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
157#define CONFIG_PCI_IO_SIZE 0x00100000 /* 1M */
158
159/*
160 * USB
161 */
162#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
163#if defined(CONFIG_FTPCI100)
164#define __io /* enable outl & inl */
165#define CONFIG_CMD_USB
166#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 5
167#define CONFIG_USB_STORAGE
168#define CONFIG_USB_EHCI
169#define CONFIG_PCI_EHCI_DEVICE 0
170#define CONFIG_USB_EHCI_PCI
171#define CONFIG_PREBOOT "usb start;"
172#endif /* #if defiend(CONFIG_FTPCI100) */
173#endif /* #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) */
174
175/*
176 * IDE/ATA stuff
177 */
178#define __io
179#define CONFIG_IDE_AHB
180#define CONFIG_IDE_FTIDE020
181
182#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
183#undef CONFIG_IDE_LED /* no led for ide supported */
184#define CONFIG_IDE_RESET 1 /* reset for ide supported */
185#define CONFIG_IDE_PREINIT 1 /* preinit for ide */
186
187/* max: 2 IDE busses */
188#define CONFIG_SYS_IDE_MAXBUS 1 /* origin: 2 */
189/* max: 2 drives per IDE bus */
190#define CONFIG_SYS_IDE_MAXDEVICE 1 /* origin: (MAXBUS * 2) */
191
192#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_FTIDE020S_BASE
193#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
194#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0000
195
196#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* for data I/O */
197#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* for normal regs access */
198#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* for alternate regs */
199
200#define CONFIG_MAC_PARTITION
201#define CONFIG_DOS_PARTITION
202#define CONFIG_SUPPORT_VFAT
203
204/*
205 * Miscellaneous configurable options
206 */
207#define CONFIG_SYS_LONGHELP /* undef to save memory */
208#define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */
209#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
210
211/* Print Buffer Size */
212#define CONFIG_SYS_PBSIZE \
213 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
214
215/* max number of command args */
216#define CONFIG_SYS_MAXARGS 16
217
218/* Boot Argument Buffer Size */
219#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
220
221/*
Macpaul Linb9725ae2011-09-23 16:49:59 +0800222 * Size of malloc() pool
223 */
224#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
225
226/*
227 * size in bytes reserved for initial data
228*/
229#define CONFIG_SYS_GBL_DATA_SIZE 128
230
231/*
232 * AHB Controller configuration
233 */
234#define CONFIG_FTAHBC020S
235
236#ifdef CONFIG_FTAHBC020S
237#include <faraday/ftahbc020s.h>
238
239/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
240#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100
241
242/*
243 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
244 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
245 * in C language.
246 */
247#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
248 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
249 FTAHBC020S_SLAVE_BSR_SIZE(0xb))
250#endif
251
252/*
253 * Watchdog
254 */
255#define CONFIG_FTWDT010_WATCHDOG
256
257/*
258 * PCU Power Control Unit configuration
259 */
260#define CONFIG_ANDES_PCU
261
262#ifdef CONFIG_ANDES_PCU
263#include <andestech/andes_pcu.h>
264
265#endif
266
267/*
268 * DDR DRAM controller configuration
269 */
270#define CONFIG_DWCDDR21MCTL
271
272#ifdef CONFIG_DWCDDR21MCTL
273#include <synopsys/dwcddr21mctl.h>
274/* DCR:
275 * 2GB: 0x000025d2, 2GB (1Gb x8 2 ranks) Micron/innoDisk/Transcend
276 * 1GB: 0x000021d2, 1GB (1Gb x8 1 rank) Micron/Transcend/innoDisk
277 * 512MB: 0x000025cc, Micron 512MB (512Mb x16 2 ranks)
278 * 512MB: 0x000021ca, Trenscend/innoDisk 512MB (512Mb x8 1 rank)
279 * 256MB: 0x000020d4, Micron 256MB (1Gb x16 1 ranks)
280 */
281#define CONFIG_SYS_DWCDDR21MCTL_CCR 0x00020004
282#define CONFIG_SYS_DWCDDR21MCTL_CCR2 (DWCDDR21MCTL_CCR_DTT(0x1) | \
283 DWCDDR21MCTL_CCR_DFTLM(0x4) | \
284 DWCDDR21MCTL_CCR_HOSTEN(0x1))
285
286/* 0x04: 0x000020d4 */
287#define CONFIG_SYS_DWCDDR21MCTL_DCR 0x000020ca
288
289/* 0x08: 0x0000000f */
290#define CONFIG_SYS_DWCDDR21MCTL_IOCR 0x0000000f
291
292/* 0x10: 0x00034812 */
293#define CONFIG_SYS_DWCDDR21MCTL_DRR (DWCDDR21MCTL_DRR_TRFC(0x12) | \
294 DWCDDR21MCTL_DRR_TRFPRD(0x0348))
295/* 0x24 */
296#define CONFIG_SYS_DWCDDR21MCTL_DLLCR0 DWCDDR21MCTL_DLLCR_PHASE(0x0)
297
298/* 0x4c: 0x00000040 */
299#define CONFIG_SYS_DWCDDR21MCTL_RSLR0 0x00000040
300
301/* 0x5c: 0x000055CF */
302#define CONFIG_SYS_DWCDDR21MCTL_RDGR0 0x000055cf
303
304/* 0xa4: 0x00100000 */
305#define CONFIG_SYS_DWCDDR21MCTL_DTAR (DWCDDR21MCTL_DTAR_DTBANK(0x0) | \
306 DWCDDR21MCTL_DTAR_DTROW(0x0100) | \
307 DWCDDR21MCTL_DTAR_DTCOL(0x0))
308/* 0x1f0: 0x00000852 */
309#define CONFIG_SYS_DWCDDR21MCTL_MR (DWCDDR21MCTL_MR_WR(0x4) | \
310 DWCDDR21MCTL_MR_CL(0x5) | \
311 DWCDDR21MCTL_MR_BL(0x2))
312#endif
313
314/*
315 * Physical Memory Map
316 */
317#if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
318#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
319#if defined(CONFIG_MEM_REMAP)
320#define PHYS_SDRAM_0_AT_INIT 0x80000000 /* SDRAM Bank #1 before remap*/
321#endif
322#else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
323#define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */
324#endif
325
326#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
327#define PHYS_SDRAM_0_SIZE 0x10000000 /* 256 MB */
328
329#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
330
331#ifdef CONFIG_MEM_REMAP
332#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
333 GENERATED_GBL_DATA_SIZE)
334#else
335#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
336 GENERATED_GBL_DATA_SIZE)
337#endif /* CONFIG_MEM_REMAP */
338
339/*
340 * Load address and memory test area should agree with
341 * board/faraday/a320/config.mk
342 * Be careful not to overwrite U-boot itself.
343 */
344#define CONFIG_SYS_LOAD_ADDR 0x0CF00000
345
346/* memtest works on 63 MB in DRAM */
347#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
348#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
349
350/*
351 * Static memory controller configuration
352 */
353
354/*
355 * FLASH and environment organization
356 */
357#define CONFIG_SYS_NO_FLASH
358
359/*
360 * Env Storage Settings
361 */
362#define CONFIG_ENV_IS_NOWHERE
363#define CONFIG_ENV_SIZE 4096
364
365#endif /* __CONFIG_H */