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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk324f6cf2002-10-07 21:13:39 +00002/*
3 * (C) Copyright 2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
wdenk324f6cf2002-10-07 21:13:39 +00005 */
6
Tom Rinid678a592024-05-18 20:20:43 -06007#include <common.h>
wdenk324f6cf2002-10-07 21:13:39 +00008
wdenk324f6cf2002-10-07 21:13:39 +00009#include <post.h>
10
Yuri Tikhonov6e8ec682008-05-08 15:42:47 +020011extern int ocm_post_test (int flags);
wdenk324f6cf2002-10-07 21:13:39 +000012extern int cache_post_test (int flags);
13extern int watchdog_post_test (int flags);
14extern int i2c_post_test (int flags);
15extern int rtc_post_test (int flags);
16extern int memory_post_test (int flags);
17extern int cpu_post_test (int flags);
Igor Lisitsina11e0692007-03-28 19:06:19 +040018extern int fpu_post_test (int flags);
wdenk324f6cf2002-10-07 21:13:39 +000019extern int uart_post_test (int flags);
20extern int ether_post_test (int flags);
21extern int spi_post_test (int flags);
22extern int usb_post_test (int flags);
23extern int spr_post_test (int flags);
wdenk4532cb62003-04-27 22:52:51 +000024extern int sysmon_post_test (int flags);
wdenk5a8c51c2004-04-15 21:16:42 +000025extern int dsp_post_test (int flags);
wdenk79fa88f2004-06-07 23:46:25 +000026extern int codec_post_test (int flags);
Pavel Kolesnikov531e3e82007-07-20 15:03:03 +020027extern int ecc_post_test (int flags);
Mike Frysingerf6f73952011-05-10 13:35:40 +000028extern int flash_post_test(int flags);
wdenk4532cb62003-04-27 22:52:51 +000029
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +010030extern int dspic_init_post_test (int flags);
31extern int dspic_post_test (int flags);
32extern int gdc_post_test (int flags);
33extern int fpga_post_test (int flags);
34extern int lwmon5_watchdog_post_test(int flags);
35extern int sysmon1_post_test(int flags);
Anatolij Gustschin29fd7ce2010-04-24 19:27:11 +020036extern int coprocessor_post_test(int flags);
Mike Frysinger21513742011-05-10 16:22:25 -040037extern int led_post_test(int flags);
38extern int button_post_test(int flags);
Valentin Longchamp8d3fcb52011-09-12 04:18:40 +000039extern int memory_regions_post_test(int flags);
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +010040
wdenk4532cb62003-04-27 22:52:51 +000041extern int sysmon_init_f (void);
42
43extern void sysmon_reloc (void);
44
wdenk324f6cf2002-10-07 21:13:39 +000045
46struct post_test post_list[] =
47{
Tom Rini1e019502022-12-04 10:14:17 -050048#if CFG_POST & CFG_SYS_POST_OCM
Yuri Tikhonov6e8ec682008-05-08 15:42:47 +020049 {
50 "OCM test",
51 "ocm",
52 "This test checks on chip memory (OCM).",
Yuri Tikhonov7845d492008-05-08 15:46:02 +020053 POST_ROM | POST_ALWAYS | POST_PREREL | POST_CRITICAL | POST_STOP,
Yuri Tikhonov6e8ec682008-05-08 15:42:47 +020054 &ocm_post_test,
55 NULL,
56 NULL,
Tom Rini1e019502022-12-04 10:14:17 -050057 CFG_SYS_POST_OCM
Yuri Tikhonov6e8ec682008-05-08 15:42:47 +020058 },
59#endif
Tom Rini1e019502022-12-04 10:14:17 -050060#if CFG_POST & CFG_SYS_POST_CACHE
wdenk324f6cf2002-10-07 21:13:39 +000061 {
wdenk8bde7f72003-06-27 21:31:46 +000062 "Cache test",
63 "cache",
64 "This test verifies the CPU cache operation.",
65 POST_RAM | POST_ALWAYS,
66 &cache_post_test,
67 NULL,
68 NULL,
Tom Rini1e019502022-12-04 10:14:17 -050069 CFG_SYS_POST_CACHE
wdenk324f6cf2002-10-07 21:13:39 +000070 },
71#endif
Tom Rini1e019502022-12-04 10:14:17 -050072#if CFG_POST & CFG_SYS_POST_WATCHDOG
Tom Rini9cebc4a2022-11-19 18:45:44 -050073#if defined(CFG_POST_WATCHDOG)
74 CFG_POST_WATCHDOG,
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +010075#else
wdenk324f6cf2002-10-07 21:13:39 +000076 {
wdenk8bde7f72003-06-27 21:31:46 +000077 "Watchdog timer test",
78 "watchdog",
79 "This test checks the watchdog timer.",
wdenk8564acf2003-07-14 22:13:32 +000080 POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT,
wdenk8bde7f72003-06-27 21:31:46 +000081 &watchdog_post_test,
82 NULL,
83 NULL,
Tom Rini1e019502022-12-04 10:14:17 -050084 CFG_SYS_POST_WATCHDOG
wdenk324f6cf2002-10-07 21:13:39 +000085 },
86#endif
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +010087#endif
Tom Rini1e019502022-12-04 10:14:17 -050088#if CFG_POST & CFG_SYS_POST_I2C
wdenk324f6cf2002-10-07 21:13:39 +000089 {
wdenk8bde7f72003-06-27 21:31:46 +000090 "I2C test",
91 "i2c",
92 "This test verifies the I2C operation.",
93 POST_RAM | POST_ALWAYS,
94 &i2c_post_test,
95 NULL,
96 NULL,
Tom Rini1e019502022-12-04 10:14:17 -050097 CFG_SYS_POST_I2C
wdenk324f6cf2002-10-07 21:13:39 +000098 },
99#endif
Tom Rini1e019502022-12-04 10:14:17 -0500100#if CFG_POST & CFG_SYS_POST_RTC
wdenk324f6cf2002-10-07 21:13:39 +0000101 {
wdenk8bde7f72003-06-27 21:31:46 +0000102 "RTC test",
103 "rtc",
104 "This test verifies the RTC operation.",
wdenk8564acf2003-07-14 22:13:32 +0000105 POST_RAM | POST_SLOWTEST | POST_MANUAL,
wdenk8bde7f72003-06-27 21:31:46 +0000106 &rtc_post_test,
107 NULL,
108 NULL,
Tom Rini1e019502022-12-04 10:14:17 -0500109 CFG_SYS_POST_RTC
wdenk324f6cf2002-10-07 21:13:39 +0000110 },
111#endif
Tom Rini9cebc4a2022-11-19 18:45:44 -0500112#if CFG_POST & CFG_SYS_POST_MEMORY
wdenk324f6cf2002-10-07 21:13:39 +0000113 {
wdenk8bde7f72003-06-27 21:31:46 +0000114 "Memory test",
115 "memory",
116 "This test checks RAM.",
wdenk8564acf2003-07-14 22:13:32 +0000117 POST_ROM | POST_POWERON | POST_SLOWTEST | POST_PREREL,
wdenk8bde7f72003-06-27 21:31:46 +0000118 &memory_post_test,
119 NULL,
120 NULL,
Tom Rini65cc0e22022-11-16 13:10:41 -0500121 CFG_SYS_POST_MEMORY
wdenk324f6cf2002-10-07 21:13:39 +0000122 },
123#endif
Tom Rini1e019502022-12-04 10:14:17 -0500124#if CFG_POST & CFG_SYS_POST_CPU
wdenk324f6cf2002-10-07 21:13:39 +0000125 {
wdenk8bde7f72003-06-27 21:31:46 +0000126 "CPU test",
127 "cpu",
128 "This test verifies the arithmetic logic unit of"
129 " CPU.",
130 POST_RAM | POST_ALWAYS,
131 &cpu_post_test,
132 NULL,
133 NULL,
Tom Rini1e019502022-12-04 10:14:17 -0500134 CFG_SYS_POST_CPU
wdenk324f6cf2002-10-07 21:13:39 +0000135 },
136#endif
Tom Rini1e019502022-12-04 10:14:17 -0500137#if CFG_POST & CFG_SYS_POST_FPU
Igor Lisitsina11e0692007-03-28 19:06:19 +0400138 {
139 "FPU test",
140 "fpu",
141 "This test verifies the arithmetic logic unit of"
142 " FPU.",
143 POST_RAM | POST_ALWAYS,
144 &fpu_post_test,
145 NULL,
146 NULL,
Tom Rini1e019502022-12-04 10:14:17 -0500147 CFG_SYS_POST_FPU
Igor Lisitsina11e0692007-03-28 19:06:19 +0400148 },
149#endif
Tom Rini1e019502022-12-04 10:14:17 -0500150#if CFG_POST & CFG_SYS_POST_UART
Tom Rini9cebc4a2022-11-19 18:45:44 -0500151#if defined(CFG_POST_UART)
152 CFG_POST_UART,
Stefan Roese834a45d2010-10-07 14:16:25 +0200153#else
wdenk324f6cf2002-10-07 21:13:39 +0000154 {
wdenk8bde7f72003-06-27 21:31:46 +0000155 "UART test",
156 "uart",
157 "This test verifies the UART operation.",
wdenk8564acf2003-07-14 22:13:32 +0000158 POST_RAM | POST_SLOWTEST | POST_MANUAL,
wdenk8bde7f72003-06-27 21:31:46 +0000159 &uart_post_test,
160 NULL,
161 NULL,
Tom Rini1e019502022-12-04 10:14:17 -0500162 CFG_SYS_POST_UART
wdenk324f6cf2002-10-07 21:13:39 +0000163 },
Tom Rini9cebc4a2022-11-19 18:45:44 -0500164#endif /* CFG_POST_UART */
wdenk324f6cf2002-10-07 21:13:39 +0000165#endif
Tom Rini1e019502022-12-04 10:14:17 -0500166#if CFG_POST & CFG_SYS_POST_ETHER
wdenk324f6cf2002-10-07 21:13:39 +0000167 {
wdenk8bde7f72003-06-27 21:31:46 +0000168 "ETHERNET test",
169 "ethernet",
170 "This test verifies the ETHERNET operation.",
Robert P. J. Day5735bca2016-03-27 10:18:55 -0400171 POST_RAM | POST_ALWAYS,
wdenk8bde7f72003-06-27 21:31:46 +0000172 &ether_post_test,
173 NULL,
174 NULL,
Tom Rini1e019502022-12-04 10:14:17 -0500175 CFG_SYS_POST_ETHER
wdenk324f6cf2002-10-07 21:13:39 +0000176 },
177#endif
Tom Rini1e019502022-12-04 10:14:17 -0500178#if CFG_POST & CFG_SYS_POST_USB
wdenk324f6cf2002-10-07 21:13:39 +0000179 {
wdenk8bde7f72003-06-27 21:31:46 +0000180 "USB test",
181 "usb",
182 "This test verifies the USB operation.",
Robert P. J. Day5735bca2016-03-27 10:18:55 -0400183 POST_RAM | POST_ALWAYS,
wdenk8bde7f72003-06-27 21:31:46 +0000184 &usb_post_test,
185 NULL,
186 NULL,
Tom Rini1e019502022-12-04 10:14:17 -0500187 CFG_SYS_POST_USB
wdenk324f6cf2002-10-07 21:13:39 +0000188 },
189#endif
Tom Rini1e019502022-12-04 10:14:17 -0500190#if CFG_POST & CFG_SYS_POST_SPR
wdenk324f6cf2002-10-07 21:13:39 +0000191 {
wdenk8bde7f72003-06-27 21:31:46 +0000192 "SPR test",
193 "spr",
194 "This test checks SPR contents.",
Stefan Roeseb2e21422008-01-09 10:38:58 +0100195 POST_RAM | POST_ALWAYS,
wdenk8bde7f72003-06-27 21:31:46 +0000196 &spr_post_test,
197 NULL,
198 NULL,
Tom Rini1e019502022-12-04 10:14:17 -0500199 CFG_SYS_POST_SPR
wdenk324f6cf2002-10-07 21:13:39 +0000200 },
201#endif
Tom Rini1e019502022-12-04 10:14:17 -0500202#if CFG_POST & CFG_SYS_POST_SYSMON
wdenk4532cb62003-04-27 22:52:51 +0000203 {
wdenk8bde7f72003-06-27 21:31:46 +0000204 "SYSMON test",
205 "sysmon",
206 "This test monitors system hardware.",
207 POST_RAM | POST_ALWAYS,
208 &sysmon_post_test,
209 &sysmon_init_f,
210 &sysmon_reloc,
Tom Rini1e019502022-12-04 10:14:17 -0500211 CFG_SYS_POST_SYSMON
wdenk4532cb62003-04-27 22:52:51 +0000212 },
213#endif
Tom Rini1e019502022-12-04 10:14:17 -0500214#if CFG_POST & CFG_SYS_POST_DSP
wdenk5a8c51c2004-04-15 21:16:42 +0000215 {
216 "DSP test",
217 "dsp",
218 "This test checks any connected DSP(s).",
Robert P. J. Day5735bca2016-03-27 10:18:55 -0400219 POST_RAM | POST_ALWAYS,
wdenk5a8c51c2004-04-15 21:16:42 +0000220 &dsp_post_test,
221 NULL,
222 NULL,
Tom Rini1e019502022-12-04 10:14:17 -0500223 CFG_SYS_POST_DSP
wdenk5a8c51c2004-04-15 21:16:42 +0000224 },
225#endif
Tom Rini1e019502022-12-04 10:14:17 -0500226#if CFG_POST & CFG_SYS_POST_CODEC
wdenk79fa88f2004-06-07 23:46:25 +0000227 {
228 "CODEC test",
229 "codec",
230 "This test checks any connected codec(s).",
231 POST_RAM | POST_MANUAL,
232 &codec_post_test,
233 NULL,
234 NULL,
Tom Rini1e019502022-12-04 10:14:17 -0500235 CFG_SYS_POST_CODEC
wdenk79fa88f2004-06-07 23:46:25 +0000236 },
237#endif
Tom Rini1e019502022-12-04 10:14:17 -0500238#if CFG_POST & CFG_SYS_POST_ECC
Pavel Kolesnikov531e3e82007-07-20 15:03:03 +0200239 {
240 "ECC test",
241 "ecc",
Larry Johnson8dafa872008-01-12 23:35:33 -0500242 "This test checks the ECC facility of memory.",
243 POST_ROM | POST_ALWAYS | POST_PREREL,
Pavel Kolesnikov531e3e82007-07-20 15:03:03 +0200244 &ecc_post_test,
245 NULL,
246 NULL,
Tom Rini1e019502022-12-04 10:14:17 -0500247 CFG_SYS_POST_ECC
Pavel Kolesnikov531e3e82007-07-20 15:03:03 +0200248 },
249#endif
Tom Rini1e019502022-12-04 10:14:17 -0500250#if CFG_POST & CFG_SYS_POST_BSPEC1
Tom Rini9cebc4a2022-11-19 18:45:44 -0500251 CFG_POST_BSPEC1,
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +0100252#endif
Tom Rini1e019502022-12-04 10:14:17 -0500253#if CFG_POST & CFG_SYS_POST_BSPEC2
Tom Rini9cebc4a2022-11-19 18:45:44 -0500254 CFG_POST_BSPEC2,
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +0100255#endif
Tom Rini1e019502022-12-04 10:14:17 -0500256#if CFG_POST & CFG_SYS_POST_BSPEC3
Tom Rini9cebc4a2022-11-19 18:45:44 -0500257 CFG_POST_BSPEC3,
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +0100258#endif
Tom Rini1e019502022-12-04 10:14:17 -0500259#if CFG_POST & CFG_SYS_POST_BSPEC4
Tom Rini9cebc4a2022-11-19 18:45:44 -0500260 CFG_POST_BSPEC4,
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +0100261#endif
Tom Rini1e019502022-12-04 10:14:17 -0500262#if CFG_POST & CFG_SYS_POST_BSPEC5
Tom Rini9cebc4a2022-11-19 18:45:44 -0500263 CFG_POST_BSPEC5,
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +0100264#endif
Tom Rini1e019502022-12-04 10:14:17 -0500265#if CFG_POST & CFG_SYS_POST_COPROC
Anatolij Gustschin29fd7ce2010-04-24 19:27:11 +0200266 {
267 "Coprocessors communication test",
268 "coproc_com",
269 "This test checks communication with coprocessors.",
270 POST_RAM | POST_ALWAYS | POST_CRITICAL,
271 &coprocessor_post_test,
272 NULL,
273 NULL,
Tom Rini1e019502022-12-04 10:14:17 -0500274 CFG_SYS_POST_COPROC
Mike Frysingerf6f73952011-05-10 13:35:40 +0000275 },
276#endif
Tom Rini1e019502022-12-04 10:14:17 -0500277#if CFG_POST & CFG_SYS_POST_FLASH
Mike Frysingerf6f73952011-05-10 13:35:40 +0000278 {
279 "Parallel NOR flash test",
280 "flash",
281 "This test verifies parallel flash operations.",
282 POST_RAM | POST_SLOWTEST | POST_MANUAL,
283 &flash_post_test,
284 NULL,
285 NULL,
Tom Rini1e019502022-12-04 10:14:17 -0500286 CFG_SYS_POST_FLASH
Mike Frysingerf6f73952011-05-10 13:35:40 +0000287 },
Anatolij Gustschin29fd7ce2010-04-24 19:27:11 +0200288#endif
Tom Rini9cebc4a2022-11-19 18:45:44 -0500289#if CFG_POST & CFG_SYS_POST_MEM_REGIONS
Valentin Longchamp8d3fcb52011-09-12 04:18:40 +0000290 {
291 "Memory regions test",
292 "mem_regions",
293 "This test checks regularly placed regions of the RAM.",
294 POST_ROM | POST_SLOWTEST | POST_PREREL,
295 &memory_regions_post_test,
296 NULL,
297 NULL,
Tom Rini65cc0e22022-11-16 13:10:41 -0500298 CFG_SYS_POST_MEM_REGIONS
Valentin Longchamp8d3fcb52011-09-12 04:18:40 +0000299 },
300#endif
wdenk324f6cf2002-10-07 21:13:39 +0000301};
302
Mike Frysingerd2397812011-05-10 07:28:35 +0000303unsigned int post_list_size = ARRAY_SIZE(post_list);