blob: 1b347541c08b5950db02978fb2b0368b4ae6cbca [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Timur Tabic59e1b42010-06-14 15:28:24 -05002/*
ramneek mehresh3d7506f2012-04-18 19:39:53 +00003 * Copyright 2010-2012 Freescale Semiconductor, Inc.
Timur Tabic59e1b42010-06-14 15:28:24 -05004 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
5 * Timur Tabi <timur@freescale.com>
Timur Tabic59e1b42010-06-14 15:28:24 -05006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#include "../board/freescale/common/ics307_clk.h"
12
Matthew McClintockaf253602012-05-18 06:04:17 +000013#ifdef CONFIG_SDCARD
Ying Zhang7c8eea52013-08-16 15:16:12 +080014#define CONFIG_SPL_FLUSH_IMAGE
15#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Ying Zhang7c8eea52013-08-16 15:16:12 +080016#define CONFIG_SPL_TEXT_BASE 0xf8f81000
Ying Zhangee4d6512014-01-24 15:50:06 +080017#define CONFIG_SPL_PAD_TO 0x20000
18#define CONFIG_SPL_MAX_SIZE (128 * 1024)
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053019#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
Ying Zhang7c8eea52013-08-16 15:16:12 +080020#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
21#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
Ying Zhangee4d6512014-01-24 15:50:06 +080022#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
Ying Zhang7c8eea52013-08-16 15:16:12 +080023#define CONFIG_SYS_MPC85XX_NO_RESETVEC
24#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
25#define CONFIG_SPL_MMC_BOOT
26#ifdef CONFIG_SPL_BUILD
27#define CONFIG_SPL_COMMON_INIT_DDR
28#endif
Matthew McClintockaf253602012-05-18 06:04:17 +000029#endif
30
31#ifdef CONFIG_SPIFLASH
Ying Zhang382ce7e2013-08-16 15:16:14 +080032#define CONFIG_SPL_SPI_FLASH_MINIMAL
33#define CONFIG_SPL_FLUSH_IMAGE
34#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Ying Zhang382ce7e2013-08-16 15:16:14 +080035#define CONFIG_SPL_TEXT_BASE 0xf8f81000
Ying Zhangee4d6512014-01-24 15:50:06 +080036#define CONFIG_SPL_PAD_TO 0x20000
37#define CONFIG_SPL_MAX_SIZE (128 * 1024)
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053038#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
Ying Zhang382ce7e2013-08-16 15:16:14 +080039#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
40#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
Ying Zhangee4d6512014-01-24 15:50:06 +080041#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
Ying Zhang382ce7e2013-08-16 15:16:14 +080042#define CONFIG_SYS_MPC85XX_NO_RESETVEC
43#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
44#define CONFIG_SPL_SPI_BOOT
45#ifdef CONFIG_SPL_BUILD
46#define CONFIG_SPL_COMMON_INIT_DDR
47#endif
Matthew McClintockaf253602012-05-18 06:04:17 +000048#endif
49
Matthew McClintockf45210d2013-02-18 10:02:19 +000050#define CONFIG_NAND_FSL_ELBC
York Sun9407c3f2013-12-17 11:21:08 -080051#define CONFIG_SYS_NAND_MAX_ECCPOS 56
52#define CONFIG_SYS_NAND_MAX_OOBFREE 5
Matthew McClintockf45210d2013-02-18 10:02:19 +000053
54#ifdef CONFIG_NAND
Ying Zhang5d97fe22013-08-16 15:16:16 +080055#ifdef CONFIG_TPL_BUILD
56#define CONFIG_SPL_NAND_BOOT
57#define CONFIG_SPL_FLUSH_IMAGE
Simon Glass989e1ce2016-09-12 23:18:45 -060058#define CONFIG_SPL_NAND_INIT
Ying Zhang5d97fe22013-08-16 15:16:16 +080059#define CONFIG_SPL_COMMON_INIT_DDR
60#define CONFIG_SPL_MAX_SIZE (128 << 10)
61#define CONFIG_SPL_TEXT_BASE 0xf8f81000
62#define CONFIG_SYS_MPC85XX_NO_RESETVEC
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053063#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
Ying Zhang5d97fe22013-08-16 15:16:16 +080064#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
65#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
66#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
67#elif defined(CONFIG_SPL_BUILD)
Matthew McClintockf45210d2013-02-18 10:02:19 +000068#define CONFIG_SPL_INIT_MINIMAL
Matthew McClintockf45210d2013-02-18 10:02:19 +000069#define CONFIG_SPL_FLUSH_IMAGE
Ying Zhang5d97fe22013-08-16 15:16:16 +080070#define CONFIG_SPL_TEXT_BASE 0xff800000
71#define CONFIG_SPL_MAX_SIZE 4096
72#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
73#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
74#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
75#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
76#endif
77#define CONFIG_SPL_PAD_TO 0x20000
78#define CONFIG_TPL_PAD_TO 0x20000
79#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Ying Zhang5d97fe22013-08-16 15:16:16 +080080#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
Matthew McClintockf45210d2013-02-18 10:02:19 +000081#endif
82
Timur Tabic59e1b42010-06-14 15:28:24 -050083/* High Level Configuration Options */
Timur Tabic59e1b42010-06-14 15:28:24 -050084#define CONFIG_MP /* support multiple processors */
85
Kumar Gala7a577fd2011-01-12 02:48:53 -060086#ifndef CONFIG_RESET_VECTOR_ADDRESS
87#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
88#endif
89
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -040090#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
91#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
92#define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */
Timur Tabic59e1b42010-06-14 15:28:24 -050093#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
94#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
95#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
96
Timur Tabic59e1b42010-06-14 15:28:24 -050097#define CONFIG_ENABLE_36BIT_PHYS
Timur Tabibabb3482011-09-06 09:36:06 -050098
99#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500100#define CONFIG_ADDR_MAP
101#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
Jiang Yutang9899ac12011-01-24 18:21:15 +0800102#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500103
Timur Tabic59e1b42010-06-14 15:28:24 -0500104#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
105#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
106#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
107
108/*
109 * These can be toggled for performance analysis, otherwise use default.
110 */
111#define CONFIG_L2_CACHE
112#define CONFIG_BTB
113
114#define CONFIG_SYS_MEMTEST_START 0x00000000
115#define CONFIG_SYS_MEMTEST_END 0x7fffffff
116
Timur Tabie46fedf2011-08-04 18:03:41 -0500117#define CONFIG_SYS_CCSRBAR 0xffe00000
118#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Timur Tabic59e1b42010-06-14 15:28:24 -0500119
Matthew McClintockf45210d2013-02-18 10:02:19 +0000120/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
121 SPL code*/
122#ifdef CONFIG_SPL_BUILD
123#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
124#endif
125
Timur Tabic59e1b42010-06-14 15:28:24 -0500126/* DDR Setup */
127#define CONFIG_DDR_SPD
128#define CONFIG_VERY_BIG_RAM
Timur Tabic59e1b42010-06-14 15:28:24 -0500129
130#ifdef CONFIG_DDR_ECC
131#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
132#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
133#endif
134
135#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
136#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
137
Timur Tabic59e1b42010-06-14 15:28:24 -0500138#define CONFIG_DIMM_SLOTS_PER_CTLR 1
139#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
140
141/* I2C addresses of SPD EEPROMs */
142#define CONFIG_SYS_SPD_BUS_NUM 1
Kumar Galac39f44d2011-01-31 22:18:47 -0600143#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Timur Tabic59e1b42010-06-14 15:28:24 -0500144
Matthew McClintockf45210d2013-02-18 10:02:19 +0000145/* These are used when DDR doesn't use SPD. */
146#define CONFIG_SYS_SDRAM_SIZE 2048
147#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
148#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
149#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
150#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
151#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202
152#define CONFIG_SYS_DDR_TIMING_3 0x00010000
153#define CONFIG_SYS_DDR_TIMING_0 0x40110104
154#define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746
155#define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca
156#define CONFIG_SYS_DDR_MODE_1 0x00441221
157#define CONFIG_SYS_DDR_MODE_2 0x00000000
158#define CONFIG_SYS_DDR_INTERVAL 0x0a280100
159#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
160#define CONFIG_SYS_DDR_CLK_CTRL 0x02800000
161#define CONFIG_SYS_DDR_CONTROL 0xc7000008
162#define CONFIG_SYS_DDR_CONTROL_2 0x24401041
163#define CONFIG_SYS_DDR_TIMING_4 0x00220001
164#define CONFIG_SYS_DDR_TIMING_5 0x02401400
165#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
166#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608
167
Timur Tabic59e1b42010-06-14 15:28:24 -0500168/*
169 * Memory map
170 *
171 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
172 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
173 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
174 *
175 * Localbus cacheable (TBD)
176 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
177 *
178 * Localbus non-cacheable
179 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
180 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
Matthew McClintockf45210d2013-02-18 10:02:19 +0000181 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable
Timur Tabic59e1b42010-06-14 15:28:24 -0500182 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
183 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
184 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
185 */
186
187/*
188 * Local Bus Definitions
189 */
Matthew McClintockf45210d2013-02-18 10:02:19 +0000190#define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */
Jiang Yutang9899ac12011-01-24 18:21:15 +0800191#ifdef CONFIG_PHYS_64BIT
Matthew McClintockf45210d2013-02-18 10:02:19 +0000192#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800193#else
194#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
195#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500196
197#define CONFIG_FLASH_BR_PRELIM \
Matthew McClintockf45210d2013-02-18 10:02:19 +0000198 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
Timur Tabic59e1b42010-06-14 15:28:24 -0500199#define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
200
Matthew McClintockf45210d2013-02-18 10:02:19 +0000201#ifdef CONFIG_NAND
202#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
203#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
204#else
Timur Tabic59e1b42010-06-14 15:28:24 -0500205#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
206#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
Matthew McClintockf45210d2013-02-18 10:02:19 +0000207#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500208
Matthew McClintockf45210d2013-02-18 10:02:19 +0000209#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
Timur Tabic59e1b42010-06-14 15:28:24 -0500210#define CONFIG_SYS_FLASH_QUIET_TEST
211#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
212
Matthew McClintockf45210d2013-02-18 10:02:19 +0000213#define CONFIG_SYS_MAX_FLASH_BANKS 1
Timur Tabic59e1b42010-06-14 15:28:24 -0500214#define CONFIG_SYS_MAX_FLASH_SECT 1024
215
Matthew McClintockf45210d2013-02-18 10:02:19 +0000216#ifndef CONFIG_SYS_MONITOR_BASE
217#ifdef CONFIG_SPL_BUILD
218#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
219#else
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200220#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Matthew McClintockf45210d2013-02-18 10:02:19 +0000221#endif
222#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500223
224#define CONFIG_FLASH_CFI_DRIVER
225#define CONFIG_SYS_FLASH_CFI
226#define CONFIG_SYS_FLASH_EMPTY_INFO
227
Matthew McClintockf45210d2013-02-18 10:02:19 +0000228/* Nand Flash */
229#if defined(CONFIG_NAND_FSL_ELBC)
230#define CONFIG_SYS_NAND_BASE 0xff800000
231#ifdef CONFIG_PHYS_64BIT
232#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
233#else
234#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
235#endif
236
Ying Zhang5d97fe22013-08-16 15:16:16 +0800237#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
Matthew McClintockf45210d2013-02-18 10:02:19 +0000238#define CONFIG_SYS_MAX_NAND_DEVICE 1
Ying Zhang5d97fe22013-08-16 15:16:16 +0800239#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
Matthew McClintockf45210d2013-02-18 10:02:19 +0000240#define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
241
242/* NAND flash config */
243#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
244 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
245 | BR_PS_8 /* Port Size = 8 bit */ \
246 | BR_MS_FCM /* MSEL = FCM */ \
247 | BR_V) /* valid */
248#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \
249 | OR_FCM_PGS /* Large Page*/ \
250 | OR_FCM_CSCT \
251 | OR_FCM_CST \
252 | OR_FCM_CHT \
253 | OR_FCM_SCY_1 \
254 | OR_FCM_TRLX \
255 | OR_FCM_EHTR)
256#ifdef CONFIG_NAND
257#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
258#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
259#else
260#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
261#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
262#endif
263
264#endif /* CONFIG_NAND_FSL_ELBC */
265
Timur Tabic59e1b42010-06-14 15:28:24 -0500266#define CONFIG_MISC_INIT_R
Timur Tabia2d12f82010-07-21 16:56:19 -0500267#define CONFIG_HWCONFIG
Timur Tabic59e1b42010-06-14 15:28:24 -0500268
269#define CONFIG_FSL_NGPIXIS
270#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
Jiang Yutang9899ac12011-01-24 18:21:15 +0800271#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500272#define PIXIS_BASE_PHYS 0xfffdf0000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800273#else
274#define PIXIS_BASE_PHYS PIXIS_BASE
275#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500276
277#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
278#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
279
280#define PIXIS_LBMAP_SWITCH 7
York Sun29068452011-01-26 10:30:00 -0800281#define PIXIS_LBMAP_MASK 0xF0
Timur Tabic59e1b42010-06-14 15:28:24 -0500282#define PIXIS_LBMAP_ALTBANK 0x20
Matthew McClintockf45210d2013-02-18 10:02:19 +0000283#define PIXIS_SPD 0x07
284#define PIXIS_SPD_SYSCLK_MASK 0x07
Jiang Yutang9b6e9d12011-02-24 16:11:56 +0800285#define PIXIS_ELBC_SPI_MASK 0xc0
286#define PIXIS_SPI 0x80
Timur Tabic59e1b42010-06-14 15:28:24 -0500287
288#define CONFIG_SYS_INIT_RAM_LOCK
289#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200290#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Timur Tabic59e1b42010-06-14 15:28:24 -0500291
Timur Tabic59e1b42010-06-14 15:28:24 -0500292#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200293 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Timur Tabic59e1b42010-06-14 15:28:24 -0500294#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
295
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530296#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Jerry Huang07b5edc2011-11-02 09:16:44 +0800297#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
Timur Tabic59e1b42010-06-14 15:28:24 -0500298
299/*
Ying Zhang7c8eea52013-08-16 15:16:12 +0800300 * Config the L2 Cache as L2 SRAM
301*/
302#if defined(CONFIG_SPL_BUILD)
Ying Zhang382ce7e2013-08-16 15:16:14 +0800303#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
Ying Zhang7c8eea52013-08-16 15:16:12 +0800304#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
305#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
306#define CONFIG_SYS_L2_SIZE (256 << 10)
307#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
308#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
Ying Zhang27585bd2014-01-24 15:50:08 +0800309#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
Ying Zhang7c8eea52013-08-16 15:16:12 +0800310#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
Ying Zhang27585bd2014-01-24 15:50:08 +0800311#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
312#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
Ying Zhang7c8eea52013-08-16 15:16:12 +0800313#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
Ying Zhang5d97fe22013-08-16 15:16:16 +0800314#elif defined(CONFIG_NAND)
315#ifdef CONFIG_TPL_BUILD
316#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
317#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
318#define CONFIG_SYS_L2_SIZE (256 << 10)
319#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
320#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
321#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
322#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
323#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
324#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
325#else
326#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
327#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
328#define CONFIG_SYS_L2_SIZE (256 << 10)
329#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
330#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
331#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
332#endif
Ying Zhang7c8eea52013-08-16 15:16:12 +0800333#endif
334#endif
335
336/*
Timur Tabic59e1b42010-06-14 15:28:24 -0500337 * Serial Port
338 */
Timur Tabic59e1b42010-06-14 15:28:24 -0500339#define CONFIG_SYS_NS16550_SERIAL
340#define CONFIG_SYS_NS16550_REG_SIZE 1
341#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Ying Zhang7c8eea52013-08-16 15:16:12 +0800342#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
Matthew McClintockf45210d2013-02-18 10:02:19 +0000343#define CONFIG_NS16550_MIN_FUNCTIONS
344#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500345
346#define CONFIG_SYS_BAUDRATE_TABLE \
347 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
348
349#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
350#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
351
Timur Tabic59e1b42010-06-14 15:28:24 -0500352/* Video */
Timur Tabiba8e76b2011-04-11 14:18:22 -0500353
Timur Tabid5e01e42010-09-24 01:25:53 +0200354#ifdef CONFIG_FSL_DIU_FB
355#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
Timur Tabid5e01e42010-09-24 01:25:53 +0200356#define CONFIG_VIDEO_LOGO
357#define CONFIG_VIDEO_BMP_LOGO
Timur Tabi55b05232010-09-16 16:35:44 -0500358#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
359/*
360 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
361 * disable empty flash sector detection, which is I/O-intensive.
362 */
363#undef CONFIG_SYS_FLASH_EMPTY_INFO
Timur Tabic59e1b42010-06-14 15:28:24 -0500364#endif
365
Timur Tabiba8e76b2011-04-11 14:18:22 -0500366#ifndef CONFIG_FSL_DIU_FB
Jiang Yutang218a7582011-01-24 18:21:19 +0800367#endif
368
369#ifdef CONFIG_ATI
370#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
Jiang Yutang218a7582011-01-24 18:21:19 +0800371#define CONFIG_BIOSEMU
Jiang Yutang218a7582011-01-24 18:21:19 +0800372#define CONFIG_ATI_RADEON_FB
373#define CONFIG_VIDEO_LOGO
374#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
Jiang Yutang218a7582011-01-24 18:21:19 +0800375#endif
376
Timur Tabic59e1b42010-06-14 15:28:24 -0500377/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200378#define CONFIG_SYS_I2C
379#define CONFIG_SYS_I2C_FSL
380#define CONFIG_SYS_FSL_I2C_SPEED 400000
381#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
382#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
383#define CONFIG_SYS_FSL_I2C2_SPEED 400000
384#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
385#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Timur Tabic59e1b42010-06-14 15:28:24 -0500386#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
Timur Tabic59e1b42010-06-14 15:28:24 -0500387
388/*
389 * I2C2 EEPROM
390 */
391#define CONFIG_ID_EEPROM
392#define CONFIG_SYS_I2C_EEPROM_NXID
393#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
394#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
395#define CONFIG_SYS_EEPROM_BUS_NUM 1
396
397/*
Jiang Yutang9b6e9d12011-02-24 16:11:56 +0800398 * eSPI - Enhanced SPI
399 */
Jiang Yutang9b6e9d12011-02-24 16:11:56 +0800400
401#define CONFIG_HARD_SPI
Jiang Yutang9b6e9d12011-02-24 16:11:56 +0800402
Jiang Yutang9b6e9d12011-02-24 16:11:56 +0800403#define CONFIG_SF_DEFAULT_SPEED 10000000
404#define CONFIG_SF_DEFAULT_MODE 0
405
406/*
Timur Tabic59e1b42010-06-14 15:28:24 -0500407 * General PCI
408 * Memory space is mapped 1-1, but I/O space must start from 0.
409 */
410
411/* controller 1, Slot 2, tgtid 1, Base address a000 */
412#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800413#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500414#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
415#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800416#else
417#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
418#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
419#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500420#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
421#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
422#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800423#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500424#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800425#else
426#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
427#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500428#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
429
430/* controller 2, direct to uli, tgtid 2, Base address 9000 */
431#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800432#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500433#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
434#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800435#else
436#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
437#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
438#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500439#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
440#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
441#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800442#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500443#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800444#else
445#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
446#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500447#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
448
449/* controller 3, Slot 1, tgtid 3, Base address b000 */
450#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800451#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500452#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
453#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800454#else
455#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
456#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
457#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500458#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
459#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
460#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800461#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500462#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800463#else
464#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
465#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500466#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
467
468#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000469#define CONFIG_PCI_INDIRECT_BRIDGE
Timur Tabic59e1b42010-06-14 15:28:24 -0500470#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
471#endif
472
473/* SATA */
Zang Roy-R619119760b272012-11-26 00:05:38 +0000474#define CONFIG_FSL_SATA_V2
Timur Tabic59e1b42010-06-14 15:28:24 -0500475
476#define CONFIG_SYS_SATA_MAX_DEVICE 2
477#define CONFIG_SATA1
478#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
479#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
480#define CONFIG_SATA2
481#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
482#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
483
484#ifdef CONFIG_FSL_SATA
485#define CONFIG_LBA48
Timur Tabic59e1b42010-06-14 15:28:24 -0500486#endif
487
Timur Tabic59e1b42010-06-14 15:28:24 -0500488#ifdef CONFIG_MMC
Timur Tabic59e1b42010-06-14 15:28:24 -0500489#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
490#endif
491
Timur Tabic59e1b42010-06-14 15:28:24 -0500492#ifdef CONFIG_TSEC_ENET
493
494#define CONFIG_TSECV2
Timur Tabic59e1b42010-06-14 15:28:24 -0500495
496#define CONFIG_MII /* MII PHY management */
497#define CONFIG_TSEC1 1
498#define CONFIG_TSEC1_NAME "eTSEC1"
499#define CONFIG_TSEC2 1
500#define CONFIG_TSEC2_NAME "eTSEC2"
501
502#define TSEC1_PHY_ADDR 1
503#define TSEC2_PHY_ADDR 2
504
505#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
506#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
507
508#define TSEC1_PHYIDX 0
509#define TSEC2_PHYIDX 0
510
511#define CONFIG_ETHPRIME "eTSEC1"
Timur Tabic59e1b42010-06-14 15:28:24 -0500512#endif
513
514/*
Yangbo Lu94b383e2014-10-16 10:58:55 +0800515 * Dynamic MTD Partition support with mtdparts
516 */
517#define CONFIG_MTD_DEVICE
518#define CONFIG_MTD_PARTITIONS
Yangbo Lu94b383e2014-10-16 10:58:55 +0800519#define CONFIG_FLASH_CFI_MTD
Yangbo Lu94b383e2014-10-16 10:58:55 +0800520
521/*
Timur Tabic59e1b42010-06-14 15:28:24 -0500522 * Environment
523 */
Ying Zhang382ce7e2013-08-16 15:16:14 +0800524#ifdef CONFIG_SPIFLASH
Matthew McClintockaf253602012-05-18 06:04:17 +0000525#define CONFIG_ENV_SPI_BUS 0
526#define CONFIG_ENV_SPI_CS 0
527#define CONFIG_ENV_SPI_MAX_HZ 10000000
528#define CONFIG_ENV_SPI_MODE 0
529#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
530#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
531#define CONFIG_ENV_SECT_SIZE 0x10000
Ying Zhang7c8eea52013-08-16 15:16:12 +0800532#elif defined(CONFIG_SDCARD)
Ying Zhang7c8eea52013-08-16 15:16:12 +0800533#define CONFIG_FSL_FIXED_MMC_LOCATION
Timur Tabic59e1b42010-06-14 15:28:24 -0500534#define CONFIG_ENV_SIZE 0x2000
Matthew McClintockaf253602012-05-18 06:04:17 +0000535#define CONFIG_SYS_MMC_ENV_DEV 0
Matthew McClintockf45210d2013-02-18 10:02:19 +0000536#elif defined(CONFIG_NAND)
Ying Zhang5d97fe22013-08-16 15:16:16 +0800537#ifdef CONFIG_TPL_BUILD
538#define CONFIG_ENV_SIZE 0x2000
539#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
540#else
Matthew McClintockaf253602012-05-18 06:04:17 +0000541#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Ying Zhang5d97fe22013-08-16 15:16:16 +0800542#endif
Ying Zhang5d97fe22013-08-16 15:16:16 +0800543#define CONFIG_ENV_OFFSET (1024 * 1024)
Matthew McClintockaf253602012-05-18 06:04:17 +0000544#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
Matthew McClintockf45210d2013-02-18 10:02:19 +0000545#elif defined(CONFIG_SYS_RAMBOOT)
Matthew McClintockaf253602012-05-18 06:04:17 +0000546#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
547#define CONFIG_ENV_SIZE 0x2000
Matthew McClintockaf253602012-05-18 06:04:17 +0000548#else
Matthew McClintockaf253602012-05-18 06:04:17 +0000549#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Matthew McClintockaf253602012-05-18 06:04:17 +0000550#define CONFIG_ENV_SIZE 0x2000
551#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
552#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500553
554#define CONFIG_LOADS_ECHO
555#define CONFIG_SYS_LOADS_BAUD_CHANGE
556
557/*
Timur Tabic59e1b42010-06-14 15:28:24 -0500558 * USB
559 */
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000560#define CONFIG_HAS_FSL_DR_USB
561#ifdef CONFIG_HAS_FSL_DR_USB
Tom Rini8850c5d2017-05-12 22:33:27 -0400562#ifdef CONFIG_USB_EHCI_HCD
Timur Tabic59e1b42010-06-14 15:28:24 -0500563#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
564#define CONFIG_USB_EHCI_FSL
Timur Tabic59e1b42010-06-14 15:28:24 -0500565#endif
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000566#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500567
568/*
569 * Miscellaneous configurable options
570 */
Timur Tabic59e1b42010-06-14 15:28:24 -0500571#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Timur Tabic59e1b42010-06-14 15:28:24 -0500572
573/*
574 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500575 * have to be in the first 64 MB of memory, since this is
Timur Tabic59e1b42010-06-14 15:28:24 -0500576 * the maximum mapped by the Linux kernel during initialization.
577 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500578#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
579#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Timur Tabic59e1b42010-06-14 15:28:24 -0500580
Timur Tabic59e1b42010-06-14 15:28:24 -0500581#ifdef CONFIG_CMD_KGDB
582#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Timur Tabic59e1b42010-06-14 15:28:24 -0500583#endif
584
585/*
586 * Environment Configuration
587 */
588
Mario Six5bc05432018-03-28 14:38:20 +0200589#define CONFIG_HOSTNAME "p1022ds"
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000590#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000591#define CONFIG_BOOTFILE "uImage"
Timur Tabic59e1b42010-06-14 15:28:24 -0500592#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
593
594#define CONFIG_LOADADDR 1000000
595
Timur Tabi84e34b62012-05-04 12:21:29 +0000596#define CONFIG_EXTRA_ENV_SETTINGS \
597 "netdev=eth0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200598 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
599 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
Timur Tabi84e34b62012-05-04 12:21:29 +0000600 "tftpflash=tftpboot $loadaddr $uboot && " \
601 "protect off $ubootaddr +$filesize && " \
602 "erase $ubootaddr +$filesize && " \
603 "cp.b $loadaddr $ubootaddr $filesize && " \
604 "protect on $ubootaddr +$filesize && " \
605 "cmp.b $loadaddr $ubootaddr $filesize\0" \
606 "consoledev=ttyS0\0" \
607 "ramdiskaddr=2000000\0" \
608 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
Scott Woodb24a4f62016-07-19 17:52:06 -0500609 "fdtaddr=1e00000\0" \
Timur Tabi84e34b62012-05-04 12:21:29 +0000610 "fdtfile=p1022ds.dtb\0" \
611 "bdev=sda3\0" \
Timur Tabiba8e76b2011-04-11 14:18:22 -0500612 "hwconfig=esdhc;audclk:12\0"
Timur Tabic59e1b42010-06-14 15:28:24 -0500613
614#define CONFIG_HDBOOT \
615 "setenv bootargs root=/dev/$bdev rw " \
Timur Tabi84e34b62012-05-04 12:21:29 +0000616 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
Timur Tabic59e1b42010-06-14 15:28:24 -0500617 "tftp $loadaddr $bootfile;" \
618 "tftp $fdtaddr $fdtfile;" \
619 "bootm $loadaddr - $fdtaddr"
620
621#define CONFIG_NFSBOOTCOMMAND \
622 "setenv bootargs root=/dev/nfs rw " \
623 "nfsroot=$serverip:$rootpath " \
624 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
Timur Tabi84e34b62012-05-04 12:21:29 +0000625 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
Timur Tabic59e1b42010-06-14 15:28:24 -0500626 "tftp $loadaddr $bootfile;" \
627 "tftp $fdtaddr $fdtfile;" \
628 "bootm $loadaddr - $fdtaddr"
629
630#define CONFIG_RAMBOOTCOMMAND \
631 "setenv bootargs root=/dev/ram rw " \
Timur Tabi84e34b62012-05-04 12:21:29 +0000632 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
Timur Tabic59e1b42010-06-14 15:28:24 -0500633 "tftp $ramdiskaddr $ramdiskfile;" \
634 "tftp $loadaddr $bootfile;" \
635 "tftp $fdtaddr $fdtfile;" \
636 "bootm $loadaddr $ramdiskaddr $fdtaddr"
637
638#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
639
640#endif