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wdenk0f8c9762002-08-19 11:57:05 +00001/*
2 * Parameters for GTH board
3 * Based on FADS860T
4 * by thomas.lange@corelatus.com
5
6 * A collection of structures, addresses, and values associated with
7 * the Motorola 860T FADS board. Copied from the MBX stuff.
8 * Magnus Damm added defines for 8xxrom and extended bd_info.
9 * Helmut Buchsbaum added bitvalues for BCSRx
10 *
11 * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
12 */
13
14/*
15 * ff000000 -> ff00ffff : IMAP internal in the cpu
16 * e0000000 -> ennnnnnn : pcmcia
17 * 98000000 -> 983nnnnn : FPGA 4MB
18 * 90000000 -> 903nnnnn : FPGA 4MB
19 * 80000000 -> 80nnnnnn : flash connected to CS0, final ( real ) location
20 * 00000000 -> nnnnnnnn : sdram
21 */
22
23/* ------------------------------------------------------------------------- */
24
25/*
26 * board/config.h - configuration options, board specific
27 */
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32/*
33 * High Level Configuration Options
34 * (easy to change)
35 */
36#include <mpc8xx_irq.h>
37
38#define CONFIG_MPC860 1
39#define CONFIG_MPC860T 1
40#define CONFIG_GTH 1
41
42#define CONFIG_MISC_INIT_R 1
43
44#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
45#undef CONFIG_8xx_CONS_SMC2
46#undef CONFIG_8xx_CONS_NONE
47#define CONFIG_BAUDRATE 9600
48#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
49
50#define MPC8XX_FACT 3 /* Multiply by 3 */
51#define MPC8XX_XIN 16384000 /* 16.384 MHz */
52#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
53
54#define CONFIG_BOOTDELAY 1 /* autoboot after 0 seconds */
55
56#define CONFIG_ENV_OVERWRITE 1 /* Allow change of ethernet address */
57
58#define CONFIG_BOOT_RETRY_TIME 5 /* Retry boot in 5 secs */
59
60#define CONFIG_RESET_TO_RETRY 1 /* If timeout waiting for command, perform a reset */
61
62/* Only interrupt boot if space is pressed */
63/* If a long serial cable is connected but */
64/* other end is dead, garbage will be read */
65#define CONFIG_AUTOBOOT_KEYED 1
66#define CONFIG_AUTOBOOT_PROMPT "Press space to abort autoboot in %d second\n"
67#define CONFIG_AUTOBOOT_DELAY_STR "d"
68#define CONFIG_AUTOBOOT_STOP_STR " "
69
70#if 0
71/* Net boot */
72/* Loads a tftp image and starts it */
73#define CONFIG_BOOTCOMMAND "bootp;bootm 100000" /* autoboot command */
74#define CONFIG_BOOTARGS "panic=1"
75#else
76/* Compact flash boot */
77#define CONFIG_BOOTARGS "panic=1 root=/dev/hda7"
78#define CONFIG_BOOTCOMMAND "disk 100000 0:5;bootm 100000"
79#endif
80
81/* Enable watchdog */
82#define CONFIG_WATCHDOG 1
83
84/* choose SCC1 ethernet (10BASET on motherboard)
85 * or FEC ethernet (10/100 on daughterboard)
86 */
87#if 1
88#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */
89#undef CONFIG_FEC_ENET /* disable FEC ethernet */
90#define CFG_DISCOVER_PHY
91#else
92#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
93#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
94#define CFG_DISCOVER_PHY
95#endif
96#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
97#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
98#endif
99
Jon Loeliger60a08762007-07-07 21:04:26 -0500100
101/*
Jon Loeliger11799432007-07-10 09:02:57 -0500102 * BOOTP options
103 */
104#define CONFIG_BOOTP_BOOTFILESIZE
105#define CONFIG_BOOTP_BOOTPATH
106#define CONFIG_BOOTP_GATEWAY
107#define CONFIG_BOOTP_HOSTNAME
108
109
110/*
Jon Loeliger60a08762007-07-07 21:04:26 -0500111 * Command line configuration.
112 */
113#include <config_cmd_default.h>
114
115#define CONFIG_CMD_IDE
116
117
wdenk0f8c9762002-08-19 11:57:05 +0000118#define CONFIG_MAC_PARTITION
119#define CONFIG_DOS_PARTITION
120
wdenk0f8c9762002-08-19 11:57:05 +0000121/*
122 * Miscellaneous configurable options
123 */
124#define CFG_PROMPT "=>" /* Monitor Command Prompt */
Jon Loeliger60a08762007-07-07 21:04:26 -0500125#if defined(CONFIG_CMD_KGDB)
wdenk0f8c9762002-08-19 11:57:05 +0000126#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
127#else
128#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
129#endif
130#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
131#define CFG_MAXARGS 16 /* max number of command args */
132#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
133
134#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
135#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
136
137/* Default location to load data from net */
138#define CFG_LOAD_ADDR 0x100000
139
140#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
141
142#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400 }
143
144/*
145 * Low Level Configuration Settings
146 * (address mappings, register initial values, etc.)
147 * You should know what you are doing if you make changes here.
148 */
149/*-----------------------------------------------------------------------
150 * Internal Memory Mapped Register
151 */
152#define CFG_IMMR 0xFF000000
153#define CFG_IMMR_SIZE ((uint)(64 * 1024))
154
155/*-----------------------------------------------------------------------
156 * Definitions for initial stack pointer and data area (in DPRAM)
157 */
158#define CFG_INIT_RAM_ADDR CFG_IMMR
159#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
160#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
161#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
162#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
163
164/*-----------------------------------------------------------------------
165 * Start addresses for the final memory configuration
166 * (Set up by the startup code)
167 * Please note that CFG_SDRAM_BASE _must_ start at 0
168 */
169#define CFG_SDRAM_BASE 0x00000000
170
171#define CFG_FLASH_BASE 0x80000000
172
173#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
174
175#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
176
177#define CFG_MONITOR_BASE TEXT_BASE
178
179#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
180
181/*
182 * For booting Linux, the board info and command line data
183 * have to be in the first 8 MB of memory, since this is
184 * the maximum mapped by the Linux kernel during initialization.
185 */
186#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
187/*-----------------------------------------------------------------------
188 * FLASH organization
189 */
190#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
191#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
192
193#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
194#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
195
196#define CFG_ENV_IS_IN_FLASH 1
197#undef CFG_ENV_IS_IN_EEPROM
198#define CFG_ENV_OFFSET 0x000E0000
199#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
200
201#define CFG_ENV_SECT_SIZE 0x50000 /* see README - env sector total size */
202
203/*-----------------------------------------------------------------------
204 * Cache Configuration
205 */
206#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger60a08762007-07-07 21:04:26 -0500207#if defined(CONFIG_CMD_KGDB)
wdenk0f8c9762002-08-19 11:57:05 +0000208#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
209#endif
210
211/*-----------------------------------------------------------------------
212 * SYPCR - System Protection Control 11-9
213 * SYPCR can only be written once after reset!
214 *-----------------------------------------------------------------------
215 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
216 */
217#if defined(CONFIG_WATCHDOG)
218#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
219 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
220#else
221#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
222#endif
223
224/*-----------------------------------------------------------------------
225 * SIUMCR - SIU Module Configuration 11-6
226 *-----------------------------------------------------------------------
227 * PCMCIA config., multi-function pin tri-state
228 */
229#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
230
231/*-----------------------------------------------------------------------
232 * TBSCR - Time Base Status and Control 11-26
233 *-----------------------------------------------------------------------
234 * Clear Reference Interrupt Status, Timebase freezing enabled
235 */
236#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
237
238/*----------------------------------------------------------------------
239 * RTCSC - Real-Time Clock Status and Control Register 11-27
240 *-----------------------------------------------------------------------
241 */
242
243/*FIXME dont use for now */
244/*#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
245/*#define CFG_RTCSC (RTCSC_RTF) */
246
247/*-----------------------------------------------------------------------
248 * PISCR - Periodic Interrupt Status and Control 11-31
249 *-----------------------------------------------------------------------
250 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
251 */
252#define CFG_PISCR (PISCR_PS | PISCR_PITF)
253/* PITE */
254/*-----------------------------------------------------------------------
255 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
256 *-----------------------------------------------------------------------
257 * set the PLL, the low-power modes and the reset control (15-29)
258 */
259#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
260 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
261
262/*-----------------------------------------------------------------------
263 * SCCR - System Clock and reset Control Register 15-27
264 *-----------------------------------------------------------------------
265 * Set clock output, timebase and RTC source and divider,
266 * power management and some other internal clocks
267 */
268
269/* FIXME check values */
270#define SCCR_MASK SCCR_EBDF11
271#define CFG_SCCR (SCCR_TBS|SCCR_RTSEL|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
272
273 /*-----------------------------------------------------------------------
274 *
275 *-----------------------------------------------------------------------
276 *
277 */
278#define CFG_DER 0
279
280/* Because of the way the 860 starts up and assigns CS0 the
281* entire address space, we have to set the memory controller
282* differently. Normally, you write the option register
283* first, and then enable the chip select by writing the
284* base register. For CS0, you must write the base register
285* first, followed by the option register.
286*/
287
288/*
289 * Init Memory Controller:
290 *
291 * BR0/1 and OR0/1 (FLASH)
292 */
293/* the other CS:s are determined by looking at parameters in BCSRx */
294
295#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
296
297#define CFG_REMAP_OR_AM 0xFF800000 /* 4 MB OR addr mask */
298#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
299
300#define FPGA_2_BASE 0x90000000
301#define FPGA_3_BASE 0x98000000
302
303/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
304#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
305
306#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
307
308
309#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/
310#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16 )
311
312/*
313 * Internal Definitions
314 *
315 * Boot Flags
316 */
317#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
318#define BOOTFLAG_WARM 0x02 /* Software reboot */
319
320#define CONFIG_ETHADDR DE:AD:BE:EF:00:01 /* Ethernet address */
321
322#ifdef CONFIG_MPC860T
323
324/* Interrupt level assignments.
325*/
326#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
327
328#endif /* CONFIG_MPC860T */
329
330/* We don't use the 8259.
331*/
332#define NR_8259_INTS 0
333
334/* Machine type
335*/
336#define _MACH_8xx (_MACH_gth)
337
338#ifdef CONFIG_MPC860
339#define PCMCIA_SLOT_A 1
340#define CONFIG_PCMCIA_SLOT_A 1
341#endif
342
343#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
344#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
345#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
346#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
347#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
348#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
349#define CFG_PCMCIA_IO_ADDR (0xEC000000)
350#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
351
352#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
353#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
354#undef CONFIG_IDE_LED /* LED for ide not supported */
355#undef CONFIG_IDE_RESET /* reset for ide not supported */
356
357#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
358#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
359
360#define CFG_ATA_IDE0_OFFSET 0x0000
361#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
362/* Offset for data I/O */
363#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
364/* Offset for normal register accesses */
365#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
366/* Offset for alternate registers */
367#define CFG_ATA_ALT_OFFSET 0x0100
368
369#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */
370
371#define PA_FRONT_LED ((u16)0x4) /* PA 13 */
372#define PA_FL_CONFIG ((u16)0x20) /* PA 10 */
373#define PA_FL_CE ((u16)0x1000) /* PA 3 */
374
375#define PB_ID_GND ((u32)1) /* PB 31 */
376#define PB_REV_1 ((u32)2) /* PB 30 */
377#define PB_REV_0 ((u32)4) /* PB 29 */
378#define PB_BLUE_LED ((u32)0x400) /* PB 21 */
379#define PB_EEPROM ((u32)0x800) /* PB 20 */
380#define PB_ID_3 ((u32)0x2000) /* PB 18 */
381#define PB_ID_2 ((u32)0x4000) /* PB 17 */
382#define PB_ID_1 ((u32)0x8000) /* PB 16 */
383#define PB_ID_0 ((u32)0x10000) /* PB 15 */
384
385/* NOTE. This is reset for 100Mbit port only */
386#define PC_ENET100_RESET ((ushort)0x0080) /* PC 8 */
387
388#endif /* __CONFIG_H */