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Stefan Roese899620c2006-08-15 14:22:35 +02001/*
Stefan Roese63044302007-01-30 12:51:07 +01002 * (C) Copyright 2006-2007
Stefan Roese899620c2006-08-15 14:22:35 +02003 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*-----------------------------------------------------------------------
28 * High Level Configuration Options
29 *----------------------------------------------------------------------*/
30#define CONFIG_ALPR 1 /* Board is ebony */
31#define CONFIG_440GX 1 /* Specifc GX support */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +020032#define CONFIG_440 1 /* ... PPC440 family */
Stefan Roese899620c2006-08-15 14:22:35 +020033#define CONFIG_4xx 1 /* ... PPC4xx family */
34#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
Stefan Roese1c2ce222006-11-27 14:12:17 +010035#define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */
Stefan Roese899620c2006-08-15 14:22:35 +020036#undef CFG_DRAM_TEST /* Disable-takes long time! */
Stefan Roese1c2ce222006-11-27 14:12:17 +010037#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
Stefan Roese899620c2006-08-15 14:22:35 +020038
39/*-----------------------------------------------------------------------
40 * Base addresses -- Note these are effective addresses where the
41 * actual resources get mapped (not physical addresses)
42 *----------------------------------------------------------------------*/
Stefan Roese1c2ce222006-11-27 14:12:17 +010043#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
44#define CFG_FLASH_BASE 0xffe00000 /* start of FLASH */
45#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
46#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
47#define CFG_PCI_MEMSIZE 0x40000000 /* size of mapped pci memory */
48#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
49#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
50#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
51#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
52#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
53#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
Stefan Roese899620c2006-08-15 14:22:35 +020054
55
56#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000)
57#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
58
59/*-----------------------------------------------------------------------
60 * Initial RAM & stack pointer (placed in internal SRAM)
61 *----------------------------------------------------------------------*/
62#define CFG_TEMP_STACK_OCM 1
63#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
64#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
65#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
66#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
67
68#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
69#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
70#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
71
72#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
73#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
74
75/*-----------------------------------------------------------------------
76 * Serial Port
77 *----------------------------------------------------------------------*/
78#undef CFG_EXT_SERIAL_CLOCK
79#define CONFIG_BAUDRATE 115200
80#define CONFIG_UART1_CONSOLE /* define for uart1 as console */
81
82#define CFG_BAUDRATE_TABLE \
83 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
84
85/*-----------------------------------------------------------------------
Stefan Roese899620c2006-08-15 14:22:35 +020086 * FLASH related
87 *----------------------------------------------------------------------*/
Stefan Roese1c2ce222006-11-27 14:12:17 +010088#define CFG_FLASH_CFI 1 /* The flash is CFI compatible */
89#define CFG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */
Stefan Roese899620c2006-08-15 14:22:35 +020090#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
Stefan Roese1c2ce222006-11-27 14:12:17 +010091#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
92#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
Stefan Roese899620c2006-08-15 14:22:35 +020093#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Stefan Roese1c2ce222006-11-27 14:12:17 +010094#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
Stefan Roese899620c2006-08-15 14:22:35 +020095
96#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
97
Wolfgang Denk1636d1c2007-06-22 23:59:00 +020098#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
Stefan Roese899620c2006-08-15 14:22:35 +020099#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
100#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
101
102/* Address and size of Redundant Environment Sector */
103#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
104#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
105
106/*-----------------------------------------------------------------------
107 * DDR SDRAM
108 *----------------------------------------------------------------------*/
109#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
110#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0 */
111#undef CONFIG_SDRAM_ECC /* enable ECC support */
112#define CFG_SDRAM_TABLE { \
113 {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
114 {(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */
115
116/*-----------------------------------------------------------------------
117 * I2C
118 *----------------------------------------------------------------------*/
119#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
120#undef CONFIG_SOFT_I2C /* I2C bit-banged */
121#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
122#define CFG_I2C_SLAVE 0x7F
123#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
124
125/*-----------------------------------------------------------------------
126 * I2C EEPROM (PCF8594C)
127 *----------------------------------------------------------------------*/
128#define CFG_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */
129#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
130/* mask of address bits that overflow into the "EEPROM chip address" */
131#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
132#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */
133 /* 8 byte page write mode using */
134 /* last 3 bits of the address */
135#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */
136#define CFG_EEPROM_PAGE_WRITE_ENABLE
137
138#define CONFIG_PREBOOT "echo;" \
Stefan Roese63044302007-01-30 12:51:07 +0100139 "echo Type \"run kernelx\" to boot the system;" \
Stefan Roese899620c2006-08-15 14:22:35 +0200140 "echo"
141
142#undef CONFIG_BOOTARGS
143
144#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roese1c2ce222006-11-27 14:12:17 +0100145 "netdev=eth3\0" \
Stefan Roese899620c2006-08-15 14:22:35 +0200146 "hostname=alpr\0" \
147 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Stefan Roese63044302007-01-30 12:51:07 +0100148 "nfsroot=${serverip}:${rootpath} ${init}\0" \
Stefan Roese899620c2006-08-15 14:22:35 +0200149 "ramargs=setenv bootargs root=/dev/ram rw\0" \
150 "addip=setenv bootargs ${bootargs} " \
151 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
152 ":${hostname}:${netdev}:off panic=1\0" \
Stefan Roese1c2ce222006-11-27 14:12:17 +0100153 "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate} " \
154 "mem=193M\0" \
Stefan Roese899620c2006-08-15 14:22:35 +0200155 "flash_nfs=run nfsargs addip addtty;" \
156 "bootm ${kernel_addr}\0" \
157 "flash_self=run ramargs addip addtty;" \
158 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
159 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
160 "bootm\0" \
Stefan Roese1c2ce222006-11-27 14:12:17 +0100161 "rootpath=/opt/projects/alpr/nfs_root\0" \
162 "bootfile=/alpr/uImage\0" \
Stefan Roese899620c2006-08-15 14:22:35 +0200163 "kernel_addr=fff00000\0" \
164 "ramdisk_addr=fff10000\0" \
Stefan Roese1c2ce222006-11-27 14:12:17 +0100165 "load=tftp 100000 /alpr/u-boot/u-boot.bin\0" \
Stefan Roese899620c2006-08-15 14:22:35 +0200166 "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
167 "cp.b 100000 fffc0000 40000;" \
168 "setenv filesize;saveenv\0" \
169 "upd=run load;run update\0" \
Stefan Roesef16c1da2007-01-06 15:56:13 +0100170 "ethprime=ppc_4xx_eth3\0" \
171 "ethact=ppc_4xx_eth3\0" \
172 "autoload=no\0" \
173 "ipconfig=dhcp;setenv serverip 11.0.0.152\0" \
Stefan Roesef16c1da2007-01-06 15:56:13 +0100174 "load_fpga=fpga load 0 ffe00000 10dd9a\0" \
175 "mtdargs=setenv bootargs root=/dev/mtdblock6 rw " \
176 "rootfstype=jffs2 init=/sbin/init\0" \
177 "kernel1_mtd=nand read 200000 0 200000;run mtdargs addip addtty"\
178 ";bootm 200000\0" \
179 "kernel2_mtd=nand read 200000 200000 200000;run mtdargs addip " \
180 "addtty;bootm 200000\0" \
Stefan Roese63044302007-01-30 12:51:07 +0100181 "kernel1=setenv actkernel 'kernel1';run load_fpga " \
182 "kernel1_mtd\0" \
183 "kernel2=setenv actkernel 'kernel2';run load_fpga " \
184 "kernel2_mtd\0" \
Stefan Roese899620c2006-08-15 14:22:35 +0200185 ""
Stefan Roesef16c1da2007-01-06 15:56:13 +0100186
187#define CONFIG_BOOTCOMMAND "run kernel2"
Stefan Roese899620c2006-08-15 14:22:35 +0200188
Stefan Roese1c2ce222006-11-27 14:12:17 +0100189#define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */
Stefan Roese899620c2006-08-15 14:22:35 +0200190
191#define CONFIG_BAUDRATE 115200
192
193#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
194#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
195
196#define CONFIG_MII 1 /* MII PHY management */
197#define CONFIG_NET_MULTI 1
198#define CONFIG_PHY_ADDR 0x02 /* dummy setting, no EMAC0 used */
199#define CONFIG_PHY1_ADDR 0x03 /* dummy setting, no EMAC1 used */
Stefan Roese1c2ce222006-11-27 14:12:17 +0100200#define CONFIG_PHY2_ADDR 0x01 /* PHY address for EMAC2 */
201#define CONFIG_PHY3_ADDR 0x02 /* PHY address for EMAC3 */
Stefan Roese899620c2006-08-15 14:22:35 +0200202#define CONFIG_HAS_ETH0
203#define CONFIG_HAS_ETH1
204#define CONFIG_HAS_ETH2
205#define CONFIG_HAS_ETH3
206#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
Stefan Roeseec0c2ec2006-11-27 14:46:06 +0100207#define CONFIG_M88E1111_PHY 1 /* needed for PHY specific setup*/
Stefan Roese899620c2006-08-15 14:22:35 +0200208#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
Stefan Roese5bc528f2006-10-07 11:35:25 +0200209#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
Stefan Roese899620c2006-08-15 14:22:35 +0200210
Stefan Roese5bc528f2006-10-07 11:35:25 +0200211#define CONFIG_NETCONSOLE /* include NetConsole support */
212
Stefan Roese899620c2006-08-15 14:22:35 +0200213
Jon Loeliger0b361c92007-07-04 22:31:42 -0500214/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500215 * BOOTP options
216 */
217#define CONFIG_BOOTP_BOOTFILESIZE
218#define CONFIG_BOOTP_BOOTPATH
219#define CONFIG_BOOTP_GATEWAY
220#define CONFIG_BOOTP_HOSTNAME
221
222
223/*
Jon Loeliger0b361c92007-07-04 22:31:42 -0500224 * Command line configuration.
225 */
226#include <config_cmd_default.h>
227
228#define CONFIG_CMD_ASKENV
229#define CONFIG_CMD_DHCP
230#define CONFIG_CMD_DIAG
231#define CONFIG_CMD_EEPROM
232#define CONFIG_CMD_ELF
233#define CONFIG_CMD_FPGA
234#define CONFIG_CMD_I2C
235#define CONFIG_CMD_IRQ
236#define CONFIG_CMD_MII
237#define CONFIG_CMD_NAND
238#define CONFIG_CMD_NET
239#define CONFIG_CMD_NFS
240#define CONFIG_CMD_PCI
241#define CONFIG_CMD_PING
242#define CONFIG_CMD_REGINFO
243
Stefan Roese899620c2006-08-15 14:22:35 +0200244
245#undef CONFIG_WATCHDOG /* watchdog disabled */
246
247/*
248 * Miscellaneous configurable options
249 */
250#define CFG_LONGHELP /* undef to save memory */
251#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger0b361c92007-07-04 22:31:42 -0500252#if defined(CONFIG_CMD_KGDB)
Stefan Roese899620c2006-08-15 14:22:35 +0200253#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
254#else
255#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
256#endif
257#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
258#define CFG_MAXARGS 16 /* max number of command args */
259#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
260
Stefan Roese63044302007-01-30 12:51:07 +0100261#define CFG_ALT_MEMTEST 1 /* Enable more extensive memtest*/
Stefan Roese899620c2006-08-15 14:22:35 +0200262#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
263#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
264
265#define CFG_LOAD_ADDR 0x100000 /* default load address */
266#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
267
268#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
269
Stefan Roese5bc528f2006-10-07 11:35:25 +0200270#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Stefan Roese899620c2006-08-15 14:22:35 +0200271#define CONFIG_LOOPW 1 /* enable loopw command */
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200272#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
Stefan Roese899620c2006-08-15 14:22:35 +0200273#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
Stefan Roese1c2ce222006-11-27 14:12:17 +0100274#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
275
276#define CFG_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
Stefan Roese899620c2006-08-15 14:22:35 +0200277
Stefan Roese899620c2006-08-15 14:22:35 +0200278/*-----------------------------------------------------------------------
279 * PCI stuff
280 *-----------------------------------------------------------------------
281 */
282/* General PCI */
283#define CONFIG_PCI /* include pci support */
284#define CONFIG_PCI_PNP /* do pci plug-and-play */
285#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
286#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
Stefan Roese1c2ce222006-11-27 14:12:17 +0100287#define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/
Stefan Roese899620c2006-08-15 14:22:35 +0200288
289/* Board-specific PCI */
Stefan Roese899620c2006-08-15 14:22:35 +0200290#define CFG_PCI_TARGET_INIT /* let board init pci target */
291#define CFG_PCI_MASTER_INIT
292
293#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
294#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
295
296/*-----------------------------------------------------------------------
297 * FPGA stuff
Stefan Roese1c2ce222006-11-27 14:12:17 +0100298 *-----------------------------------------------------------------------*/
Stefan Roese899620c2006-08-15 14:22:35 +0200299#define CONFIG_FPGA CFG_ALTERA_CYCLON2
Stefan Roese1c2ce222006-11-27 14:12:17 +0100300#define CFG_FPGA_CHECK_CTRLC
301#define CFG_FPGA_PROG_FEEDBACK
Stefan Roese899620c2006-08-15 14:22:35 +0200302#define CONFIG_FPGA_COUNT 1 /* Ich habe 2 ... aber in
303 Reihe geschaltet -> sollte gehen,
304 aufpassen mit Datasize ist jetzt
305 halt doppelt so gross ... Seite 306
306 ist das mit den multiple Device in PS
307 Mode erklaert ...*/
308
Stefan Roese899620c2006-08-15 14:22:35 +0200309/* FPGA program pin configuration */
310#define CFG_GPIO_CLK 18 /* FPGA clk pin (cpu output) */
311#define CFG_GPIO_DATA 19 /* FPGA data pin (cpu output) */
312#define CFG_GPIO_STATUS 20 /* FPGA status pin (cpu input) */
313#define CFG_GPIO_CONFIG 21 /* FPGA CONFIG pin (cpu output) */
314#define CFG_GPIO_CON_DON 22 /* FPGA CONFIG_DONE pin (cpu input) */
315
316#define CFG_GPIO_SEL_DPR 14 /* cpu output */
317#define CFG_GPIO_SEL_AVR 15 /* cpu output */
318#define CFG_GPIO_PROG_EN 23 /* cpu output */
319
Stefan Roese1c2ce222006-11-27 14:12:17 +0100320/*-----------------------------------------------------------------------
321 * Definitions for GPIO setup
322 *-----------------------------------------------------------------------*/
Stefan Roesef16c1da2007-01-06 15:56:13 +0100323#define CFG_GPIO_SHUTDOWN (0x80000000 >> 6)
324#define CFG_GPIO_SSD_EMPTY (0x80000000 >> 9)
Stefan Roese1c2ce222006-11-27 14:12:17 +0100325#define CFG_GPIO_EREADY (0x80000000 >> 26)
326#define CFG_GPIO_REV0 (0x80000000 >> 14)
327#define CFG_GPIO_REV1 (0x80000000 >> 15)
328
329/*-----------------------------------------------------------------------
Stefan Roese899620c2006-08-15 14:22:35 +0200330 * NAND-FLASH stuff
Stefan Roese1c2ce222006-11-27 14:12:17 +0100331 *-----------------------------------------------------------------------*/
Stefan Roese5bc528f2006-10-07 11:35:25 +0200332#define CFG_MAX_NAND_DEVICE 4
333#define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE
334#define CFG_NAND_BASE 0xF0000000 /* NAND FLASH Base Address */
335#define CFG_NAND_BASE_LIST { CFG_NAND_BASE + 0, CFG_NAND_BASE + 2, \
336 CFG_NAND_BASE + 4, CFG_NAND_BASE + 6 }
337#define CFG_NAND_QUIET_TEST 1 /* don't warn upon unknown NAND flash */
Stefan Roese899620c2006-08-15 14:22:35 +0200338
339/*-----------------------------------------------------------------------
340 * External Bus Controller (EBC) Setup
341 *----------------------------------------------------------------------*/
342#define CFG_FLASH CFG_FLASH_BASE
343
344/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
345#define CFG_EBC_PB0AP 0x92015480
346#define CFG_EBC_PB0CR (CFG_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */
Stefan Roese899620c2006-08-15 14:22:35 +0200347
Stefan Roese5bc528f2006-10-07 11:35:25 +0200348/* Memory Bank 1 (NAND-FLASH) initialization */
349#define CFG_EBC_PB1AP 0x01840380 /* TWT=3 */
Stefan Roese1c2ce222006-11-27 14:12:17 +0100350#define CFG_EBC_PB1CR (CFG_NAND_BASE | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */
Stefan Roese899620c2006-08-15 14:22:35 +0200351
352/*
353 * For booting Linux, the board info and command line data
354 * have to be in the first 8 MB of memory, since this is
355 * the maximum mapped by the Linux kernel during initialization.
356 */
357#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
358/*-----------------------------------------------------------------------
359 * Cache Configuration
360 */
361#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */
362#define CFG_CACHELINE_SIZE 32 /* ... */
Stefan Roese899620c2006-08-15 14:22:35 +0200363#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Stefan Roese899620c2006-08-15 14:22:35 +0200364
365/*
366 * Internal Definitions
367 *
368 * Boot Flags
369 */
370#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
371#define BOOTFLAG_WARM 0x02 /* Software reboot */
372
Jon Loeliger0b361c92007-07-04 22:31:42 -0500373#if defined(CONFIG_CMD_KGDB)
Stefan Roese899620c2006-08-15 14:22:35 +0200374#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
375#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
376#endif
377#endif /* __CONFIG_H */