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stroese46578cc2003-05-23 11:28:55 +00001/*
Stefan Roese8a316c92005-08-01 16:49:12 +02002 * (C) Copyright 2000-2005
stroese46578cc2003-05-23 11:28:55 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
stroese46578cc2003-05-23 11:28:55 +000031/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405EP 1 /* This is a PPC405 CPU */
37#define CONFIG_4xx 1 /* ...member of PPC4xx family */
Stefan Roese8a316c92005-08-01 16:49:12 +020038#define CONFIG_BUBINGA 1 /* ...on a BUBINGA board */
stroese46578cc2003-05-23 11:28:55 +000039
wdenkc837dcb2004-01-20 23:12:12 +000040#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
stroese46578cc2003-05-23 11:28:55 +000041
42#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
43
44#define CONFIG_NO_SERIAL_EEPROM
45/*#undef CONFIG_NO_SERIAL_EEPROM*/
46/*----------------------------------------------------------------------------*/
stroese46578cc2003-05-23 11:28:55 +000047#ifdef CONFIG_NO_SERIAL_EEPROM
48
49/*
50!-------------------------------------------------------------------------------
51! Defines for entry options.
52! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
53! are plugged in the board will be utilized as non-ECC DIMMs.
54!-------------------------------------------------------------------------------
55*/
56#define AUTO_MEMORY_CONFIG
57#define DIMM_READ_ADDR 0xAB
58#define DIMM_WRITE_ADDR 0xAA
59
60/*
61!-------------------------------------------------------------------------------
62! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
63! assuming a 33MHz input clock to the 405EP from the C9531.
64!-------------------------------------------------------------------------------
65*/
66#define PLLMR0_DEFAULT PLLMR0_266_133_66
67#define PLLMR1_DEFAULT PLLMR1_266_133_66
68
69#endif
70/*----------------------------------------------------------------------------*/
stroese46578cc2003-05-23 11:28:55 +000071
Stefan Roese8a316c92005-08-01 16:49:12 +020072/*
73 * Define here the location of the environment variables (FLASH or NVRAM).
74 * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
75 * supported for backward compatibility.
76 */
77#if 1
78#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
stroese46578cc2003-05-23 11:28:55 +000079#else
Stefan Roese8a316c92005-08-01 16:49:12 +020080#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
stroese46578cc2003-05-23 11:28:55 +000081#endif
Stefan Roese8a316c92005-08-01 16:49:12 +020082
83#define CONFIG_PREBOOT "echo;" \
84 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
85 "echo"
86
87#undef CONFIG_BOOTARGS
88
89#define CONFIG_EXTRA_ENV_SETTINGS \
90 "netdev=eth0\0" \
91 "hostname=bubinga\0" \
92 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010093 "nfsroot=${serverip}:${rootpath}\0" \
Stefan Roese8a316c92005-08-01 16:49:12 +020094 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010095 "addip=setenv bootargs ${bootargs} " \
96 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
97 ":${hostname}:${netdev}:off panic=1\0" \
98 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
Stefan Roese8a316c92005-08-01 16:49:12 +020099 "flash_nfs=run nfsargs addip addtty;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100100 "bootm ${kernel_addr}\0" \
Stefan Roese8a316c92005-08-01 16:49:12 +0200101 "flash_self=run ramargs addip addtty;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100102 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
103 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
Stefan Roese8a316c92005-08-01 16:49:12 +0200104 "bootm\0" \
105 "rootpath=/opt/eldk/ppc_4xx\0" \
106 "bootfile=/tftpboot/bubinga/uImage\0" \
107 "kernel_addr=fff80000\0" \
108 "ramdisk_addr=fff90000\0" \
Stefan Roese5a753f92007-02-07 16:51:08 +0100109 "initrd_high=30000000\0" \
Stefan Roese8a316c92005-08-01 16:49:12 +0200110 "load=tftp 100000 /tftpboot/bubinga/u-boot.bin\0" \
111 "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
112 "cp.b 100000 fffc0000 40000;" \
113 "setenv filesize;saveenv\0" \
114 "upd=run load;run update\0" \
115 ""
116#define CONFIG_BOOTCOMMAND "run net_nfs"
117
118#if 0
119#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
120#else
121#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
stroese46578cc2003-05-23 11:28:55 +0000122#endif
123
124#define CONFIG_BAUDRATE 115200
stroese46578cc2003-05-23 11:28:55 +0000125
126#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
127#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
128
129#define CONFIG_MII 1 /* MII PHY management */
130#define CONFIG_PHY_ADDR 1 /* PHY address */
Stefan Roese9e005892005-08-11 17:58:40 +0200131#define CONFIG_HAS_ETH1
132#define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */
133#define CONFIG_NET_MULTI 1
134#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
stroese46578cc2003-05-23 11:28:55 +0000135
Stefan Roese1e25f952005-10-20 16:34:28 +0200136#define CONFIG_NETCONSOLE /* include NetConsole support */
137
stroese46578cc2003-05-23 11:28:55 +0000138#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */
139
stroese46578cc2003-05-23 11:28:55 +0000140
Jon Loeligerba2351f2007-07-04 22:31:49 -0500141/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500142 * BOOTP options
143 */
144#define CONFIG_BOOTP_BOOTFILESIZE
145#define CONFIG_BOOTP_BOOTPATH
146#define CONFIG_BOOTP_GATEWAY
147#define CONFIG_BOOTP_HOSTNAME
148
149
150/*
Jon Loeligerba2351f2007-07-04 22:31:49 -0500151 * Command line configuration.
152 */
153#include <config_cmd_default.h>
154
155#define CONFIG_CMD_ASKENV
156#define CONFIG_CMD_CACHE
157#define CONFIG_CMD_DATE
158#define CONFIG_CMD_DHCP
159#define CONFIG_CMD_EEPROM
160#define CONFIG_CMD_ELF
161#define CONFIG_CMD_I2C
162#define CONFIG_CMD_IRQ
163#define CONFIG_CMD_MII
164#define CONFIG_CMD_NET
165#define CONFIG_CMD_PCI
166#define CONFIG_CMD_PING
167#define CONFIG_CMD_REGINFO
168#define CONFIG_CMD_SDRAM
169#define CONFIG_CMD_SNTP
170
stroese46578cc2003-05-23 11:28:55 +0000171
172#undef CONFIG_WATCHDOG /* watchdog disabled */
173
174#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
175
176/*
177 * Miscellaneous configurable options
178 */
179#define CFG_LONGHELP /* undef to save memory */
180#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligerba2351f2007-07-04 22:31:49 -0500181#if defined(CONFIG_CMD_KGDB)
stroese46578cc2003-05-23 11:28:55 +0000182#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
183#else
184#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
185#endif
186#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
187#define CFG_MAXARGS 16 /* max number of command args */
188#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
189
190#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
191#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
192
193/*
194 * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
195 * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
196 * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
197 * The Linux BASE_BAUD define should match this configuration.
198 * baseBaud = cpuClock/(uartDivisor*16)
199 * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
200 * set Linux BASE_BAUD to 403200.
201 */
Stefan Roese8a316c92005-08-01 16:49:12 +0200202#undef CONFIG_SERIAL_SOFTWARE_FIFO
stroese46578cc2003-05-23 11:28:55 +0000203#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
204#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
205#define CFG_BASE_BAUD 691200
206
207/* The following table includes the supported baudrates */
208#define CFG_BAUDRATE_TABLE \
209 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
210
211#define CFG_LOAD_ADDR 0x100000 /* default load address */
212#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
213
214#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
215
Stefan Roese4f92ed52006-08-07 14:33:32 +0200216#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Stefan Roese8a316c92005-08-01 16:49:12 +0200217#define CONFIG_LOOPW 1 /* enable loopw command */
Stefan Roese4f92ed52006-08-07 14:33:32 +0200218#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
Stefan Roese8a316c92005-08-01 16:49:12 +0200219#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
220#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
221
Stefan Roese8a316c92005-08-01 16:49:12 +0200222/*-----------------------------------------------------------------------
223 * I2C stuff
224 *-----------------------------------------------------------------------
225 */
stroese46578cc2003-05-23 11:28:55 +0000226#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
227#undef CONFIG_SOFT_I2C /* I2C bit-banged */
228#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
229#define CFG_I2C_SLAVE 0x7F
230
stroeseb828dda2003-12-09 14:54:43 +0000231#define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */
232#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
233
Jon Loeligerba2351f2007-07-04 22:31:49 -0500234#if defined(CONFIG_CMD_EEPROM)
stroeseb828dda2003-12-09 14:54:43 +0000235#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */
236#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
237#endif
238
stroese46578cc2003-05-23 11:28:55 +0000239/*-----------------------------------------------------------------------
240 * PCI stuff
241 *-----------------------------------------------------------------------
242 */
243#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
244#define PCI_HOST_FORCE 1 /* configure as pci host */
245#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
246
247#define CONFIG_PCI /* include pci support */
248#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
249#define CONFIG_PCI_PNP /* do pci plug-and-play */
wdenk8bde7f72003-06-27 21:31:46 +0000250 /* resource configuration */
stroeseb828dda2003-12-09 14:54:43 +0000251#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
stroese46578cc2003-05-23 11:28:55 +0000252
Stefan Roese8a316c92005-08-01 16:49:12 +0200253#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
254#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
stroeseb828dda2003-12-09 14:54:43 +0000255#define CFG_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */
stroese46578cc2003-05-23 11:28:55 +0000256#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
257#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
258#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
259#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
260#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
261#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
262
263/*-----------------------------------------------------------------------
264 * External peripheral base address
265 *-----------------------------------------------------------------------
266 */
stroese46578cc2003-05-23 11:28:55 +0000267#define CFG_KEY_REG_BASE_ADDR 0xF0100000
268#define CFG_IR_REG_BASE_ADDR 0xF0200000
269#define CFG_FPGA_REG_BASE_ADDR 0xF0300000
270
271/*-----------------------------------------------------------------------
272 * Start addresses for the final memory configuration
273 * (Set up by the startup code)
274 * Please note that CFG_SDRAM_BASE _must_ start at 0
275 */
276#define CFG_SDRAM_BASE 0x00000000
stroese46578cc2003-05-23 11:28:55 +0000277#define CFG_SRAM_BASE 0xFFF00000
278#define CFG_FLASH_BASE 0xFFF80000
Stefan Roese8a316c92005-08-01 16:49:12 +0200279#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
stroese46578cc2003-05-23 11:28:55 +0000280#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
Stefan Roese8a316c92005-08-01 16:49:12 +0200281#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
stroese46578cc2003-05-23 11:28:55 +0000282
283/*
284 * For booting Linux, the board info and command line data
285 * have to be in the first 8 MB of memory, since this is
286 * the maximum mapped by the Linux kernel during initialization.
287 */
288#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Stefan Roese8a316c92005-08-01 16:49:12 +0200289
stroese46578cc2003-05-23 11:28:55 +0000290/*-----------------------------------------------------------------------
291 * FLASH organization
292 */
293#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
294#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
295
296#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
297#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
298
Stefan Roese8a316c92005-08-01 16:49:12 +0200299#define CFG_FLASH_ADDR0 0x5555
300#define CFG_FLASH_ADDR1 0x2aaa
301#define CFG_FLASH_WORD_SIZE unsigned char
302
stroese46578cc2003-05-23 11:28:55 +0000303#ifdef CFG_ENV_IS_IN_FLASH
Stefan Roese8a316c92005-08-01 16:49:12 +0200304#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
305#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
306#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
307
308/* Address and size of Redundant Environment Sector */
309#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
310#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
311#endif /* CFG_ENV_IS_IN_FLASH */
312
stroese46578cc2003-05-23 11:28:55 +0000313/*-----------------------------------------------------------------------
314 * NVRAM organization
315 */
316#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
317#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
318
319#ifdef CFG_ENV_IS_IN_NVRAM
stroeseb828dda2003-12-09 14:54:43 +0000320#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
stroese46578cc2003-05-23 11:28:55 +0000321#define CFG_ENV_ADDR \
322 (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
323#endif
324/*-----------------------------------------------------------------------
325 * Cache Configuration
326 */
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200327#define CFG_DCACHE_SIZE 16384 /* For AMCC 405EP CPU */
stroese46578cc2003-05-23 11:28:55 +0000328#define CFG_CACHELINE_SIZE 32 /* ... */
Jon Loeligerba2351f2007-07-04 22:31:49 -0500329#if defined(CONFIG_CMD_KGDB)
stroese46578cc2003-05-23 11:28:55 +0000330#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
331#endif
332
333/*
334 * Init Memory Controller:
335 *
336 * BR0/1 and OR0/1 (FLASH)
337 */
338
339#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
340#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
341
stroese46578cc2003-05-23 11:28:55 +0000342/*-----------------------------------------------------------------------
343 * Definitions for initial stack pointer and data area (in data cache)
344 */
345/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
346#define CFG_TEMP_STACK_OCM 1
347
348/* On Chip Memory location */
349#define CFG_OCM_DATA_ADDR 0xF8000000
350#define CFG_OCM_DATA_SIZE 0x1000
351#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
352#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
353
354#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
355#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
356#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
357
358/*-----------------------------------------------------------------------
359 * External Bus Controller (EBC) Setup
360 */
361
362/* Memory Bank 0 (Flash/SRAM) initialization */
363#define CFG_EBC_PB0AP 0x04006000
364#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
365
366/* Memory Bank 1 (NVRAM/RTC) initialization */
367#define CFG_EBC_PB1AP 0x04041000
368#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
369
370/* Memory Bank 2 (not used) initialization */
371#define CFG_EBC_PB2AP 0x00000000
372#define CFG_EBC_PB2CR 0x00000000
373
374/* Memory Bank 2 (not used) initialization */
375#define CFG_EBC_PB3AP 0x00000000
376#define CFG_EBC_PB3CR 0x00000000
377
378/* Memory Bank 4 (FPGA regs) initialization */
379#define CFG_EBC_PB4AP 0x01815000
380#define CFG_EBC_PB4CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
381
382/*-----------------------------------------------------------------------
383 * Definitions for Serial Presence Detect EEPROM address
384 * (to get SDRAM settings)
385 */
386#define SPD_EEPROM_ADDRESS 0x55
387
388/*-----------------------------------------------------------------------
389 * Definitions for GPIO setup (PPC405EP specific)
390 *
391 * GPIO0[0] - External Bus Controller BLAST output
392 * GPIO0[1-9] - Instruction trace outputs
393 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
394 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
395 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
396 * GPIO0[24-27] - UART0 control signal inputs/outputs
397 * GPIO0[28-29] - UART1 data signal input/output
398 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
399 */
400#define CFG_GPIO0_OSRH 0x55555555
401#define CFG_GPIO0_OSRL 0x40000110
402#define CFG_GPIO0_ISR1H 0x00000000
403#define CFG_GPIO0_ISR1L 0x15555445
404#define CFG_GPIO0_TSRH 0x00000000
405#define CFG_GPIO0_TSRL 0x00000000
406#define CFG_GPIO0_TCR 0xFFFF8014
407
408/*-----------------------------------------------------------------------
409 * Some BUBINGA stuff...
410 */
411#define NVRAM_BASE 0xF0000000
412#define FPGA_REG0 0xF0300000 /* FPGA Reg 0 */
413#define FPGA_REG1 0xF0300001 /* FPGA Reg 1 */
414#define NVRVFY1 0x4f532d4f /* used to determine if state data in */
415#define NVRVFY2 0x50454e00 /* NVRAM initialized (ascii for OS-OPEN)*/
416
417#define FPGA_REG0_F_RANGE 0x80 /* SDRAM PLL freq range */
418#define FPGA_REG0_EXT_INT_DIS 0x20 /* External interface disable */
419#define FPGA_REG0_LED_MASK 0x07 /* Board LEDs DS9, DS10, and DS11 */
420#define FPGA_REG0_LED0 0x04 /* Turn on LED0 */
421#define FPGA_REG0_LED1 0x02 /* Turn on LED1 */
422#define FPGA_REG0_LED2 0x01 /* Turn on LED2 */
423
424#define FPGA_REG1_SSPEC_DIS 0x80 /* C9531 Spread Spectrum disabled */
425#define FPGA_REG1_OFFBD_PCICLK 0x40 /* Onboard PCI clock selected */
426#define FPGA_REG1_CLOCK_MASK 0x30 /* Mask for C9531 output freq select */
427#define FPGA_REG1_CLOCK_BIT_SHIFT 4
428#define FPGA_REG1_PCI_INT_ARB 0x08 /* PCI Internal arbiter selected */
429#define FPGA_REG1_PCI_FREQ 0x04 /* PCI Frequency select */
430#define FPGA_REG1_OFFB_FLASH 0x02 /* Off board flash */
431#define FPGA_REG1_SRAM_BOOT 0x01 /* SRAM at 0xFFF80000 not Flash */
432
stroese46578cc2003-05-23 11:28:55 +0000433/*
434 * Internal Definitions
435 *
436 * Boot Flags
437 */
438#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
439#define BOOTFLAG_WARM 0x02 /* Software reboot */
440
Jon Loeligerba2351f2007-07-04 22:31:49 -0500441#if defined(CONFIG_CMD_KGDB)
stroese46578cc2003-05-23 11:28:55 +0000442#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
443#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
444#endif
445
446#endif /* __CONFIG_H */