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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +05302/*
3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 * Based on davinci_dvevm.h. Original Copyrights follow:
6 *
7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +05308 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13/*
14 * Board
15 */
16
17/*
18 * SoC Configuration
19 */
Christian Rieschb67d8812012-02-02 00:44:39 +000020#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053021#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
22#define CONFIG_SYS_OSCIN_FREQ 24000000
23#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
24#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
Adam Ford66e26372019-08-01 08:47:55 -050025#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053026
Adam Ford7bb33e42020-06-29 18:49:41 -050027#ifdef CONFIG_MTD_NOR_FLASH
Lad, Prabhakar63777662012-06-24 21:35:23 +000028#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
Lad, Prabhakar63777662012-06-24 21:35:23 +000029#endif
30
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053031/*
32 * Memory Info
33 */
34#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053035#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
36#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
Ben Gardiner97003752010-08-23 09:08:15 -040037#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
Adam Ford15b8c752019-02-25 21:53:46 -060038#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
39#define CONFIG_SPL_BSS_MAX_SIZE 0x1080000
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053040/* memtest start addr */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053041
42/* memtest will be run on 16MB */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053043
Christian Riesch3d2c8e62011-12-09 09:47:37 +000044#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
45 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
46 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
47 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
48 DAVINCI_SYSCFG_SUSPSRC_EMAC | \
49 DAVINCI_SYSCFG_SUSPSRC_I2C)
50
51/*
52 * PLL configuration
53 */
Christian Riesch3d2c8e62011-12-09 09:47:37 +000054
55#define CONFIG_SYS_DA850_PLL0_PLLM 24
56#define CONFIG_SYS_DA850_PLL1_PLLM 21
57
58/*
59 * DDR2 memory configuration
60 */
61#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
62 DV_DDR_PHY_EXT_STRBEN | \
63 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
64
65#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
66 (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
67 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
68 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
69 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
70 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
71 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
72 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
73
74/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
75#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
76
77#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
78 (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \
79 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \
80 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
81 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \
82 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
83 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
84 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
85 (0 << DV_DDR_SDTMR1_WTR_SHIFT))
86
87#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
88 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
89 (0 << DV_DDR_SDTMR2_XP_SHIFT) | \
90 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
91 (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
92 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
93 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
94 (0 << DV_DDR_SDTMR2_CKE_SHIFT))
95
96#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494
97#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
98
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053099/*
100 * Serial Driver info
101 */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530102#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530103
Stefano Babicd73a8a12010-11-11 15:38:02 +0100104#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
Stefano Babicd73a8a12010-11-11 15:38:02 +0100105
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530106/*
107 * I2C Configuration
108 */
Adam Fordc7742072017-09-17 20:43:48 -0500109#ifndef CONFIG_SPL_BUILD
Sudhakar Rajashekharad2607402010-11-18 09:59:37 -0500110#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
Adam Fordc7742072017-09-17 20:43:48 -0500111#endif
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530112
113/*
Ben Gardiner6b2c6462010-10-14 17:26:25 -0400114 * Flash & Environment
115 */
Miquel Raynal88718be2019-10-03 19:50:03 +0200116#ifdef CONFIG_MTD_RAW_NAND
Ben Gardiner6b2c6462010-10-14 17:26:25 -0400117#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
118#define CONFIG_SYS_NAND_PAGE_2K
119#define CONFIG_SYS_NAND_CS 3
120#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
Eric Benard34fa0702013-04-22 05:55:00 +0000121#define CONFIG_SYS_NAND_MASK_CLE 0x10
122#define CONFIG_SYS_NAND_MASK_ALE 0x8
Ben Gardiner6b2c6462010-10-14 17:26:25 -0400123#undef CONFIG_SYS_NAND_HW_ECC
124#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
Lad, Prabhakar122f9c92012-06-24 21:35:22 +0000125#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
126#define CONFIG_SYS_NAND_5_ADDR_CYCLE
127#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
128#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
Adam Ford93f33622018-08-15 13:22:03 -0500129#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000
Lad, Prabhakar122f9c92012-06-24 21:35:22 +0000130#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
131#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
132#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
133 CONFIG_SYS_NAND_U_BOOT_SIZE - \
134 CONFIG_SYS_MALLOC_LEN - \
135 GENERATED_GBL_DATA_SIZE)
136#define CONFIG_SYS_NAND_ECCPOS { \
137 24, 25, 26, 27, 28, \
138 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
139 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
140 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
141 59, 60, 61, 62, 63 }
142#define CONFIG_SYS_NAND_PAGE_COUNT 64
143#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
144#define CONFIG_SYS_NAND_ECCSIZE 512
145#define CONFIG_SYS_NAND_ECCBYTES 10
146#define CONFIG_SYS_NAND_OOBSIZE 64
Lad, Prabhakar122f9c92012-06-24 21:35:22 +0000147#define CONFIG_SPL_NAND_LOAD
Bartosz Golaszewski95cffd92019-07-29 08:58:05 +0200148
149#ifndef CONFIG_SPL_BUILD
150#define CONFIG_SYS_NAND_SELF_INIT
151#endif
Ben Gardiner6b2c6462010-10-14 17:26:25 -0400152#endif
153
154/*
Ben Gardiner3d248d32010-10-14 17:26:29 -0400155 * Network & Ethernet Configuration
156 */
157#ifdef CONFIG_DRIVER_TI_EMAC
Ben Gardiner3d248d32010-10-14 17:26:29 -0400158#define CONFIG_NET_RETRY_COUNT 10
Ben Gardiner3d248d32010-10-14 17:26:29 -0400159#endif
160
Adam Ford7bb33e42020-06-29 18:49:41 -0500161#ifdef CONFIG_MTD_NOR_FLASH
Nagabhushana Netagunte1506b0a2011-09-03 22:18:32 -0400162#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
163#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
Nagabhushana Netagunte1506b0a2011-09-03 22:18:32 -0400164#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
165#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
166#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
167 + 3)
Adam Ford93f33622018-08-15 13:22:03 -0500168#endif
Stefano Babicd73a8a12010-11-11 15:38:02 +0100169
Ben Gardiner3d248d32010-10-14 17:26:29 -0400170/*
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530171 * U-Boot general configuration
172 */
173#define CONFIG_BOOTFILE "uImage" /* Boot file name */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530174#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530175#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
176#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530177
178/*
179 * Linux Information
180 */
Ben Gardiner59e0d612010-10-14 17:26:32 -0400181#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
Nagabhushana Netaguntecf2c24e2011-09-03 22:19:28 -0400182#define CONFIG_HWCONFIG /* enable hwconfig */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530183#define CONFIG_CMDLINE_TAG
Sekhar Nori4f6fc152010-11-19 11:39:48 -0500184#define CONFIG_REVISION_TAG
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530185#define CONFIG_SETUP_MEMORY_TAGS
Adam Forda4670f82017-09-17 20:43:46 -0500186
187#define CONFIG_BOOTCOMMAND \
188 "run envboot; " \
189 "run mmcboot; "
190
191#define DEFAULT_LINUX_BOOT_ENV \
192 "loadaddr=0xc0700000\0" \
193 "fdtaddr=0xc0600000\0" \
194 "scriptaddr=0xc0600000\0"
195
196#include <environment/ti/mmc.h>
197
198#define CONFIG_EXTRA_ENV_SETTINGS \
199 DEFAULT_LINUX_BOOT_ENV \
200 DEFAULT_MMC_TI_ARGS \
201 "bootpart=0:2\0" \
202 "bootdir=/boot\0" \
203 "bootfile=zImage\0" \
204 "fdtfile=da850-evm.dtb\0" \
205 "boot_fdt=yes\0" \
206 "boot_fit=0\0" \
207 "console=ttyS2,115200n8\0" \
208 "hwconfig=dsp:wake=yes"
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530209
Hadli, Manjunath8f5d4682012-02-06 00:30:44 +0000210#ifdef CONFIG_CMD_BDI
211#define CONFIG_CLOCKS
212#endif
213
Adam Ford95468e62019-04-30 05:21:42 -0500214/* USB Configs */
Adam Ford95468e62019-04-30 05:21:42 -0500215#define CONFIG_USB_OHCI_NEW
Adam Ford95468e62019-04-30 05:21:42 -0500216#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
Adam Ford95468e62019-04-30 05:21:42 -0500217
Adam Ford7bb33e42020-06-29 18:49:41 -0500218#ifdef CONFIG_SPL_BUILD
Christian Riesch3d2c8e62011-12-09 09:47:37 +0000219/* defines for SPL */
Tom Rini3f7f2412012-08-14 12:27:13 -0700220#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
221 CONFIG_SYS_MALLOC_LEN)
222#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
Christian Riesch3d2c8e62011-12-09 09:47:37 +0000223#define CONFIG_SPL_STACK 0x8001ff00
Albert ARIBAUDb7b5f1a2013-04-12 05:14:32 +0000224#define CONFIG_SPL_MAX_FOOTPRINT 32768
Christian Riesch532d5312014-05-07 10:16:28 +0200225#define CONFIG_SPL_PAD_TO 32768
Lad, Prabhakar63777662012-06-24 21:35:23 +0000226#endif
Lad, Prabhakar0d986e62012-06-24 21:35:20 +0000227
228/* Load U-Boot Image From MMC */
Lad, Prabhakar0d986e62012-06-24 21:35:20 +0000229
Heiko Schocherab86f722010-09-17 13:10:42 +0200230/* additions for new relocation code, must added to all boards */
Heiko Schocherab86f722010-09-17 13:10:42 +0200231#define CONFIG_SYS_SDRAM_BASE 0xc0000000
Lad, Prabhakar63777662012-06-24 21:35:23 +0000232
Adam Ford7bb33e42020-06-29 18:49:41 -0500233#ifdef CONFIG_MTD_NOR_FLASH
Lad, Prabhakar63777662012-06-24 21:35:23 +0000234#define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00
235#else
Heiko Schocherab86f722010-09-17 13:10:42 +0200236#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200237 GENERATED_GBL_DATA_SIZE)
Adam Ford7bb33e42020-06-29 18:49:41 -0500238#endif /* CONFIG_MTD_NOR_FLASH */
Simon Glass89f5eaa2017-05-17 08:23:09 -0600239
240#include <asm/arch/hardware.h>
241
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530242#endif /* __CONFIG_H */