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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
York Sunf749db32014-06-23 15:15:56 -07002/*
3 * Copyright (C) 2014 Freescale Semiconductor
York Sunf749db32014-06-23 15:15:56 -07004 */
5
6#ifndef __LS2_SIMU_H
7#define __LS2_SIMU_H
8
Prabhakar Kushwaha44937212015-11-09 16:42:07 +05309#include "ls2080a_common.h"
York Sunf749db32014-06-23 15:15:56 -070010
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -070011#define CONFIG_SYS_CLK_FREQ 100000000
12#define CONFIG_DDR_CLK_FREQ 133333333
13
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -070014#define CONFIG_DIMM_SLOTS_PER_CTLR 1
15#define CONFIG_CHIP_SELECTS_PER_CTRL 4
Prabhakar Kushwaha44937212015-11-09 16:42:07 +053016#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -070017#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
Prabhakar Kushwaha44937212015-11-09 16:42:07 +053018#endif
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -070019
York Sunf749db32014-06-23 15:15:56 -070020/* SMSC 91C111 ethernet configuration */
21#define CONFIG_SMC91111
22#define CONFIG_SMC91111_BASE (0x2210000)
23
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -070024#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
25#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
26
Masahiro Yamadae856bdc2017-02-11 22:43:54 +090027#ifdef CONFIG_MTD_NOR_FLASH
Yuan Yao82d13342016-06-08 18:24:53 +080028#define CONFIG_SYS_FLASH_QUIET_TEST
29#endif
30
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -070031/*
32 * NOR Flash Timing Params
33 */
34#define CONFIG_SYS_NOR0_CSPR \
35 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
36 CSPR_PORT_SIZE_16 | \
37 CSPR_MSEL_NOR | \
38 CSPR_V)
39#define CONFIG_SYS_NOR0_CSPR_EARLY \
40 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
41 CSPR_PORT_SIZE_16 | \
42 CSPR_MSEL_NOR | \
43 CSPR_V)
44#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
45#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
46 FTIM0_NOR_TEADC(0x1) | \
47 FTIM0_NOR_TEAHC(0x1))
48#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
49 FTIM1_NOR_TRAD_NOR(0x1))
50#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
51 FTIM2_NOR_TCH(0x0) | \
52 FTIM2_NOR_TWP(0x1))
53#define CONFIG_SYS_NOR_FTIM3 0x04000000
54#define CONFIG_SYS_IFC_CCR 0x01000000
55
Masahiro Yamadae856bdc2017-02-11 22:43:54 +090056#ifdef CONFIG_MTD_NOR_FLASH
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -070057#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
58
59#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
60#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
61#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
62#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
63
64#define CONFIG_SYS_FLASH_EMPTY_INFO
65#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
66#endif
67
68#define CONFIG_NAND_FSL_IFC
69#define CONFIG_SYS_NAND_MAX_ECCPOS 256
70#define CONFIG_SYS_NAND_MAX_OOBFREE 2
71
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -070072#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
73#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
74 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
75 | CSPR_MSEL_NAND /* MSEL = NAND */ \
76 | CSPR_V)
77#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
78
79#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
80 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
81 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
82 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
83 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
84 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
85 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
86
87#define CONFIG_SYS_NAND_ONFI_DETECTION
88
89/* ONFI NAND Flash mode0 Timing Params */
90#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
91 FTIM0_NAND_TWP(0x18) | \
92 FTIM0_NAND_TWCHT(0x07) | \
93 FTIM0_NAND_TWH(0x0a))
94#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
95 FTIM1_NAND_TWBE(0x39) | \
96 FTIM1_NAND_TRR(0x0e) | \
97 FTIM1_NAND_TRP(0x18))
98#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
99 FTIM2_NAND_TREH(0x0a) | \
100 FTIM2_NAND_TWHRE(0x1e))
101#define CONFIG_SYS_NAND_FTIM3 0x0
102
103#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
104#define CONFIG_SYS_MAX_NAND_DEVICE 1
105#define CONFIG_MTD_NAND_VERIFY_WRITE
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -0700106
107#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
108
109#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
110#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
111#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
112#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
113#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
114#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
115#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
116#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
117#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
Prabhakar Kushwahae211c122014-07-16 09:21:12 +0530118#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
119#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
120#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
121#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
122#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
123#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
124#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
125#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
126
Yangbo Lub22b8e92015-07-24 17:37:29 +0800127/* MMC */
Yangbo Lub22b8e92015-07-24 17:37:29 +0800128#ifdef CONFIG_MMC
Yangbo Lub22b8e92015-07-24 17:37:29 +0800129#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
Yangbo Lub22b8e92015-07-24 17:37:29 +0800130#endif
131
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -0700132/* Debug Server firmware */
133#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
134#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL
135
136/* MC firmware */
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -0700137#define CONFIG_SYS_LS_MC_DPL_IN_NOR
138#define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL
139
J. German Rivera125e2bc2015-03-20 19:28:18 -0700140#define CONFIG_SYS_LS_MC_DPC_IN_NOR
141#define CONFIG_SYS_LS_MC_DPC_ADDR 0x5806F8000ULL
142
143#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000
144
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -0700145/* Store environment at top of flash */
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -0700146
York Sunf749db32014-06-23 15:15:56 -0700147#endif /* __LS2_SIMU_H */