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Heiko Schocher6dedf3d2006-12-21 16:14:48 +01001/*
2 * (C) Copyright 2006
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
5 * (C) Copyright 2003-2004
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
8 * (C) Copyright 2004
9 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
10 *
11 * (C) Copyright 2004
12 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
13 *
14 * See file CREDITS for list of people who contributed to this
15 * project.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * MA 02111-1307 USA
31 */
32
33#include <common.h>
34#include <mpc5xxx.h>
35#include <pci.h>
36#include <malloc.h>
37
38/* some SIMPLE GPIO Pins */
39#define GPIO_USB_8 (31-12)
40#define GPIO_USB_7 (31-13)
41#define GPIO_USB_6 (31-14)
42#define GPIO_USB_0 (31-15)
43#define GPIO_PSC3_7 (31-18)
44#define GPIO_PSC3_6 (31-19)
45#define GPIO_PSC3_1 (31-22)
46#define GPIO_PSC3_0 (31-23)
47
48/* some simple Interrupt GPIO Pins */
49#define GPIO_PSC3_8 2
50#define GPIO_USB1_9 3
51
52#define GPT_OUT_0 0x00000027
53#define GPT_OUT_1 0x00000037
54#define GPT_DISABLE 0x00000000 /* GPT pin disabled */
55
56#define GP_SIMP_ENABLE_O(n, v) {pgpio->simple_dvo |= (v << n); \
57 pgpio->simple_ddr |= (1 << n); \
58 pgpio->simple_gpioe |= (1 << n); \
59 }
60
61#define GP_SIMP_ENABLE_I(n) { pgpio->simple_ddr |= ~(1 << n); \
62 pgpio->simple_gpioe |= (1 << n); \
63 }
64
65#define GP_SIMP_SET_O(n, v) (pgpio->simple_dvo = v ? \
66 (pgpio->simple_dvo | (1 << n)) : \
67 (pgpio->simple_dvo & ~(1 << n)) )
Wolfgang Denkf11033e2007-01-15 13:41:04 +010068
Heiko Schocher6dedf3d2006-12-21 16:14:48 +010069#define GP_SIMP_GET_O(n) ((pgpio->simple_dvo >> n) & 1)
70#define GP_SIMP_GET_I(n) ((pgpio->simple_ival >> n) & 1)
71
Heiko Schocher6dedf3d2006-12-21 16:14:48 +010072#define GP_SINT_SET_O(n, v) (pgpio->sint_dvo = v ? \
73 (pgpio->sint_dvo | (1 << n)) : \
74 (pgpio->sint_dvo & ~(1 << n)) )
75
76#define GP_SINT_ENABLE_O(n, v) {pgpio->sint_ode &= ~(1 << n); \
77 pgpio->sint_ddr |= (1 << n); \
78 GP_SINT_SET_O(n, v); \
79 pgpio->sint_gpioe |= (1 << n); \
80 }
81
82#define GP_SINT_ENABLE_I(n) { pgpio->sint_ddr |= ~(1 << n); \
83 pgpio->sint_gpioe |= (1 << n); \
84 }
85
86#define GP_SINT_GET_O(n) ((pgpio->sint_ival >> n) & 1)
87#define GP_SINT_GET_I(n) ((pgpio-ntt_ival >> n) & 1)
88
89#define GP_TIMER_ENABLE_O(n, v) ( \
90 ((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->emsr = v ? \
91 GPT_OUT_1 : \
92 GPT_OUT_0 )
93
94#define GP_TIMER_SET_O(n, v) GP_TIMER_ENABLE_O(n, v)
95
96#define GP_TIMER_GET_O(n, v) ( \
97 (((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->emsr & 0x10) >> 4)
98
99#define GP_TIMER_GET_I(n, v) ( \
100 (((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->sr & 0x100) >> 8)
101
102#ifndef CFG_RAMBOOT
103static void sdram_start (int hi_addr)
104{
105 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
106
107 /* unlock mode register */
108 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
109 __asm__ volatile ("sync");
110
111 /* precharge all banks */
112 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
113 __asm__ volatile ("sync");
114
115#if SDRAM_DDR
116 /* set mode register: extended mode */
117 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
118 __asm__ volatile ("sync");
119
120 /* set mode register: reset DLL */
121 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
122 __asm__ volatile ("sync");
123#endif
124
125 /* precharge all banks */
126 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
127 __asm__ volatile ("sync");
128
129 /* auto refresh */
130 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
131 __asm__ volatile ("sync");
132
133 /* set mode register */
134 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
135 __asm__ volatile ("sync");
136
137 /* normal operation */
138 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
139 __asm__ volatile ("sync");
140}
141#endif
142
143/*
144 * ATTENTION: Although partially referenced initdram does NOT make real use
145 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
146 * is something else than 0x00000000.
147 */
148
149long int initdram (int board_type)
150{
151 ulong dramsize = 0;
152#ifndef CFG_RAMBOOT
153 ulong test1, test2;
154
155 /* setup SDRAM chip selects */
156 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
157 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
158 __asm__ volatile ("sync");
159
160 /* setup config registers */
161 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
162 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
163 __asm__ volatile ("sync");
164
165#if SDRAM_DDR
166 /* set tap delay */
167 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
168 __asm__ volatile ("sync");
169#endif
170
171 /* find RAM size using SDRAM CS0 only */
172 sdram_start(0);
173 test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
174 sdram_start(1);
175 test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
176 if (test1 > test2) {
177 sdram_start(0);
178 dramsize = test1;
179 } else {
180 dramsize = test2;
181 }
182
183 /* memory smaller than 1MB is impossible */
184 if (dramsize < (1 << 20)) {
185 dramsize = 0;
186 }
187
188 /* set SDRAM CS0 size according to the amount of RAM found */
189 if (dramsize > 0) {
190 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
191 __builtin_ffs(dramsize >> 20) - 1;
192 } else {
193 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
194 }
195
196 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
197#else /* CFG_RAMBOOT */
198
199 /* retrieve size of memory connected to SDRAM CS0 */
200 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
201 if (dramsize >= 0x13) {
202 dramsize = (1 << (dramsize - 0x13)) << 20;
203 } else {
204 dramsize = 0;
205 }
206
207 /* retrieve size of memory connected to SDRAM CS1 */
208 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
209 if (dramsize2 >= 0x13) {
210 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
211 } else {
212 dramsize2 = 0;
213 }
214
215#endif /* CFG_RAMBOOT */
216
217/* return dramsize + dramsize2; */
218 return dramsize;
219}
220
221int checkboard (void)
222{
223 puts ("Board: MAN UC101\n");
224 return 0;
225}
226
227static void init_ports (void)
228{
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100229 volatile struct mpc5xxx_gpio *pgpio =
Heiko Schocher6dedf3d2006-12-21 16:14:48 +0100230 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
231
232 GP_SIMP_ENABLE_I(GPIO_USB_8); /* HEX Bit 3 */
233 GP_SIMP_ENABLE_I(GPIO_USB_7); /* HEX Bit 2 */
234 GP_SIMP_ENABLE_I(GPIO_USB_6); /* HEX Bit 1 */
235 GP_SIMP_ENABLE_I(GPIO_USB_0); /* HEX Bit 0 */
236 GP_SIMP_ENABLE_I(GPIO_PSC3_0); /* Switch Menue A */
237 GP_SIMP_ENABLE_I(GPIO_PSC3_1); /* Switch Menue B */
238 GP_SIMP_ENABLE_I(GPIO_PSC3_6); /* Switch Cold_Warm */
239 GP_SIMP_ENABLE_I(GPIO_PSC3_7); /* Switch Restart */
240 GP_SINT_ENABLE_O(GPIO_PSC3_8, 0); /* LED H2 */
241 GP_SINT_ENABLE_O(GPIO_USB1_9, 0); /* LED H3 */
242 GP_TIMER_ENABLE_O(4, 0); /* LED H4 */
243 GP_TIMER_ENABLE_O(5, 0); /* LED H5 */
244 GP_TIMER_ENABLE_O(3, 0); /* LED HB */
245 GP_TIMER_ENABLE_O(1, 0); /* RES_COLDSTART */
246}
247
248#ifdef CONFIG_PREBOOT
249
250static uchar kbd_magic_prefix[] = "key_magic";
251static uchar kbd_command_prefix[] = "key_cmd";
252
253struct kbd_data_t {
254 char s1;
255};
256
257struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
258{
259 volatile struct mpc5xxx_gpio *pgpio =
260 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
261
262 kbd_data->s1 = GP_SIMP_GET_I(GPIO_USB_8) << 3 | \
263 GP_SIMP_GET_I(GPIO_USB_7) << 2 | \
264 GP_SIMP_GET_I(GPIO_USB_6) << 1 | \
265 GP_SIMP_GET_I(GPIO_USB_0) << 0;
266 return kbd_data;
267}
268
269static int compare_magic (const struct kbd_data_t *kbd_data, uchar *str)
270{
271 char s1 = str[0];
272
273 if (s1 >= '0' && s1 <= '9')
274 s1 -= '0';
275 else if (s1 >= 'a' && s1 <= 'f')
276 s1 = s1 - 'a' + 10;
277 else if (s1 >= 'A' && s1 <= 'F')
278 s1 = s1 - 'A' + 10;
279 else
280 return -1;
281
282 if (s1 != kbd_data->s1) return -1;
283 return 0;
284}
285
286static uchar *key_match (const struct kbd_data_t *kbd_data)
287{
288 uchar magic[sizeof (kbd_magic_prefix) + 1];
289 uchar *suffix;
290 uchar *kbd_magic_keys;
291
292 /*
293 * The following string defines the characters that can be appended
294 * to "key_magic" to form the names of environment variables that
295 * hold "magic" key codes, i. e. such key codes that can cause
296 * pre-boot actions. If the string is empty (""), then only
297 * "key_magic" is checked (old behaviour); the string "125" causes
298 * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
299 */
300 if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
301 kbd_magic_keys = "";
302
303 /* loop over all magic keys;
304 * use '\0' suffix in case of empty string
305 */
306 for (suffix = kbd_magic_keys; *suffix ||
307 suffix == kbd_magic_keys; ++suffix) {
308 sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
309
310 if (compare_magic(kbd_data, getenv(magic)) == 0) {
311 uchar cmd_name[sizeof (kbd_command_prefix) + 1];
312 char *cmd;
313
314 sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
315 cmd = getenv (cmd_name);
316
317 return (cmd);
318 }
319 }
320
321 return (NULL);
322}
323
324#endif /* CONFIG_PREBOOT */
325
326int misc_init_r (void)
327{
328 /* Init the I/O ports */
329 init_ports ();
330
331#ifdef CONFIG_PREBOOT
332 struct kbd_data_t kbd_data;
333 /* Decode keys */
334 uchar *str = strdup (key_match (get_keys (&kbd_data)));
335 /* Set or delete definition */
336 setenv ("preboot", str);
337 free (str);
338#endif /* CONFIG_PREBOOT */
339 return 0;
340}
341
342int board_early_init_r (void)
343{
344 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
345 *(vu_long *)MPC5XXX_BOOTCS_START =
346 *(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE);
347 *(vu_long *)MPC5XXX_BOOTCS_STOP =
348 *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE);
349 /* Interbus enable it here ?? */
350 *(vu_long *)MPC5XXX_GPT6_ENABLE = GPT_OUT_1;
351 return 0;
352}
353#ifdef CONFIG_PCI
354static struct pci_controller hose;
355
356extern void pci_mpc5xxx_init(struct pci_controller *);
357
358void pci_init_board(void)
359{
360 pci_mpc5xxx_init(&hose);
361}
362#endif
363
364#if defined(CONFIG_HW_WATCHDOG)
365void hw_watchdog_reset(void)
366{
367 /* Trigger HW Watchdog with TIMER_0 */
368 *(vu_long *)MPC5XXX_GPT0_ENABLE = GPT_OUT_1;
369 *(vu_long *)MPC5XXX_GPT0_ENABLE = GPT_OUT_0;
370}
371#endif