| Marty E. Plummer | 6d36e92 | 2021-12-24 16:43:46 +0300 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_SKIP_LOWLEVEL_INIT=y |
| Peng Fan | abf8d96 | 2022-04-13 17:47:20 +0800 | [diff] [blame] | 3 | CONFIG_COUNTER_FREQUENCY=24000000 |
| Marty E. Plummer | 6d36e92 | 2021-12-24 16:43:46 +0300 | [diff] [blame] | 4 | CONFIG_ARCH_ROCKCHIP=y |
| 5 | CONFIG_SYS_TEXT_BASE=0x00200000 |
| 6 | CONFIG_SPL_GPIO=y |
| 7 | CONFIG_NR_DRAM_BANKS=1 |
| 8 | CONFIG_ENV_OFFSET=0x3F8000 |
| 9 | CONFIG_DEFAULT_DEVICE_TREE="rk3399-gru-kevin" |
| 10 | CONFIG_SPL_TEXT_BASE=0xff8c2000 |
| 11 | CONFIG_ROCKCHIP_RK3399=y |
| 12 | CONFIG_ROCKCHIP_BOOT_MODE_REG=0 |
| 13 | CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 |
| 14 | # CONFIG_SPL_MMC is not set |
| 15 | CONFIG_TARGET_CHROMEBOOK_KEVIN=y |
| 16 | CONFIG_DEBUG_UART_BASE=0xff1a0000 |
| 17 | CONFIG_DEBUG_UART_CLOCK=24000000 |
| 18 | CONFIG_SPL_SPI_FLASH_SUPPORT=y |
| 19 | CONFIG_SPL_SPI=y |
| Marty E. Plummer | 6d36e92 | 2021-12-24 16:43:46 +0300 | [diff] [blame] | 20 | CONFIG_SYS_LOAD_ADDR=0x800800 |
| Tom Rini | d46e86d | 2022-04-08 13:36:51 -0400 | [diff] [blame] | 21 | CONFIG_DEBUG_UART=y |
| Tom Rini | eaf6ea6 | 2022-05-25 12:16:03 -0400 | [diff] [blame] | 22 | CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y |
| 23 | CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 |
| Marty E. Plummer | 6d36e92 | 2021-12-24 16:43:46 +0300 | [diff] [blame] | 24 | CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-kevin.dtb" |
| 25 | # CONFIG_DISPLAY_CPUINFO is not set |
| 26 | CONFIG_DISPLAY_BOARDINFO_LATE=y |
| 27 | CONFIG_BOARD_EARLY_INIT_R=y |
| 28 | CONFIG_MISC_INIT_R=y |
| 29 | CONFIG_BLOBLIST=y |
| Marty E. Plummer | 6d36e92 | 2021-12-24 16:43:46 +0300 | [diff] [blame] | 30 | CONFIG_BLOBLIST_ADDR=0x100000 |
| Tom Rini | 8d2b7ae | 2022-03-28 14:01:11 +0000 | [diff] [blame] | 31 | CONFIG_BLOBLIST_SIZE=0x1000 |
| Tom Rini | ca8a329 | 2022-05-16 17:20:26 -0400 | [diff] [blame] | 32 | CONFIG_SPL_MAX_SIZE=0x2e000 |
| 33 | CONFIG_SPL_PAD_TO=0x7f8000 |
| Tom Rini | 9b5f9ae | 2022-05-19 15:09:22 -0400 | [diff] [blame] | 34 | CONFIG_SPL_BSS_MAX_SIZE=0x10000 |
| Marty E. Plummer | 6d36e92 | 2021-12-24 16:43:46 +0300 | [diff] [blame] | 35 | CONFIG_HANDOFF=y |
| 36 | # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set |
| Tom Rini | f113d7d | 2022-05-26 13:13:21 -0400 | [diff] [blame^] | 37 | # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set |
| 38 | CONFIG_SPL_STACK=0xff8effff |
| Marty E. Plummer | 6d36e92 | 2021-12-24 16:43:46 +0300 | [diff] [blame] | 39 | CONFIG_SPL_STACK_R=y |
| 40 | CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 |
| 41 | CONFIG_SPL_SPI_LOAD=y |
| 42 | CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 |
| 43 | CONFIG_CMD_BOOTZ=y |
| 44 | CONFIG_CMD_GPIO=y |
| 45 | CONFIG_CMD_GPT=y |
| 46 | CONFIG_CMD_I2C=y |
| 47 | CONFIG_CMD_MMC=y |
| 48 | CONFIG_CMD_SF_TEST=y |
| 49 | CONFIG_CMD_SPI=y |
| 50 | CONFIG_CMD_USB=y |
| 51 | # CONFIG_CMD_SETEXPR is not set |
| 52 | CONFIG_CMD_TIME=y |
| 53 | CONFIG_CMD_PMIC=y |
| 54 | CONFIG_CMD_REGULATOR=y |
| 55 | CONFIG_CMD_LOG=y |
| 56 | CONFIG_SPL_OF_CONTROL=y |
| 57 | CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" |
| 58 | CONFIG_ENV_IS_IN_MMC=y |
| 59 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
| 60 | CONFIG_SPL_DM_SEQ_ALIAS=y |
| 61 | CONFIG_ROCKCHIP_GPIO=y |
| 62 | CONFIG_I2C_CROS_EC_TUNNEL=y |
| 63 | CONFIG_SYS_I2C_ROCKCHIP=y |
| 64 | CONFIG_I2C_MUX=y |
| 65 | CONFIG_CROS_EC_KEYB=y |
| 66 | CONFIG_MISC=y |
| 67 | CONFIG_ROCKCHIP_EFUSE=y |
| 68 | CONFIG_CROS_EC=y |
| 69 | CONFIG_CROS_EC_SPI=y |
| 70 | CONFIG_PWRSEQ=y |
| 71 | CONFIG_MMC_PWRSEQ=y |
| 72 | CONFIG_MMC_DW=y |
| 73 | CONFIG_MMC_DW_ROCKCHIP=y |
| 74 | CONFIG_MMC_SDHCI=y |
| 75 | CONFIG_MMC_SDHCI_ROCKCHIP=y |
| 76 | CONFIG_SF_DEFAULT_BUS=1 |
| 77 | CONFIG_SF_DEFAULT_SPEED=20000000 |
| 78 | CONFIG_SPI_FLASH_GIGADEVICE=y |
| 79 | CONFIG_SPI_FLASH_WINBOND=y |
| 80 | CONFIG_DM_ETH=y |
| 81 | CONFIG_ETH_DESIGNWARE=y |
| 82 | CONFIG_GMAC_ROCKCHIP=y |
| 83 | CONFIG_PHY_ROCKCHIP_INNO_USB2=y |
| 84 | CONFIG_PHY_ROCKCHIP_TYPEC=y |
| 85 | CONFIG_PMIC_RK8XX=y |
| 86 | CONFIG_REGULATOR_PWM=y |
| 87 | CONFIG_DM_REGULATOR_GPIO=y |
| 88 | CONFIG_REGULATOR_RK8XX=y |
| 89 | CONFIG_PWM_CROS_EC=y |
| 90 | CONFIG_PWM_ROCKCHIP=y |
| 91 | CONFIG_DM_RESET=y |
| 92 | CONFIG_DM_RNG=y |
| 93 | CONFIG_RNG_ROCKCHIP=y |
| 94 | CONFIG_DEBUG_UART_SHIFT=2 |
| 95 | CONFIG_ROCKCHIP_SPI=y |
| 96 | CONFIG_SYSRESET=y |
| 97 | CONFIG_USB=y |
| 98 | CONFIG_USB_XHCI_HCD=y |
| 99 | CONFIG_USB_XHCI_DWC3=y |
| 100 | CONFIG_USB_EHCI_HCD=y |
| 101 | CONFIG_USB_EHCI_GENERIC=y |
| 102 | CONFIG_USB_OHCI_HCD=y |
| 103 | CONFIG_USB_OHCI_GENERIC=y |
| 104 | CONFIG_USB_DWC3=y |
| 105 | CONFIG_USB_KEYBOARD=y |
| 106 | CONFIG_USB_HOST_ETHER=y |
| 107 | CONFIG_USB_ETHER_ASIX=y |
| 108 | CONFIG_USB_ETHER_ASIX88179=y |
| 109 | CONFIG_USB_ETHER_MCS7830=y |
| 110 | CONFIG_USB_ETHER_RTL8152=y |
| 111 | CONFIG_USB_ETHER_SMSC95XX=y |
| 112 | CONFIG_DM_VIDEO=y |
| 113 | CONFIG_DISPLAY=y |
| 114 | CONFIG_VIDEO_ROCKCHIP=y |
| 115 | CONFIG_VIDEO_ROCKCHIP_MAX_XRES=2400 |
| 116 | CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1600 |
| 117 | CONFIG_DISPLAY_ROCKCHIP_EDP=y |
| 118 | CONFIG_CMD_DHRYSTONE=y |
| 119 | CONFIG_ERRNO_STR=y |