| Simon Glass | fc760cb | 2016-01-21 19:44:54 -0700 | [diff] [blame] | 1 | config DM_PWM |
| 2 | bool "Enable support for pulse-width modulation devices (PWM)" |
| 3 | depends on DM |
| 4 | help |
| 5 | A pulse-width modulator emits a pulse of varying width and provides |
| 6 | control over the duty cycle (high and low time) of the signal. This |
| 7 | is often used to control a voltage level. The more time the PWM |
| 8 | spends in the 'high' state, the higher the voltage. The PWM's |
| 9 | frequency/period can be controlled along with the proportion of that |
| 10 | time that the signal is high. |
| Simon Glass | 0e23fd8 | 2016-01-21 19:44:55 -0700 | [diff] [blame] | 11 | |
| Alper Nebi Yasak | 1b9ee28 | 2020-10-22 23:49:27 +0300 | [diff] [blame] | 12 | config PWM_CROS_EC |
| 13 | bool "Enable support for the Chrome OS EC PWM" |
| 14 | depends on DM_PWM |
| 15 | help |
| 16 | This PWM is found on several Chrome OS devices and controlled by |
| 17 | the Chrome OS embedded controller. It may be used to control the |
| 18 | screen brightness and/or the keyboard backlight depending on the |
| 19 | device. |
| 20 | |
| Simon Glass | 5c2dd4c | 2016-02-21 21:08:49 -0700 | [diff] [blame] | 21 | config PWM_EXYNOS |
| 22 | bool "Enable support for the Exynos PWM" |
| 23 | depends on DM_PWM |
| 24 | help |
| 25 | This PWM is found on Samsung Exynos 5250 and other Samsung SoCs. It |
| 26 | supports a programmable period and duty cycle. A 32-bit counter is |
| 27 | used. It provides 5 channels which can be independently |
| 28 | programmed. Channel 4 (the last) is normally used as a timer. |
| 29 | |
| Heiko Schocher | e0f0657 | 2019-05-28 06:51:51 +0200 | [diff] [blame] | 30 | config PWM_IMX |
| 31 | bool "Enable support for i.MX27 and later PWM" |
| 32 | help |
| 33 | This PWM is found i.MX27 and later i.MX SoCs. |
| 34 | |
| Neil Armstrong | 2d481b2 | 2020-10-01 10:04:56 +0200 | [diff] [blame] | 35 | config PWM_MESON |
| 36 | bool "Enable support for Amlogic Meson SoCs PWM" |
| 37 | depends on DM_PWM |
| 38 | help |
| 39 | This PWM is found on Amlogic Meson SoCs. It supports a |
| 40 | programmable period and duty cycle for 2 independant channels. |
| 41 | |
| Sam Shih | a537fa4 | 2020-02-21 21:01:46 +0800 | [diff] [blame] | 42 | config PWM_MTK |
| 43 | bool "Enable support for MediaTek PWM" |
| 44 | depends on DM_PWM |
| 45 | help |
| 46 | This PWM is found on MT7622, MT7623, and MT7629. It supports a |
| 47 | programmable period and duty cycle. |
| 48 | |
| Simon Glass | 0e23fd8 | 2016-01-21 19:44:55 -0700 | [diff] [blame] | 49 | config PWM_ROCKCHIP |
| 50 | bool "Enable support for the Rockchip PWM" |
| 51 | depends on DM_PWM |
| 52 | help |
| 53 | This PWM is found on RK3288 and other Rockchip SoCs. It supports a |
| 54 | programmable period and duty cycle. A 32-bit counter is used. |
| 55 | Various options provided in the hardware (such as capture mode and |
| 56 | continuous/single-shot) are not supported by the driver. |
| Simon Glass | 41fa035 | 2016-01-30 16:38:00 -0700 | [diff] [blame] | 57 | |
| Simon Glass | 43b4156 | 2017-04-16 21:01:11 -0600 | [diff] [blame] | 58 | config PWM_SANDBOX |
| 59 | bool "Enable support for the sandbox PWM" |
| 60 | help |
| 61 | This is a sandbox PWM used for testing. It provides 3 channels and |
| 62 | records the settings passed into it, but otherwise does nothing |
| 63 | useful. The PWM can be enabled but is not connected to any outputs |
| 64 | so this is not very useful. |
| 65 | |
| Yash Shah | 7239a61 | 2020-04-23 16:57:16 +0530 | [diff] [blame] | 66 | config PWM_SIFIVE |
| 67 | bool "Enable support for SiFive PWM" |
| 68 | depends on DM_PWM |
| 69 | help |
| 70 | This PWM is found SiFive's FU540 and other SoCs. |
| 71 | |
| Simon Glass | 41fa035 | 2016-01-30 16:38:00 -0700 | [diff] [blame] | 72 | config PWM_TEGRA |
| 73 | bool "Enable support for the Tegra PWM" |
| Simon Glass | 91c08af | 2016-01-30 16:38:01 -0700 | [diff] [blame] | 74 | depends on DM_PWM |
| Simon Glass | 41fa035 | 2016-01-30 16:38:00 -0700 | [diff] [blame] | 75 | help |
| 76 | This PWM is found on Tegra 20 and other Nvidia SoCs. It supports |
| 77 | four channels with a programmable period and duty cycle. Only a |
| 78 | 32KHz clock is supported by the driver but the duty cycle is |
| 79 | configurable. |
| Vasily Khoruzhick | 1c353ae | 2018-05-14 08:16:20 -0700 | [diff] [blame] | 80 | |
| 81 | config PWM_SUNXI |
| 82 | bool "Enable support for the Allwinner Sunxi PWM" |
| 83 | depends on DM_PWM |
| 84 | help |
| 85 | This PWM is found on H3, A64 and other Allwinner SoCs. It supports a |
| 86 | programmable period and duty cycle. A 16-bit counter is used. |
| Dario Binacchi | ade7f0d | 2020-12-30 00:16:24 +0100 | [diff] [blame] | 87 | |
| 88 | config PWM_TI_EHRPWM |
| 89 | bool "Enable support for EHRPWM PWM" |
| 90 | depends on DM_PWM && ARCH_OMAP2PLUS |
| 91 | default y |
| 92 | help |
| 93 | PWM driver support for the EHRPWM controller found on TI SOCs. |