blob: 9ab550242274df5bc48203635bb73974a1f1035f [file] [log] [blame]
Heiko Stübner0a2be692017-02-18 19:46:36 +01001/*
2 * (C) Copyright 2015 Google, Inc
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __CONFIG_RK3188_COMMON_H
8#define __CONFIG_RK3188_COMMON_H
9
10#define CONFIG_SYS_CACHELINE_SIZE 64
11
12#include <asm/arch/hardware.h>
13#include "rockchip-common.h"
14
15#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
Heiko Stübner0a2be692017-02-18 19:46:36 +010016#define CONFIG_NR_DRAM_BANKS 1
Heiko Stübner0a2be692017-02-18 19:46:36 +010017#define CONFIG_SYS_MALLOC_LEN (32 << 20)
18#define CONFIG_SYS_CBSIZE 1024
Heiko Stübner0a2be692017-02-18 19:46:36 +010019
20#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
21#define CONFIG_SYS_TIMER_BASE 0x2000e000 /* TIMER3 */
22#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
23#define CONFIG_SYS_TIMER_COUNTS_DOWN
24
25#define CONFIG_SYS_NS16550_MEM32
Heiko Stübner0a2be692017-02-18 19:46:36 +010026
Philipp Tomsichee14d292017-06-29 11:21:15 +020027#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
Heiko Stübner0a2be692017-02-18 19:46:36 +010028/* Bootrom will load u-boot binary to 0x60000000 once return from SPL */
29#define CONFIG_SYS_TEXT_BASE 0x60000000
30#else
31#define CONFIG_SYS_TEXT_BASE 0x60100000
32#endif
33#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
34#define CONFIG_SYS_LOAD_ADDR 0x60800800
35
36#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x8000 - 0x800)
37#define CONFIG_ROCKCHIP_CHIP_TAG "RK31"
38
Philipp Tomsich4d9253f2017-10-10 16:21:15 +020039#define CONFIG_SPL_TEXT_BASE 0x10080800
40/* spl size 32kb sram - 2kb bootrom */
41#define CONFIG_SPL_MAX_SIZE (0x8000 - 0x800)
Heiko Stübner0a2be692017-02-18 19:46:36 +010042#define CONFIG_SPL_FRAMEWORK 1
Heiko Stübner0a2be692017-02-18 19:46:36 +010043#define CONFIG_ROCKCHIP_SERIAL 1
Heiko Stübner0a2be692017-02-18 19:46:36 +010044
45#define CONFIG_SPL_STACK 0x10087fff
46
47/* MMC/SD IP block */
48#define CONFIG_BOUNCE_BUFFER
49
Heiko Stübner0a2be692017-02-18 19:46:36 +010050#define CONFIG_SYS_SDRAM_BASE 0x60000000
51#define CONFIG_NR_DRAM_BANKS 1
52#define SDRAM_BANK_SIZE (2UL << 30)
Kever Yang6d1970f2017-06-23 16:11:05 +080053#define SDRAM_MAX_SIZE 0x80000000
Heiko Stübner0a2be692017-02-18 19:46:36 +010054
55#define CONFIG_SPI_FLASH
56#define CONFIG_SPI
57#define CONFIG_SF_DEFAULT_SPEED 20000000
58
59#ifndef CONFIG_SPL_BUILD
60/* usb otg */
Heiko Stübner0a2be692017-02-18 19:46:36 +010061
62/* usb host support */
Heiko Stübner0a2be692017-02-18 19:46:36 +010063#define ENV_MEM_LAYOUT_SETTINGS \
64 "scriptaddr=0x60000000\0" \
65 "pxefile_addr_r=0x60100000\0" \
66 "fdt_addr_r=0x61f00000\0" \
67 "kernel_addr_r=0x62000000\0" \
68 "ramdisk_addr_r=0x64000000\0"
69
70#include <config_distro_bootcmd.h>
71
72/* Linux fails to load the fdt if it's loaded above 256M on a Rock board,
73 * so limit the fdt reallocation to that */
74#define CONFIG_EXTRA_ENV_SETTINGS \
75 "fdt_high=0x6fffffff\0" \
76 "initrd_high=0x6fffffff\0" \
77 "partitions=" PARTS_DEFAULT \
78 ENV_MEM_LAYOUT_SETTINGS \
79 ROCKCHIP_DEVICE_SETTINGS \
80 BOOTENV
81
82#endif /* CONFIG_SPL_BUILD */
83
84#define CONFIG_PREBOOT
85
86#endif