blob: 0b75b7622b765ea338828b9919820ca729e9695d [file] [log] [blame]
Andre Schwarz1f2463d2010-04-01 21:26:55 +02001/*
2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004-2010
6 * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30#include <version.h>
31
32#define CONFIG_MPC5xxx 1
33#define CONFIG_MPC5200 1
34
Wolfgang Denk2ae18242010-10-06 09:05:45 +020035#ifndef CONFIG_SYS_TEXT_BASE
36#define CONFIG_SYS_TEXT_BASE 0xFF800000
37#endif
Wolfgang Denk2ced53e2010-11-28 21:18:58 +010038#define CONFIG_SYS_LDSCRIPT "board/matrix_vision/mvsmr/u-boot.lds"
Wolfgang Denk2ae18242010-10-06 09:05:45 +020039
Andre Schwarz1f2463d2010-04-01 21:26:55 +020040#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
41
Andre Schwarz1f2463d2010-04-01 21:26:55 +020042#define CONFIG_MISC_INIT_R 1
43
44#define CONFIG_SYS_CACHELINE_SIZE 32
45#ifdef CONFIG_CMD_KGDB
46#define CONFIG_SYS_CACHELINE_SHIFT 5
47#endif
48
49#define CONFIG_PSC_CONSOLE 1
50#define CONFIG_BAUDRATE 115200
51#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200,\
52 230400}
53
54#define CONFIG_PCI 1
55#define CONFIG_PCI_PNP 1
56#undef CONFIG_PCI_SCAN_SHOW
57#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
58
59#define CONFIG_PCI_MEM_BUS 0x40000000
60#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
61#define CONFIG_PCI_MEM_SIZE 0x10000000
62
63#define CONFIG_PCI_IO_BUS 0x50000000
64#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
65#define CONFIG_PCI_IO_SIZE 0x01000000
66
67#define CONFIG_SYS_XLB_PIPELINING 1
68#define CONFIG_HIGH_BATS 1
69
70#define MV_CI mvSMR
71#define MV_VCI mvSMR
72#define MV_FPGA_DATA 0xff840000
73#define MV_FPGA_SIZE 0x1ff88
74#define MV_KERNEL_ADDR 0xfff00000
75#define MV_SCRIPT_ADDR 0xff806000
76#define MV_INITRD_ADDR 0xff880000
77#define MV_INITRD_LENGTH 0x00240000
78#define MV_SCRATCH_ADDR 0xffcc0000
79#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH
80
81#define CONFIG_SHOW_BOOT_PROGRESS 1
82
83#define MV_KERNEL_ADDR_RAM 0x00100000
84#define MV_INITRD_ADDR_RAM 0x00400000
85
86/*
87 * Supported commands
88 */
89#include <config_cmd_default.h>
90
91#define CONFIG_CMD_CACHE
92#define CONFIG_CMD_DHCP
93#define CONFIG_CMD_FPGA
94#define CONFIG_CMD_I2C
95#define CONFIG_CMD_MII
96#define CONFIG_CMD_NET
97#define CONFIG_CMD_PCI
98#define CONFIG_CMD_PING
99#define CONFIG_CMD_SDRAM
100
101#define CONFIG_BOOTP_BOOTFILESIZE
102#define CONFIG_BOOTP_BOOTPATH
103#define CONFIG_BOOTP_DNS
104#define CONFIG_BOOTP_DNS2
105#define CONFIG_BOOTP_GATEWAY
106#define CONFIG_BOOTP_HOSTNAME
107#define CONFIG_BOOTP_NTPSERVER
108#define CONFIG_BOOTP_RANDOM_DELAY
109#define CONFIG_BOOTP_SEND_HOSTNAME
110#define CONFIG_BOOTP_SUBNETMASK
111#define CONFIG_BOOTP_VENDOREX
112
113/*
114 * Autoboot
115 */
116#define CONFIG_BOOTDELAY 1
117#define CONFIG_AUTOBOOT_KEYED
118#define CONFIG_AUTOBOOT_STOP_STR "abcdefg"
119#define CONFIG_ZERO_BOOTDELAY_CHECK
120
121#define CONFIG_BOOTCOMMAND "source ${script_addr}"
122#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" \
123 " allocate=6M"
124
125#define XMK_STR(x) #x
126#define MK_STR(x) XMK_STR(x)
127
128#define CONFIG_EXTRA_ENV_SETTINGS \
129 "console_nr=0\0" \
130 "console=no\0" \
131 "stdin=serial\0" \
132 "stdout=serial\0" \
133 "stderr=serial\0" \
134 "fpga=0\0" \
135 "fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \
136 "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \
137 "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \
138 "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \
139 "script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0" \
140 "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \
141 "mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \
142 "mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \
143 "mv_scratch_addr=" MK_STR(MV_SCRATCH_ADDR) "\0" \
144 "mv_scratch_length=" MK_STR(MV_SCRATCH_LENGTH) "\0" \
145 "mv_version=" U_BOOT_VERSION "\0" \
146 "dhcp_client_id=" MK_STR(MV_CI) "\0" \
147 "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0" \
148 "netretry=no\0" \
149 "use_static_ipaddr=no\0" \
150 "static_ipaddr=192.168.0.101\0" \
151 "static_netmask=255.255.255.0\0" \
152 "static_gateway=0.0.0.0\0" \
153 "initrd_name=uInitrd.mvsmr-rfs\0" \
154 "zcip=yes\0" \
155 "netboot=no\0" \
156 ""
157
158#undef XMK_STR
159#undef MK_STR
160
161/*
162 * IPB Bus clocking configuration.
163 */
164#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
165
166/*
167 * Flash configuration
168 */
169#undef CONFIG_FLASH_16BIT
170#define CONFIG_SYS_FLASH_CFI
171#define CONFIG_FLASH_CFI_DRIVER
172#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
173#define CONFIG_SYS_FLASH_EMPTY_INFO
174
175#define CONFIG_SYS_FLASH_ERASE_TOUT 50000
176#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
177
178#define CONFIG_SYS_MAX_FLASH_BANKS 1
179#define CONFIG_SYS_MAX_FLASH_SECT 256
180
181#define CONFIG_SYS_LOWBOOT
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200182#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
Andre Schwarz1f2463d2010-04-01 21:26:55 +0200183#define CONFIG_SYS_FLASH_SIZE 0x00800000
184
185/*
186 * Environment settings
187 */
188#define CONFIG_ENV_IS_IN_FLASH
189#undef CONFIG_SYS_FLASH_PROTECTION
Andre Schwarz1f2463d2010-04-01 21:26:55 +0200190#define CONFIG_OVERWRITE_ETHADDR_ONCE
191
192#define CONFIG_ENV_OFFSET 0x8000
193#define CONFIG_ENV_SIZE 0x2000
194#define CONFIG_ENV_SECT_SIZE 0x2000
195
196/* used by linker script to wrap code around */
197#define CONFIG_SCRIPT_OFFSET 0x6000
198#define CONFIG_SCRIPT_SECT_SIZE 0x2000
199
200/*
201 * Memory map
202 */
203#define CONFIG_SYS_MBAR 0xF0000000
204#define CONFIG_SYS_SDRAM_BASE 0x00000000
205#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
206
207#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denk553f0982010-10-26 13:32:32 +0200208#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
Andre Schwarz1f2463d2010-04-01 21:26:55 +0200209
Wolfgang Denk553f0982010-10-26 13:32:32 +0200210#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200211 GENERATED_GBL_DATA_SIZE)
Andre Schwarz1f2463d2010-04-01 21:26:55 +0200212#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
213
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200214#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Andre Schwarz1f2463d2010-04-01 21:26:55 +0200215#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
216#define CONFIG_SYS_RAMBOOT 1
217#endif
218
219/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
220#define CONFIG_SYS_MONITOR_LEN (512 << 10)
221#define CONFIG_SYS_MALLOC_LEN (512 << 10)
222#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
223
224/*
225 * I2C configuration
226 */
227#define CONFIG_HARD_I2C 1
228#define CONFIG_SYS_I2C_MODULE 1
229#define CONFIG_SYS_I2C_SPEED 86000
230#define CONFIG_SYS_I2C_SLAVE 0x7F
231
232/*
233 * Ethernet configuration
234 */
235#define CONFIG_NET_RETRY_COUNT 5
236
237#define CONFIG_MPC5xxx_FEC
238#define CONFIG_MPC5xxx_FEC_MII100
239#define CONFIG_PHY_ADDR 0x00
240#define CONFIG_NETDEV eth0
241
242/*
243 * Miscellaneous configurable options
244 */
245#define CONFIG_SYS_HUSH_PARSER
246#define CONFIG_CMDLINE_EDITING
Andre Schwarz1f2463d2010-04-01 21:26:55 +0200247#undef CONFIG_SYS_LONGHELP
248#define CONFIG_SYS_PROMPT "=> "
249#ifdef CONFIG_CMD_KGDB
250#define CONFIG_SYS_CBSIZE 1024
251#else
252#define CONFIG_SYS_CBSIZE 256
253#endif
254#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
255#define CONFIG_SYS_MAXARGS 16
256#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
257
258#define CONFIG_SYS_MEMTEST_START 0x00800000
259#define CONFIG_SYS_MEMTEST_END 0x02f00000
260
261#define CONFIG_SYS_HZ 1000
262
263/* default load address */
264#define CONFIG_SYS_LOAD_ADDR 0x02000000
265/* default location for tftp and bootm */
266#define CONFIG_LOADADDR 0x00200000
267
268/*
269 * Various low-level settings
270 */
271#define CONFIG_SYS_GPS_PORT_CONFIG 0x00050044
272
273#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI)
274#define CONFIG_SYS_HID0_FINAL HID0_ICE
275
276#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
277#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
278#define CONFIG_SYS_BOOTCS_CFG 0x00047800
279#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
280#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
281
282#define CONFIG_SYS_CS_BURST 0x000000f0
283#define CONFIG_SYS_CS_DEADCYCLE 0x33333303
284
285#define CONFIG_SYS_RESET_ADDRESS 0x00000100
286
287#undef FPGA_DEBUG
288#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
289#define CONFIG_FPGA CONFIG_SYS_XILINX_SPARTAN2
290#define CONFIG_FPGA_XILINX 1
291#define CONFIG_FPGA_SPARTAN2 1
292#define CONFIG_FPGA_COUNT 1
293
294#endif