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Marek Vasutbc3a4a52010-04-05 01:50:57 +02001/*
2 * Aeronix Zipit Z2 configuration file
3 *
4 * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
22#ifndef __CONFIG_H
23#define __CONFIG_H
24
25/*
26 * High Level Board Configuration Options
27 */
Marek Vasutabc20ab2011-11-26 07:20:07 +010028#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
Marek Vasutbc3a4a52010-04-05 01:50:57 +020029#define CONFIG_ZIPITZ2 1 /* Zipit Z2 board */
Marek Vasut9b3d1672010-10-20 22:02:16 +020030#define CONFIG_SYS_TEXT_BASE 0x0
Marek Vasutbc3a4a52010-04-05 01:50:57 +020031
Helmut Raiger9660e442011-10-20 04:19:47 +000032#undef CONFIG_BOARD_LATE_INIT
Marek Vasutbc3a4a52010-04-05 01:50:57 +020033#undef CONFIG_SKIP_LOWLEVEL_INIT
Marek Vasutaac316a2012-03-08 05:41:23 +000034#define CONFIG_PREBOOT
Marek Vasutbc3a4a52010-04-05 01:50:57 +020035
36/*
37 * Environment settings
38 */
39#define CONFIG_ENV_OVERWRITE
40#define CONFIG_ENV_IS_IN_FLASH 1
41#define CONFIG_ENV_ADDR 0x40000
42#define CONFIG_ENV_SIZE 0x20000
43
Marek Vasut24e84c32010-09-30 12:22:38 +020044#define CONFIG_SYS_MALLOC_LEN (128*1024)
Marek Vasut24e84c32010-09-30 12:22:38 +020045#define CONFIG_ARCH_CPU_INIT
Marek Vasutbc3a4a52010-04-05 01:50:57 +020046
47#define CONFIG_BOOTCOMMAND \
Vasily Khoruzhick81f731c2012-01-25 22:54:33 +030048 "if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\
49 "then " \
Marek Vasutbc3a4a52010-04-05 01:50:57 +020050 "source 0xa0000000; " \
51 "else " \
52 "bootm 0x60000; " \
53 "fi; "
54#define CONFIG_BOOTARGS \
55 "console=tty0 console=ttyS2,115200 fbcon=rotate:3"
56#define CONFIG_TIMESTAMP
57#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
58#define CONFIG_CMDLINE_TAG
59#define CONFIG_SETUP_MEMORY_TAGS
Marek Vasut24e84c32010-09-30 12:22:38 +020060#define CONFIG_SYS_TEXT_BASE 0x0
Marek Vasutbc3a4a52010-04-05 01:50:57 +020061#define CONFIG_LZMA /* LZMA compression support */
62
63/*
64 * Serial Console Configuration
65 * STUART - the lower serial port on Colibri board
66 */
67#define CONFIG_PXA_SERIAL
68#define CONFIG_STUART 1
69#define CONFIG_BAUDRATE 115200
Marek Vasutbc3a4a52010-04-05 01:50:57 +020070
71/*
72 * Bootloader Components Configuration
73 */
74#include <config_cmd_default.h>
75
76#undef CONFIG_CMD_NET
Sebastien Carlier6d8962e2010-11-05 15:48:07 +010077#undef CONFIG_CMD_NFS
Marek Vasutbc3a4a52010-04-05 01:50:57 +020078#define CONFIG_CMD_ENV
79#undef CONFIG_CMD_IMLS
80#define CONFIG_CMD_MMC
81#define CONFIG_CMD_SPI
82
83/*
84 * MMC Card Configuration
85 */
86#ifdef CONFIG_CMD_MMC
87#define CONFIG_MMC
Vasily Khoruzhick81f731c2012-01-25 22:54:33 +030088#define CONFIG_GENERIC_MMC
89#define CONFIG_PXA_MMC_GENERIC
Marek Vasutbc3a4a52010-04-05 01:50:57 +020090#define CONFIG_SYS_MMC_BASE 0xF0000000
91#define CONFIG_CMD_FAT
92#define CONFIG_CMD_EXT2
93#define CONFIG_DOS_PARTITION
94#endif
95
96/*
97 * SPI and LCD
98 */
99#ifdef CONFIG_CMD_SPI
100#define CONFIG_SOFT_SPI
101#define CONFIG_LCD
102#define CONFIG_LMS283GF05
103#define CONFIG_VIDEO_LOGO
104#define CONFIG_CMD_BMP
105#define CONFIG_SPLASH_SCREEN
106#define CONFIG_SPLASH_SCREEN_ALIGN
107#define CONFIG_VIDEO_BMP_GZIP
108#define CONFIG_VIDEO_BMP_RLE8
109#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
110#undef SPI_INIT
111
112#define SPI_DELAY udelay(10)
113#define SPI_SDA(val) zipitz2_spi_sda(val)
114#define SPI_SCL(val) zipitz2_spi_scl(val)
115#define SPI_READ zipitz2_spi_read()
116#ifndef __ASSEMBLY__
117void zipitz2_spi_sda(int);
118void zipitz2_spi_scl(int);
119unsigned char zipitz2_spi_read(void);
120#endif
121#endif
122
123/*
124 * KGDB
125 */
126#ifdef CONFIG_CMD_KGDB
127#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
128#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
129#endif
130
131/*
132 * HUSH Shell Configuration
133 */
134#define CONFIG_SYS_HUSH_PARSER 1
Marek Vasutbc3a4a52010-04-05 01:50:57 +0200135
136#define CONFIG_SYS_LONGHELP /* undef to save memory */
137#ifdef CONFIG_SYS_HUSH_PARSER
138#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
139#else
140#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
141#endif
142#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
143#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
144#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
145#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
146#define CONFIG_SYS_DEVICE_NULLDEV 1
147
148/*
149 * Clock Configuration
150 */
151#undef CONFIG_SYS_CLKS_IN_HZ
152#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */
153#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
154
155/*
Vasily Khoruzhick76d4ae22012-01-13 10:11:44 +0300156 * SRAM Map
157 */
158#define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */
159#define PHYS_SRAM_SIZE 0x00040000 /* 256k */
160
161/*
Marek Vasutbc3a4a52010-04-05 01:50:57 +0200162 * DRAM Map
163 */
164#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */
165#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
166#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
167
168#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
169#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */
170
171#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
172#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
173
174#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
175
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200176#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Vasily Khoruzhick76d4ae22012-01-13 10:11:44 +0300177#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048)
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200178
Marek Vasutbc3a4a52010-04-05 01:50:57 +0200179/*
180 * NOR FLASH
181 */
182#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
183#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
184#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */
185#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
186
187#define CONFIG_SYS_FLASH_CFI
188#define CONFIG_FLASH_CFI_DRIVER 1
189#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
190
191#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
192#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
193
194#define CONFIG_SYS_MAX_FLASH_BANKS 1
195#define CONFIG_SYS_MAX_FLASH_SECT 256
196
197#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
198
199#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ)
200#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ)
201#define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ)
202#define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ)
203#define CONFIG_SYS_FLASH_PROTECTION
204
205/*
206 * GPIO settings
207 */
208#define CONFIG_SYS_GAFR0_L_VAL 0x02000140
209#define CONFIG_SYS_GAFR0_U_VAL 0x59188000
210#define CONFIG_SYS_GAFR1_L_VAL 0x63900002
211#define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950
212#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa
213#define CONFIG_SYS_GAFR2_U_VAL 0x29000308
214#define CONFIG_SYS_GAFR3_L_VAL 0x54000000
215#define CONFIG_SYS_GAFR3_U_VAL 0x000000d5
216#define CONFIG_SYS_GPCR0_VAL 0x00000000
217#define CONFIG_SYS_GPCR1_VAL 0x00000020
218#define CONFIG_SYS_GPCR2_VAL 0x00000000
219#define CONFIG_SYS_GPCR3_VAL 0x00000000
220#define CONFIG_SYS_GPDR0_VAL 0xdafcee00
221#define CONFIG_SYS_GPDR1_VAL 0xffa3aaab
Marek Vasut24e84c32010-09-30 12:22:38 +0200222#define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff
Marek Vasutbc3a4a52010-04-05 01:50:57 +0200223#define CONFIG_SYS_GPDR3_VAL 0x001b1f8a
224#define CONFIG_SYS_GPSR0_VAL 0x06080400
225#define CONFIG_SYS_GPSR1_VAL 0x007f0000
226#define CONFIG_SYS_GPSR2_VAL 0x032a0000
227#define CONFIG_SYS_GPSR3_VAL 0x00000180
228
229#define CONFIG_SYS_PSSR_VAL 0x30
230
231/*
232 * Clock settings
233 */
234#define CONFIG_SYS_CKEN 0x00511220
235#define CONFIG_SYS_CCCR 0x00000190
236
237/*
238 * Memory settings
239 */
240#define CONFIG_SYS_MSC0_VAL 0x2ffc38f8
241#define CONFIG_SYS_MSC1_VAL 0x0000ccd1
242#define CONFIG_SYS_MSC2_VAL 0x0000b884
243#define CONFIG_SYS_MDCNFG_VAL 0x08000ba9
244#define CONFIG_SYS_MDREFR_VAL 0x2011a01e
245#define CONFIG_SYS_MDMRS_VAL 0x00000000
246#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
247#define CONFIG_SYS_SXCNFG_VAL 0x40044004
248
249/*
250 * PCMCIA and CF Interfaces
251 */
252#define CONFIG_SYS_MECR_VAL 0x00000001
253#define CONFIG_SYS_MCMEM0_VAL 0x00014307
254#define CONFIG_SYS_MCMEM1_VAL 0x00014307
255#define CONFIG_SYS_MCATT0_VAL 0x0001c787
256#define CONFIG_SYS_MCATT1_VAL 0x0001c787
257#define CONFIG_SYS_MCIO0_VAL 0x0001430f
258#define CONFIG_SYS_MCIO1_VAL 0x0001430f
259
260#endif /* __CONFIG_H */