York Sun | ee52b18 | 2012-10-11 07:13:37 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2009-2012 Freescale Semiconductor, Inc. |
| 3 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
York Sun | ee52b18 | 2012-10-11 07:13:37 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <command.h> |
| 9 | #include <i2c.h> |
| 10 | #include <netdev.h> |
| 11 | #include <linux/compiler.h> |
| 12 | #include <asm/mmu.h> |
| 13 | #include <asm/processor.h> |
| 14 | #include <asm/cache.h> |
| 15 | #include <asm/immap_85xx.h> |
| 16 | #include <asm/fsl_law.h> |
| 17 | #include <asm/fsl_serdes.h> |
| 18 | #include <asm/fsl_portals.h> |
| 19 | #include <asm/fsl_liodn.h> |
| 20 | #include <fm_eth.h> |
| 21 | |
| 22 | #include "../common/qixis.h" |
| 23 | #include "../common/vsc3316_3308.h" |
| 24 | #include "t4qds.h" |
| 25 | #include "t4240qds_qixis.h" |
| 26 | |
| 27 | DECLARE_GLOBAL_DATA_PTR; |
| 28 | |
Timur Tabi | de757a7 | 2012-12-12 11:07:12 +0000 | [diff] [blame] | 29 | static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7}, |
| 30 | {8, 8}, {9, 9}, {14, 14}, {15, 15} }; |
| 31 | |
| 32 | static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5}, |
| 33 | {10, 10}, {11, 11}, {12, 12}, {13, 13} }; |
| 34 | |
| 35 | static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4}, |
| 36 | {10, 11}, {11, 10}, {12, 2}, {13, 3} }; |
| 37 | |
| 38 | static const int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6}, |
| 39 | {8, 9}, {9, 8}, {14, 1}, {15, 0} }; |
| 40 | |
York Sun | ee52b18 | 2012-10-11 07:13:37 +0000 | [diff] [blame] | 41 | int checkboard(void) |
| 42 | { |
Prabhakar Kushwaha | afa2b72 | 2012-12-23 19:26:03 +0000 | [diff] [blame] | 43 | char buf[64]; |
York Sun | ee52b18 | 2012-10-11 07:13:37 +0000 | [diff] [blame] | 44 | u8 sw; |
Simon Glass | 67ac13b | 2012-12-13 20:48:48 +0000 | [diff] [blame] | 45 | struct cpu_type *cpu = gd->arch.cpu; |
York Sun | ee52b18 | 2012-10-11 07:13:37 +0000 | [diff] [blame] | 46 | unsigned int i; |
| 47 | |
| 48 | printf("Board: %sQDS, ", cpu->name); |
Prabhakar Kushwaha | afa2b72 | 2012-12-23 19:26:03 +0000 | [diff] [blame] | 49 | printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ", |
| 50 | QIXIS_READ(id), QIXIS_READ(arch)); |
York Sun | ee52b18 | 2012-10-11 07:13:37 +0000 | [diff] [blame] | 51 | |
| 52 | sw = QIXIS_READ(brdcfg[0]); |
| 53 | sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; |
| 54 | |
| 55 | if (sw < 0x8) |
| 56 | printf("vBank: %d\n", sw); |
| 57 | else if (sw == 0x8) |
| 58 | puts("Promjet\n"); |
| 59 | else if (sw == 0x9) |
| 60 | puts("NAND\n"); |
| 61 | else |
| 62 | printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); |
| 63 | |
Prabhakar Kushwaha | afa2b72 | 2012-12-23 19:26:03 +0000 | [diff] [blame] | 64 | printf("FPGA: v%d (%s), build %d", |
| 65 | (int)QIXIS_READ(scver), qixis_read_tag(buf), |
| 66 | (int)qixis_read_minor()); |
| 67 | /* the timestamp string contains "\n" at the end */ |
| 68 | printf(" on %s", qixis_read_time(buf)); |
| 69 | |
York Sun | ee52b18 | 2012-10-11 07:13:37 +0000 | [diff] [blame] | 70 | /* |
| 71 | * Display the actual SERDES reference clocks as configured by the |
| 72 | * dip switches on the board. Note that the SWx registers could |
| 73 | * technically be set to force the reference clocks to match the |
| 74 | * values that the SERDES expects (or vice versa). For now, however, |
| 75 | * we just display both values and hope the user notices when they |
| 76 | * don't match. |
| 77 | */ |
| 78 | puts("SERDES Reference Clocks: "); |
| 79 | sw = QIXIS_READ(brdcfg[2]); |
| 80 | for (i = 0; i < MAX_SERDES; i++) { |
| 81 | static const char *freq[] = { |
| 82 | "100", "125", "156.25", "161.1328125"}; |
Roy Zang | 9458f6d | 2013-03-25 07:33:15 +0000 | [diff] [blame] | 83 | unsigned int clock = (sw >> (6 - 2 * i)) & 3; |
York Sun | ee52b18 | 2012-10-11 07:13:37 +0000 | [diff] [blame] | 84 | |
| 85 | printf("SERDES%u=%sMHz ", i+1, freq[clock]); |
| 86 | } |
| 87 | puts("\n"); |
| 88 | |
| 89 | return 0; |
| 90 | } |
| 91 | |
| 92 | int select_i2c_ch_pca9547(u8 ch) |
| 93 | { |
| 94 | int ret; |
| 95 | |
| 96 | ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); |
| 97 | if (ret) { |
| 98 | puts("PCA: failed to select proper channel\n"); |
| 99 | return ret; |
| 100 | } |
| 101 | |
| 102 | return 0; |
| 103 | } |
| 104 | |
York Sun | 97c7fe6 | 2013-03-25 07:33:22 +0000 | [diff] [blame] | 105 | /* |
| 106 | * read_voltage from sensor on I2C bus |
| 107 | * We use average of 4 readings, waiting for 532us befor another reading |
| 108 | */ |
| 109 | #define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */ |
| 110 | #define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */ |
| 111 | |
| 112 | static inline int read_voltage(void) |
| 113 | { |
| 114 | int i, ret, voltage_read = 0; |
| 115 | u16 vol_mon; |
| 116 | |
| 117 | for (i = 0; i < NUM_READINGS; i++) { |
| 118 | ret = i2c_read(I2C_VOL_MONITOR_ADDR, |
| 119 | I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2); |
| 120 | if (ret) { |
| 121 | printf("VID: failed to read core voltage\n"); |
| 122 | return ret; |
| 123 | } |
| 124 | if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) { |
| 125 | printf("VID: Core voltage sensor error\n"); |
| 126 | return -1; |
| 127 | } |
| 128 | debug("VID: bus voltage reads 0x%04x\n", vol_mon); |
| 129 | /* LSB = 4mv */ |
| 130 | voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4; |
| 131 | udelay(WAIT_FOR_ADC); |
| 132 | } |
| 133 | /* calculate the average */ |
| 134 | voltage_read /= NUM_READINGS; |
| 135 | |
| 136 | return voltage_read; |
| 137 | } |
| 138 | |
| 139 | /* |
| 140 | * We need to calculate how long before the voltage starts to drop or increase |
| 141 | * It returns with the loop count. Each loop takes several readings (532us) |
| 142 | */ |
| 143 | static inline int wait_for_voltage_change(int vdd_last) |
| 144 | { |
| 145 | int timeout, vdd_current; |
| 146 | |
| 147 | vdd_current = read_voltage(); |
| 148 | /* wait until voltage starts to drop */ |
| 149 | for (timeout = 0; abs(vdd_last - vdd_current) <= 4 && |
| 150 | timeout < 100; timeout++) { |
| 151 | vdd_current = read_voltage(); |
| 152 | } |
| 153 | if (timeout >= 100) { |
| 154 | printf("VID: Voltage adjustment timeout\n"); |
| 155 | return -1; |
| 156 | } |
| 157 | return timeout; |
| 158 | } |
| 159 | |
| 160 | /* |
| 161 | * argument 'wait' is the time we know the voltage difference can be measured |
| 162 | * this function keeps reading the voltage until it is stable |
| 163 | */ |
| 164 | static inline int wait_for_voltage_stable(int wait) |
| 165 | { |
| 166 | int timeout, vdd_current, vdd_last; |
| 167 | |
| 168 | vdd_last = read_voltage(); |
| 169 | udelay(wait * NUM_READINGS * WAIT_FOR_ADC); |
| 170 | /* wait until voltage is stable */ |
| 171 | vdd_current = read_voltage(); |
| 172 | for (timeout = 0; abs(vdd_last - vdd_current) >= 4 && |
| 173 | timeout < 100; timeout++) { |
| 174 | vdd_last = vdd_current; |
| 175 | udelay(wait * NUM_READINGS * WAIT_FOR_ADC); |
| 176 | vdd_current = read_voltage(); |
| 177 | } |
| 178 | if (timeout >= 100) { |
| 179 | printf("VID: Voltage adjustment timeout\n"); |
| 180 | return -1; |
| 181 | } |
| 182 | |
| 183 | return vdd_current; |
| 184 | } |
| 185 | |
| 186 | static inline int set_voltage(u8 vid) |
| 187 | { |
| 188 | int wait, vdd_last; |
| 189 | |
| 190 | vdd_last = read_voltage(); |
| 191 | QIXIS_WRITE(brdcfg[6], vid); |
| 192 | wait = wait_for_voltage_change(vdd_last); |
| 193 | if (wait < 0) |
| 194 | return -1; |
| 195 | debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC); |
| 196 | wait = wait ? wait : 1; |
| 197 | |
| 198 | vdd_last = wait_for_voltage_stable(wait); |
| 199 | if (vdd_last < 0) |
| 200 | return -1; |
| 201 | debug("VID: Current voltage is %d mV\n", vdd_last); |
| 202 | |
| 203 | return vdd_last; |
| 204 | } |
| 205 | |
| 206 | |
York Sun | 0aadf4a | 2013-03-25 07:40:01 +0000 | [diff] [blame] | 207 | static int adjust_vdd(ulong vdd_override) |
York Sun | 97c7fe6 | 2013-03-25 07:33:22 +0000 | [diff] [blame] | 208 | { |
| 209 | int re_enable = disable_interrupts(); |
| 210 | ccsr_gur_t __iomem *gur = |
| 211 | (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
| 212 | u32 fusesr; |
| 213 | u8 vid, vid_current; |
| 214 | int vdd_target, vdd_current, vdd_last; |
| 215 | int ret; |
York Sun | 0aadf4a | 2013-03-25 07:40:01 +0000 | [diff] [blame] | 216 | unsigned long vdd_string_override; |
| 217 | char *vdd_string; |
York Sun | 97c7fe6 | 2013-03-25 07:33:22 +0000 | [diff] [blame] | 218 | static const uint16_t vdd[32] = { |
| 219 | 0, /* unused */ |
| 220 | 9875, /* 0.9875V */ |
| 221 | 9750, |
| 222 | 9625, |
| 223 | 9500, |
| 224 | 9375, |
| 225 | 9250, |
| 226 | 9125, |
| 227 | 9000, |
| 228 | 8875, |
| 229 | 8750, |
| 230 | 8625, |
| 231 | 8500, |
| 232 | 8375, |
| 233 | 8250, |
| 234 | 8125, |
| 235 | 10000, /* 1.0000V */ |
| 236 | 10125, |
| 237 | 10250, |
| 238 | 10375, |
| 239 | 10500, |
| 240 | 10625, |
| 241 | 10750, |
| 242 | 10875, |
| 243 | 11000, |
| 244 | 0, /* reserved */ |
| 245 | }; |
| 246 | struct vdd_drive { |
| 247 | u8 vid; |
| 248 | unsigned voltage; |
| 249 | }; |
| 250 | |
| 251 | ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR); |
| 252 | if (ret) { |
| 253 | debug("VID: I2c failed to switch channel\n"); |
| 254 | ret = -1; |
| 255 | goto exit; |
| 256 | } |
| 257 | |
| 258 | /* get the voltage ID from fuse status register */ |
| 259 | fusesr = in_be32(&gur->dcfg_fusesr); |
| 260 | vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) & |
| 261 | FSL_CORENET_DCFG_FUSESR_VID_MASK; |
| 262 | if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) { |
| 263 | vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) & |
| 264 | FSL_CORENET_DCFG_FUSESR_ALTVID_MASK; |
| 265 | } |
| 266 | vdd_target = vdd[vid]; |
York Sun | 0aadf4a | 2013-03-25 07:40:01 +0000 | [diff] [blame] | 267 | |
| 268 | /* check override variable for overriding VDD */ |
| 269 | vdd_string = getenv("t4240qds_vdd_mv"); |
| 270 | if (vdd_override == 0 && vdd_string && |
| 271 | !strict_strtoul(vdd_string, 10, &vdd_string_override)) |
| 272 | vdd_override = vdd_string_override; |
| 273 | if (vdd_override >= 819 && vdd_override <= 1212) { |
| 274 | vdd_target = vdd_override * 10; /* convert to 1/10 mV */ |
| 275 | debug("VDD override is %lu\n", vdd_override); |
| 276 | } else if (vdd_override != 0) { |
| 277 | printf("Invalid value.\n"); |
| 278 | } |
| 279 | |
York Sun | 97c7fe6 | 2013-03-25 07:33:22 +0000 | [diff] [blame] | 280 | if (vdd_target == 0) { |
| 281 | debug("VID: VID not used\n"); |
| 282 | ret = 0; |
| 283 | goto exit; |
| 284 | } else { |
| 285 | /* round up and divice by 10 to get a value in mV */ |
| 286 | vdd_target = DIV_ROUND_UP(vdd_target, 10); |
| 287 | debug("VID: vid = %d mV\n", vdd_target); |
| 288 | } |
| 289 | |
| 290 | /* |
| 291 | * Check current board VID setting |
| 292 | * Voltage regulator support output to 6.250mv step |
| 293 | * The highes voltage allowed for this board is (vid=0x40) 1.21250V |
| 294 | * the lowest is (vid=0x7f) 0.81875V |
| 295 | */ |
| 296 | vid_current = QIXIS_READ(brdcfg[6]); |
| 297 | vdd_current = 121250 - (vid_current - 0x40) * 625; |
| 298 | debug("VID: Current vid setting is (0x%x) %d mV\n", |
| 299 | vid_current, vdd_current/100); |
| 300 | |
| 301 | /* |
| 302 | * Read voltage monitor to check real voltage. |
| 303 | * Voltage monitor LSB is 4mv. |
| 304 | */ |
| 305 | vdd_last = read_voltage(); |
| 306 | if (vdd_last < 0) { |
| 307 | printf("VID: Could not read voltage sensor abort VID adjustment\n"); |
| 308 | ret = -1; |
| 309 | goto exit; |
| 310 | } |
| 311 | debug("VID: Core voltage is at %d mV\n", vdd_last); |
| 312 | /* |
| 313 | * Adjust voltage to at or 8mV above target. |
| 314 | * Each step of adjustment is 6.25mV. |
| 315 | * Stepping down too fast may cause over current. |
| 316 | */ |
| 317 | while (vdd_last > 0 && vid_current < 0x80 && |
| 318 | vdd_last > (vdd_target + 8)) { |
| 319 | vid_current++; |
| 320 | vdd_last = set_voltage(vid_current); |
| 321 | } |
| 322 | /* |
| 323 | * Check if we need to step up |
| 324 | * This happens when board voltage switch was set too low |
| 325 | */ |
| 326 | while (vdd_last > 0 && vid_current >= 0x40 && |
| 327 | vdd_last < vdd_target + 2) { |
| 328 | vid_current--; |
| 329 | vdd_last = set_voltage(vid_current); |
| 330 | } |
| 331 | if (vdd_last > 0) |
| 332 | printf("VID: Core voltage %d mV\n", vdd_last); |
| 333 | else |
| 334 | ret = -1; |
| 335 | |
| 336 | exit: |
| 337 | if (re_enable) |
| 338 | enable_interrupts(); |
| 339 | return ret; |
| 340 | } |
| 341 | |
York Sun | ee52b18 | 2012-10-11 07:13:37 +0000 | [diff] [blame] | 342 | /* Configure Crossbar switches for Front-Side SerDes Ports */ |
| 343 | int config_frontside_crossbar_vsc3316(void) |
| 344 | { |
| 345 | ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
| 346 | u32 srds_prtcl_s1, srds_prtcl_s2; |
| 347 | int ret; |
| 348 | |
| 349 | ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS); |
| 350 | if (ret) |
| 351 | return ret; |
| 352 | |
| 353 | srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & |
| 354 | FSL_CORENET2_RCWSR4_SRDS1_PRTCL; |
| 355 | srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; |
| 356 | if (srds_prtcl_s1) { |
| 357 | ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8); |
| 358 | if (ret) |
| 359 | return ret; |
| 360 | ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8); |
| 361 | if (ret) |
| 362 | return ret; |
| 363 | } |
| 364 | |
| 365 | srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & |
| 366 | FSL_CORENET2_RCWSR4_SRDS2_PRTCL; |
| 367 | srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; |
| 368 | if (srds_prtcl_s2) { |
| 369 | ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8); |
| 370 | if (ret) |
| 371 | return ret; |
| 372 | ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8); |
| 373 | if (ret) |
| 374 | return ret; |
| 375 | } |
| 376 | |
| 377 | return 0; |
| 378 | } |
| 379 | |
| 380 | int config_backside_crossbar_mux(void) |
| 381 | { |
| 382 | ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
| 383 | u32 srds_prtcl_s3, srds_prtcl_s4; |
| 384 | u8 brdcfg; |
| 385 | |
| 386 | srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) & |
| 387 | FSL_CORENET2_RCWSR4_SRDS3_PRTCL; |
| 388 | srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT; |
| 389 | switch (srds_prtcl_s3) { |
| 390 | case 0: |
| 391 | /* SerDes3 is not enabled */ |
| 392 | break; |
| 393 | case 2: |
| 394 | case 9: |
| 395 | case 10: |
| 396 | /* SD3(0:7) => SLOT5(0:7) */ |
| 397 | brdcfg = QIXIS_READ(brdcfg[12]); |
| 398 | brdcfg &= ~BRDCFG12_SD3MX_MASK; |
| 399 | brdcfg |= BRDCFG12_SD3MX_SLOT5; |
| 400 | QIXIS_WRITE(brdcfg[12], brdcfg); |
| 401 | break; |
| 402 | case 4: |
| 403 | case 6: |
| 404 | case 8: |
| 405 | case 12: |
| 406 | case 14: |
| 407 | case 16: |
| 408 | case 17: |
| 409 | case 19: |
| 410 | case 20: |
| 411 | /* SD3(4:7) => SLOT6(0:3) */ |
| 412 | brdcfg = QIXIS_READ(brdcfg[12]); |
| 413 | brdcfg &= ~BRDCFG12_SD3MX_MASK; |
| 414 | brdcfg |= BRDCFG12_SD3MX_SLOT6; |
| 415 | QIXIS_WRITE(brdcfg[12], brdcfg); |
| 416 | break; |
| 417 | default: |
| 418 | printf("WARNING: unsupported for SerDes3 Protocol %d\n", |
| 419 | srds_prtcl_s3); |
| 420 | return -1; |
| 421 | } |
| 422 | |
| 423 | srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) & |
| 424 | FSL_CORENET2_RCWSR4_SRDS4_PRTCL; |
| 425 | srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT; |
| 426 | switch (srds_prtcl_s4) { |
| 427 | case 0: |
| 428 | /* SerDes4 is not enabled */ |
| 429 | break; |
| 430 | case 2: |
| 431 | /* 10b, SD4(0:7) => SLOT7(0:7) */ |
| 432 | brdcfg = QIXIS_READ(brdcfg[12]); |
| 433 | brdcfg &= ~BRDCFG12_SD4MX_MASK; |
| 434 | brdcfg |= BRDCFG12_SD4MX_SLOT7; |
| 435 | QIXIS_WRITE(brdcfg[12], brdcfg); |
| 436 | break; |
| 437 | case 4: |
| 438 | case 6: |
| 439 | case 8: |
| 440 | /* x1b, SD4(4:7) => SLOT8(0:3) */ |
| 441 | brdcfg = QIXIS_READ(brdcfg[12]); |
| 442 | brdcfg &= ~BRDCFG12_SD4MX_MASK; |
| 443 | brdcfg |= BRDCFG12_SD4MX_SLOT8; |
| 444 | QIXIS_WRITE(brdcfg[12], brdcfg); |
| 445 | break; |
| 446 | case 10: |
| 447 | case 12: |
| 448 | case 14: |
| 449 | case 16: |
| 450 | case 18: |
| 451 | /* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */ |
| 452 | brdcfg = QIXIS_READ(brdcfg[12]); |
| 453 | brdcfg &= ~BRDCFG12_SD4MX_MASK; |
| 454 | brdcfg |= BRDCFG12_SD4MX_AURO_SATA; |
| 455 | QIXIS_WRITE(brdcfg[12], brdcfg); |
| 456 | break; |
| 457 | default: |
| 458 | printf("WARNING: unsupported for SerDes4 Protocol %d\n", |
| 459 | srds_prtcl_s4); |
| 460 | return -1; |
| 461 | } |
| 462 | |
| 463 | return 0; |
| 464 | } |
| 465 | |
| 466 | int board_early_init_r(void) |
| 467 | { |
| 468 | const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; |
| 469 | const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); |
| 470 | |
| 471 | /* |
| 472 | * Remap Boot flash + PROMJET region to caching-inhibited |
| 473 | * so that flash can be erased properly. |
| 474 | */ |
| 475 | |
| 476 | /* Flush d-cache and invalidate i-cache of any FLASH data */ |
| 477 | flush_dcache(); |
| 478 | invalidate_icache(); |
| 479 | |
| 480 | /* invalidate existing TLB entry for flash + promjet */ |
| 481 | disable_tlb(flash_esel); |
| 482 | |
| 483 | set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, |
| 484 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 485 | 0, flash_esel, BOOKE_PAGESZ_256M, 1); |
| 486 | |
| 487 | set_liodns(); |
| 488 | #ifdef CONFIG_SYS_DPAA_QBMAN |
| 489 | setup_portals(); |
| 490 | #endif |
| 491 | |
Ed Swarthout | 9c0a6de | 2013-03-25 07:39:37 +0000 | [diff] [blame] | 492 | /* Disable remote I2C connection to qixis fpga */ |
| 493 | QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE); |
York Sun | ee52b18 | 2012-10-11 07:13:37 +0000 | [diff] [blame] | 494 | |
York Sun | 97c7fe6 | 2013-03-25 07:33:22 +0000 | [diff] [blame] | 495 | /* |
| 496 | * Adjust core voltage according to voltage ID |
| 497 | * This function changes I2C mux to channel 2. |
| 498 | */ |
York Sun | 0aadf4a | 2013-03-25 07:40:01 +0000 | [diff] [blame] | 499 | if (adjust_vdd(0)) |
York Sun | 97c7fe6 | 2013-03-25 07:33:22 +0000 | [diff] [blame] | 500 | printf("Warning: Adjusting core voltage failed.\n"); |
| 501 | |
York Sun | ee52b18 | 2012-10-11 07:13:37 +0000 | [diff] [blame] | 502 | /* Configure board SERDES ports crossbar */ |
| 503 | config_frontside_crossbar_vsc3316(); |
| 504 | config_backside_crossbar_mux(); |
| 505 | select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); |
| 506 | |
| 507 | return 0; |
| 508 | } |
| 509 | |
| 510 | unsigned long get_board_sys_clk(void) |
| 511 | { |
| 512 | u8 sysclk_conf = QIXIS_READ(brdcfg[1]); |
Ed Swarthout | f413881 | 2013-03-25 07:40:10 +0000 | [diff] [blame] | 513 | #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT |
| 514 | /* use accurate clock measurement */ |
| 515 | int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]); |
| 516 | int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); |
| 517 | u32 val; |
| 518 | |
| 519 | val = freq * base; |
| 520 | if (val) { |
| 521 | debug("SYS Clock measurement is: %d\n", val); |
| 522 | return val; |
| 523 | } else { |
| 524 | printf("Warning: SYS clock measurement is invalid, using value from brdcfg1.\n"); |
| 525 | } |
| 526 | #endif |
York Sun | ee52b18 | 2012-10-11 07:13:37 +0000 | [diff] [blame] | 527 | |
| 528 | switch (sysclk_conf & 0x0F) { |
| 529 | case QIXIS_SYSCLK_83: |
| 530 | return 83333333; |
| 531 | case QIXIS_SYSCLK_100: |
| 532 | return 100000000; |
| 533 | case QIXIS_SYSCLK_125: |
| 534 | return 125000000; |
| 535 | case QIXIS_SYSCLK_133: |
| 536 | return 133333333; |
| 537 | case QIXIS_SYSCLK_150: |
| 538 | return 150000000; |
| 539 | case QIXIS_SYSCLK_160: |
| 540 | return 160000000; |
| 541 | case QIXIS_SYSCLK_166: |
| 542 | return 166666666; |
| 543 | } |
| 544 | return 66666666; |
| 545 | } |
| 546 | |
| 547 | unsigned long get_board_ddr_clk(void) |
| 548 | { |
| 549 | u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); |
Ed Swarthout | f413881 | 2013-03-25 07:40:10 +0000 | [diff] [blame] | 550 | #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT |
| 551 | /* use accurate clock measurement */ |
| 552 | int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]); |
| 553 | int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); |
| 554 | u32 val; |
| 555 | |
| 556 | val = freq * base; |
| 557 | if (val) { |
| 558 | debug("DDR Clock measurement is: %d\n", val); |
| 559 | return val; |
| 560 | } else { |
| 561 | printf("Warning: DDR clock measurement is invalid, using value from brdcfg1.\n"); |
| 562 | } |
| 563 | #endif |
York Sun | ee52b18 | 2012-10-11 07:13:37 +0000 | [diff] [blame] | 564 | |
| 565 | switch ((ddrclk_conf & 0x30) >> 4) { |
| 566 | case QIXIS_DDRCLK_100: |
| 567 | return 100000000; |
| 568 | case QIXIS_DDRCLK_125: |
| 569 | return 125000000; |
| 570 | case QIXIS_DDRCLK_133: |
| 571 | return 133333333; |
| 572 | } |
| 573 | return 66666666; |
| 574 | } |
| 575 | |
| 576 | static const char *serdes_clock_to_string(u32 clock) |
| 577 | { |
| 578 | switch (clock) { |
| 579 | case SRDS_PLLCR0_RFCK_SEL_100: |
| 580 | return "100"; |
| 581 | case SRDS_PLLCR0_RFCK_SEL_125: |
| 582 | return "125"; |
| 583 | case SRDS_PLLCR0_RFCK_SEL_156_25: |
| 584 | return "156.25"; |
| 585 | case SRDS_PLLCR0_RFCK_SEL_161_13: |
| 586 | return "161.1328125"; |
| 587 | default: |
| 588 | return "???"; |
| 589 | } |
| 590 | } |
| 591 | |
| 592 | int misc_init_r(void) |
| 593 | { |
| 594 | u8 sw; |
| 595 | serdes_corenet_t *srds_regs = |
| 596 | (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; |
| 597 | u32 actual[MAX_SERDES]; |
| 598 | unsigned int i; |
| 599 | |
| 600 | sw = QIXIS_READ(brdcfg[2]); |
| 601 | for (i = 0; i < MAX_SERDES; i++) { |
Roy Zang | 9458f6d | 2013-03-25 07:33:15 +0000 | [diff] [blame] | 602 | unsigned int clock = (sw >> (6 - 2 * i)) & 3; |
York Sun | ee52b18 | 2012-10-11 07:13:37 +0000 | [diff] [blame] | 603 | switch (clock) { |
| 604 | case 0: |
| 605 | actual[i] = SRDS_PLLCR0_RFCK_SEL_100; |
| 606 | break; |
| 607 | case 1: |
| 608 | actual[i] = SRDS_PLLCR0_RFCK_SEL_125; |
| 609 | break; |
| 610 | case 2: |
| 611 | actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; |
| 612 | break; |
| 613 | case 3: |
| 614 | actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13; |
| 615 | break; |
| 616 | } |
| 617 | } |
| 618 | |
| 619 | for (i = 0; i < MAX_SERDES; i++) { |
| 620 | u32 pllcr0 = srds_regs->bank[i].pllcr0; |
| 621 | u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; |
| 622 | if (expected != actual[i]) { |
| 623 | printf("Warning: SERDES%u expects reference clock" |
| 624 | " %sMHz, but actual is %sMHz\n", i + 1, |
| 625 | serdes_clock_to_string(expected), |
| 626 | serdes_clock_to_string(actual[i])); |
| 627 | } |
| 628 | } |
| 629 | |
| 630 | return 0; |
| 631 | } |
| 632 | |
| 633 | void ft_board_setup(void *blob, bd_t *bd) |
| 634 | { |
| 635 | phys_addr_t base; |
| 636 | phys_size_t size; |
| 637 | |
| 638 | ft_cpu_setup(blob, bd); |
| 639 | |
| 640 | base = getenv_bootm_low(); |
| 641 | size = getenv_bootm_size(); |
| 642 | |
| 643 | fdt_fixup_memory(blob, (u64)base, (u64)size); |
| 644 | |
| 645 | #ifdef CONFIG_PCI |
| 646 | pci_of_setup(blob, bd); |
| 647 | #endif |
| 648 | |
| 649 | fdt_fixup_liodn(blob); |
| 650 | fdt_fixup_dr_usb(blob, bd); |
| 651 | |
| 652 | #ifdef CONFIG_SYS_DPAA_FMAN |
| 653 | fdt_fixup_fman_ethernet(blob); |
| 654 | fdt_fixup_board_enet(blob); |
| 655 | #endif |
| 656 | } |
Shaveta Leekha | 4457e3e | 2012-12-23 19:25:50 +0000 | [diff] [blame] | 657 | |
| 658 | /* |
York Sun | 9cefbd6 | 2013-03-25 07:39:24 +0000 | [diff] [blame] | 659 | * This function is called by bdinfo to print detail board information. |
| 660 | * As an exmaple for future board, we organize the messages into |
| 661 | * several sections. If applicable, the message is in the format of |
| 662 | * <name> = <value> |
| 663 | * It should aligned with normal output of bdinfo command. |
| 664 | * |
| 665 | * Voltage: Core, DDR and another configurable voltages |
| 666 | * Clock : Critical clocks which are not printed already |
| 667 | * RCW : RCW source if not printed already |
| 668 | * Misc : Other important information not in above catagories |
| 669 | */ |
| 670 | void board_detail(void) |
| 671 | { |
| 672 | int i; |
| 673 | u8 brdcfg[16], dutcfg[16], rst_ctl; |
| 674 | int vdd, rcwsrc; |
| 675 | static const char * const clk[] = {"66.67", "100", "125", "133.33"}; |
| 676 | |
| 677 | for (i = 0; i < 16; i++) { |
| 678 | brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i); |
| 679 | dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i); |
| 680 | } |
| 681 | |
| 682 | /* Voltage secion */ |
| 683 | if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR)) { |
| 684 | vdd = read_voltage(); |
| 685 | if (vdd > 0) |
| 686 | printf("Core voltage= %d mV\n", vdd); |
| 687 | select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); |
| 688 | } |
| 689 | |
| 690 | printf("XVDD = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25); |
| 691 | |
| 692 | /* clock section */ |
| 693 | printf("SYSCLK = %s MHz\nDDRCLK = %s MHz\n", |
| 694 | clk[(brdcfg[11] >> 2) & 0x3], clk[brdcfg[11] & 3]); |
| 695 | |
| 696 | /* RCW section */ |
| 697 | rcwsrc = (dutcfg[0] << 1) + (dutcfg[1] & 1); |
| 698 | puts("RCW source = "); |
| 699 | switch (rcwsrc) { |
| 700 | case 0x017: |
| 701 | case 0x01f: |
| 702 | puts("8-bit NOR\n"); |
| 703 | break; |
| 704 | case 0x027: |
| 705 | case 0x02F: |
| 706 | puts("16-bit NOR\n"); |
| 707 | break; |
| 708 | case 0x040: |
| 709 | puts("SDHC/eMMC\n"); |
| 710 | break; |
| 711 | case 0x044: |
| 712 | puts("SPI 16-bit addressing\n"); |
| 713 | break; |
| 714 | case 0x045: |
| 715 | puts("SPI 24-bit addressing\n"); |
| 716 | break; |
| 717 | case 0x048: |
| 718 | puts("I2C normal addressing\n"); |
| 719 | break; |
| 720 | case 0x049: |
| 721 | puts("I2C extended addressing\n"); |
| 722 | break; |
| 723 | case 0x108: |
| 724 | case 0x109: |
| 725 | case 0x10a: |
| 726 | case 0x10b: |
| 727 | puts("8-bit NAND, 2KB\n"); |
| 728 | break; |
| 729 | default: |
| 730 | if ((rcwsrc >= 0x080) && (rcwsrc <= 0x09f)) |
| 731 | puts("Hard-coded RCW\n"); |
| 732 | else if ((rcwsrc >= 0x110) && (rcwsrc <= 0x11f)) |
| 733 | puts("8-bit NAND, 4KB\n"); |
| 734 | else |
| 735 | puts("unknown\n"); |
| 736 | break; |
| 737 | } |
| 738 | |
| 739 | /* Misc section */ |
| 740 | rst_ctl = QIXIS_READ(rst_ctl); |
| 741 | puts("HRESET_REQ = "); |
| 742 | switch (rst_ctl & 0x30) { |
| 743 | case 0x00: |
| 744 | puts("Ignored\n"); |
| 745 | break; |
| 746 | case 0x10: |
| 747 | puts("Assert HRESET\n"); |
| 748 | break; |
| 749 | case 0x30: |
| 750 | puts("Reset system\n"); |
| 751 | break; |
| 752 | default: |
| 753 | puts("N/A\n"); |
| 754 | break; |
| 755 | } |
| 756 | } |
| 757 | |
| 758 | /* |
Shaveta Leekha | 4457e3e | 2012-12-23 19:25:50 +0000 | [diff] [blame] | 759 | * Reverse engineering switch settings. |
| 760 | * Some bits cannot be figured out. They will be displayed as |
| 761 | * underscore in binary format. mask[] has those bits. |
| 762 | * Some bits are calculated differently than the actual switches |
| 763 | * if booting with overriding by FPGA. |
| 764 | */ |
| 765 | void qixis_dump_switch(void) |
| 766 | { |
| 767 | int i; |
| 768 | u8 sw[9]; |
| 769 | |
| 770 | /* |
| 771 | * Any bit with 1 means that bit cannot be reverse engineered. |
| 772 | * It will be displayed as _ in binary format. |
| 773 | */ |
York Sun | e1379b0 | 2013-03-25 07:40:14 +0000 | [diff] [blame] | 774 | static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xcf, 0x3f, 0x1f}; |
Shaveta Leekha | 4457e3e | 2012-12-23 19:25:50 +0000 | [diff] [blame] | 775 | char buf[10]; |
| 776 | u8 brdcfg[16], dutcfg[16]; |
| 777 | |
| 778 | for (i = 0; i < 16; i++) { |
| 779 | brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i); |
| 780 | dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i); |
| 781 | } |
| 782 | |
| 783 | sw[0] = dutcfg[0]; |
| 784 | sw[1] = (dutcfg[1] << 0x07) | \ |
| 785 | ((dutcfg[12] & 0xC0) >> 1) | \ |
| 786 | ((dutcfg[11] & 0xE0) >> 3) | \ |
| 787 | ((dutcfg[6] & 0x80) >> 6) | \ |
| 788 | ((dutcfg[1] & 0x80) >> 7); |
| 789 | sw[2] = ((brdcfg[1] & 0x0f) << 4) | \ |
| 790 | ((brdcfg[1] & 0x30) >> 2) | \ |
| 791 | ((brdcfg[1] & 0x40) >> 5) | \ |
| 792 | ((brdcfg[1] & 0x80) >> 7); |
| 793 | sw[3] = brdcfg[2]; |
| 794 | sw[4] = ((dutcfg[2] & 0x01) << 7) | \ |
| 795 | ((dutcfg[2] & 0x06) << 4) | \ |
| 796 | ((~QIXIS_READ(present)) & 0x10) | \ |
| 797 | ((brdcfg[3] & 0x80) >> 4) | \ |
| 798 | ((brdcfg[3] & 0x01) << 2) | \ |
| 799 | ((brdcfg[6] == 0x62) ? 3 : \ |
| 800 | ((brdcfg[6] == 0x5a) ? 2 : \ |
| 801 | ((brdcfg[6] == 0x5e) ? 1 : 0))); |
| 802 | sw[5] = ((brdcfg[0] & 0x0f) << 4) | \ |
| 803 | ((QIXIS_READ(rst_ctl) & 0x30) >> 2) | \ |
| 804 | ((brdcfg[0] & 0x40) >> 5); |
York Sun | e1379b0 | 2013-03-25 07:40:14 +0000 | [diff] [blame] | 805 | sw[6] = (brdcfg[11] & 0x20) | |
| 806 | ((brdcfg[5] & 0x02) << 3); |
Shaveta Leekha | 4457e3e | 2012-12-23 19:25:50 +0000 | [diff] [blame] | 807 | sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) | \ |
| 808 | ((brdcfg[5] & 0x10) << 2); |
| 809 | sw[8] = ((brdcfg[12] & 0x08) << 4) | \ |
| 810 | ((brdcfg[12] & 0x03) << 5); |
| 811 | |
| 812 | puts("DIP switch (reverse-engineering)\n"); |
| 813 | for (i = 0; i < 9; i++) { |
| 814 | printf("SW%d = 0b%s (0x%02x)\n", |
| 815 | i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]); |
| 816 | } |
| 817 | } |
York Sun | 0aadf4a | 2013-03-25 07:40:01 +0000 | [diff] [blame] | 818 | |
| 819 | static int do_vdd_adjust(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
| 820 | { |
| 821 | ulong override; |
| 822 | |
| 823 | if (argc < 2) |
| 824 | return CMD_RET_USAGE; |
| 825 | if (!strict_strtoul(argv[1], 10, &override)) |
| 826 | adjust_vdd(override); /* the value is checked by callee */ |
| 827 | else |
| 828 | return CMD_RET_USAGE; |
| 829 | |
| 830 | return 0; |
| 831 | } |
| 832 | |
| 833 | U_BOOT_CMD( |
| 834 | vdd_override, 2, 0, do_vdd_adjust, |
| 835 | "Override VDD", |
| 836 | "- override with the voltage specified in mV, eg. 1050" |
| 837 | ); |