Stefan Roese | 16c0cc1 | 2007-03-21 13:39:57 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2007 |
| 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 4 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
Stefan Roese | 16c0cc1 | 2007-03-21 13:39:57 +0100 | [diff] [blame] | 6 | */ |
| 7 | |
Stefan Roese | 3cb86f3 | 2007-03-24 15:45:34 +0100 | [diff] [blame] | 8 | /* define DEBUG for debugging output (obviously ;-)) */ |
| 9 | #if 0 |
| 10 | #define DEBUG |
Stefan Roese | 16c0cc1 | 2007-03-21 13:39:57 +0100 | [diff] [blame] | 11 | #endif |
| 12 | |
Stefan Roese | 3cb86f3 | 2007-03-24 15:45:34 +0100 | [diff] [blame] | 13 | #include <common.h> |
| 14 | #include <asm/processor.h> |
| 15 | #include <asm/io.h> |
Stefan Roese | 0988776 | 2010-09-16 14:30:37 +0200 | [diff] [blame] | 16 | #include <asm/ppc4xx-gpio.h> |
Stefan Roese | 3cb86f3 | 2007-03-24 15:45:34 +0100 | [diff] [blame] | 17 | |
Simon Glass | 088454c | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 18 | DECLARE_GLOBAL_DATA_PTR; |
| 19 | |
Stefan Roese | df8a24c | 2007-06-19 16:42:31 +0200 | [diff] [blame] | 20 | extern void board_pll_init_f(void); |
| 21 | |
Stefan Roese | 16c0cc1 | 2007-03-21 13:39:57 +0100 | [diff] [blame] | 22 | static void cram_bcr_write(u32 wr_val) |
| 23 | { |
Stefan Roese | 3cb86f3 | 2007-03-24 15:45:34 +0100 | [diff] [blame] | 24 | wr_val <<= 2; |
Stefan Roese | 16c0cc1 | 2007-03-21 13:39:57 +0100 | [diff] [blame] | 25 | |
Stefan Roese | 3cb86f3 | 2007-03-24 15:45:34 +0100 | [diff] [blame] | 26 | /* set CRAM_CRE to 1 */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 27 | gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 1); |
Stefan Roese | 16c0cc1 | 2007-03-21 13:39:57 +0100 | [diff] [blame] | 28 | |
Stefan Roese | 3cb86f3 | 2007-03-24 15:45:34 +0100 | [diff] [blame] | 29 | /* Write BCR to CRAM on CS1 */ |
| 30 | out32(wr_val + 0x00200000, 0); |
| 31 | debug("CRAM VAL: %08x for CS1 ", wr_val + 0x00200000); |
Stefan Roese | 16c0cc1 | 2007-03-21 13:39:57 +0100 | [diff] [blame] | 32 | |
Stefan Roese | 3cb86f3 | 2007-03-24 15:45:34 +0100 | [diff] [blame] | 33 | /* Write BCR to CRAM on CS2 */ |
| 34 | out32(wr_val + 0x02200000, 0); |
| 35 | debug("CRAM VAL: %08x for CS2\n", wr_val + 0x02200000); |
Stefan Roese | 16c0cc1 | 2007-03-21 13:39:57 +0100 | [diff] [blame] | 36 | |
Stefan Roese | 3cb86f3 | 2007-03-24 15:45:34 +0100 | [diff] [blame] | 37 | sync(); |
| 38 | eieio(); |
Stefan Roese | 16c0cc1 | 2007-03-21 13:39:57 +0100 | [diff] [blame] | 39 | |
Stefan Roese | 3cb86f3 | 2007-03-24 15:45:34 +0100 | [diff] [blame] | 40 | /* set CRAM_CRE back to 0 (normal operation) */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 41 | gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 0); |
Stefan Roese | 16c0cc1 | 2007-03-21 13:39:57 +0100 | [diff] [blame] | 42 | |
Stefan Roese | 16c0cc1 | 2007-03-21 13:39:57 +0100 | [diff] [blame] | 43 | return; |
| 44 | } |
| 45 | |
Simon Glass | f1683aa | 2017-04-06 12:47:05 -0600 | [diff] [blame^] | 46 | int dram_init(void) |
Stefan Roese | 16c0cc1 | 2007-03-21 13:39:57 +0100 | [diff] [blame] | 47 | { |
Stefan Roese | c440bfe | 2007-06-06 11:42:13 +0200 | [diff] [blame] | 48 | int i; |
Stefan Roese | 3cb86f3 | 2007-03-24 15:45:34 +0100 | [diff] [blame] | 49 | u32 val; |
Stefan Roese | 16c0cc1 | 2007-03-21 13:39:57 +0100 | [diff] [blame] | 50 | |
Stefan Roese | 3cb86f3 | 2007-03-24 15:45:34 +0100 | [diff] [blame] | 51 | /* 1. EBC need to program READY, CLK, ADV for ASync mode */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 52 | gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); |
| 53 | gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); |
| 54 | gpio_config(CONFIG_SYS_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); |
| 55 | gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG); |
Stefan Roese | 16c0cc1 | 2007-03-21 13:39:57 +0100 | [diff] [blame] | 56 | |
Stefan Roese | 3cb86f3 | 2007-03-24 15:45:34 +0100 | [diff] [blame] | 57 | /* 2. EBC in Async mode */ |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 58 | mtebc(PB1AP, 0x078F1EC0); |
| 59 | mtebc(PB2AP, 0x078F1EC0); |
| 60 | mtebc(PB1CR, 0x000BC000); |
| 61 | mtebc(PB2CR, 0x020BC000); |
Stefan Roese | 3cb86f3 | 2007-03-24 15:45:34 +0100 | [diff] [blame] | 62 | |
| 63 | /* 3. Set CRAM in Sync mode */ |
| 64 | cram_bcr_write(0x7012); /* CRAM burst setting */ |
| 65 | |
| 66 | /* 4. EBC in Sync mode */ |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 67 | mtebc(PB1AP, 0x9C0201C0); |
| 68 | mtebc(PB2AP, 0x9C0201C0); |
Stefan Roese | 3cb86f3 | 2007-03-24 15:45:34 +0100 | [diff] [blame] | 69 | |
| 70 | /* Set GPIO pins back to alternate function */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 71 | gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); |
| 72 | gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); |
Stefan Roese | 3cb86f3 | 2007-03-24 15:45:34 +0100 | [diff] [blame] | 73 | |
| 74 | /* Config EBC to use RDY */ |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 75 | mfsdr(SDR0_ULTRA0, val); |
| 76 | mtsdr(SDR0_ULTRA0, val | SDR_ULTRA0_EBCRDYEN); |
Stefan Roese | c440bfe | 2007-06-06 11:42:13 +0200 | [diff] [blame] | 77 | |
| 78 | /* Wait a short while, since for NAND booting this is too fast */ |
| 79 | for (i=0; i<200000; i++) |
| 80 | ; |
Stefan Roese | 3cb86f3 | 2007-03-24 15:45:34 +0100 | [diff] [blame] | 81 | |
Simon Glass | 088454c | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 82 | gd->ram_size = CONFIG_SYS_MBYTES_RAM << 20; |
| 83 | |
| 84 | return 0; |
Stefan Roese | 16c0cc1 | 2007-03-21 13:39:57 +0100 | [diff] [blame] | 85 | } |