blob: 40080f512b5327ee28e04935cc16bbe96dd3dd42 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -04002/*
Oleksandr Zhadanf51d7fc2019-06-17 16:10:23 -04003 * Copyright 2013-2019 Arcturus Networks, Inc.
4 * https://www.arcturusnetworks.com/products/ucp1020/
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -04005 * based on include/configs/p1_p2_rdb_pc.h
6 * original copyright follows:
7 * Copyright 2009-2011 Freescale Semiconductor, Inc.
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -04008 */
9
10/*
11 * QorIQ uCP1020-xx boards configuration file
12 */
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
Oleksandr Zhadanf51d7fc2019-06-17 16:10:23 -040016/*** Arcturus FirmWare Environment */
17
18#define MAX_SERIAL_SIZE 15
19#define MAX_HWADDR_SIZE 17
20
21#define MAX_FWENV_ADDR 4
22
23#define FWENV_MMC 1
24#define FWENV_SPI_FLASH 2
25#define FWENV_NOR_FLASH 3
26/*
27 #define FWENV_TYPE FWENV_MMC
28 #define FWENV_TYPE FWENV_SPI_FLASH
29*/
30#define FWENV_TYPE FWENV_NOR_FLASH
31
32#if (FWENV_TYPE == FWENV_MMC)
33#ifndef CONFIG_SYS_MMC_ENV_DEV
34#define CONFIG_SYS_MMC_ENV_DEV 1
35#endif
36#define FWENV_ADDR1 -1
37#define FWENV_ADDR2 -1
38#define FWENV_ADDR3 -1
39#define FWENV_ADDR4 -1
40#define EMPY_CHAR 0
41#endif
42
43#if (FWENV_TYPE == FWENV_SPI_FLASH)
44#ifndef CONFIG_SF_DEFAULT_SPEED
45#define CONFIG_SF_DEFAULT_SPEED 1000000
46#endif
47#ifndef CONFIG_SF_DEFAULT_MODE
48#define CONFIG_SF_DEFAULT_MODE SPI_MODE0
49#endif
50#ifndef CONFIG_SF_DEFAULT_CS
51#define CONFIG_SF_DEFAULT_CS 0
52#endif
53#ifndef CONFIG_SF_DEFAULT_BUS
54#define CONFIG_SF_DEFAULT_BUS 0
55#endif
56#define FWENV_ADDR1 (0x200 - sizeof(smac))
57#define FWENV_ADDR2 (0x400 - sizeof(smac))
58#define FWENV_ADDR3 (CONFIG_ENV_SECT_SIZE + 0x200 - sizeof(smac))
59#define FWENV_ADDR4 (CONFIG_ENV_SECT_SIZE + 0x400 - sizeof(smac))
60#define EMPY_CHAR 0xff
61#endif
62
63#if (FWENV_TYPE == FWENV_NOR_FLASH)
64#define FWENV_ADDR1 0xEC080000
65#define FWENV_ADDR2 -1
66#define FWENV_ADDR3 -1
67#define FWENV_ADDR4 -1
68#define EMPY_CHAR 0xff
69#endif
70/***********************************/
71
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -040072#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
73#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
74#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
75#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -040076#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
77
78#if defined(CONFIG_TARTGET_UCP1020T1)
79
80#define CONFIG_UCP1020_REV_1_3
81
82#define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -040083
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -040084#define CONFIG_TSEC1
85#define CONFIG_TSEC3
86#define CONFIG_HAS_ETH0
87#define CONFIG_HAS_ETH1
88#define CONFIG_ETHADDR 00:19:D3:FF:FF:FF
89#define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE
90#define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD
91#define CONFIG_IPADDR 10.80.41.229
92#define CONFIG_SERVERIP 10.80.41.227
93#define CONFIG_NETMASK 255.255.252.0
94#define CONFIG_ETHPRIME "eTSEC3"
95
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -040096#define CONFIG_SYS_L2_SIZE (256 << 10)
97
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -040098#endif
99
100#if defined(CONFIG_TARGET_UCP1020)
101
102#define CONFIG_UCP1020
103#define CONFIG_UCP1020_REV_1_3
104
105#define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400106
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400107#define CONFIG_TSEC1
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400108#define CONFIG_TSEC3
109#define CONFIG_HAS_ETH0
110#define CONFIG_HAS_ETH1
111#define CONFIG_HAS_ETH2
112#define CONFIG_ETHADDR 00:06:3B:FF:FF:FF
113#define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE
114#define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD
115#define CONFIG_IPADDR 192.168.1.81
116#define CONFIG_IPADDR1 192.168.1.82
117#define CONFIG_IPADDR2 192.168.1.83
118#define CONFIG_SERVERIP 192.168.1.80
119#define CONFIG_GATEWAYIP 102.168.1.1
120#define CONFIG_NETMASK 255.255.255.0
121#define CONFIG_ETHPRIME "eTSEC1"
122
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400123#define CONFIG_SYS_L2_SIZE (256 << 10)
124
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400125#endif
126
127#ifdef CONFIG_SDCARD
128#define CONFIG_RAMBOOT_SDCARD
129#define CONFIG_SYS_RAMBOOT
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400130#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
131#endif
132
133#ifdef CONFIG_SPIFLASH
134#define CONFIG_RAMBOOT_SPIFLASH
135#define CONFIG_SYS_RAMBOOT
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400136#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
137#endif
138
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400139#define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
140
141#ifndef CONFIG_RESET_VECTOR_ADDRESS
142#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
143#endif
144
145#ifndef CONFIG_SYS_MONITOR_BASE
146#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
147#endif
148
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400149#define CONFIG_ENV_OVERWRITE
150
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400151#define CONFIG_SYS_SATA_MAX_DEVICE 2
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400152#define CONFIG_LBA48
153
154#define CONFIG_SYS_CLK_FREQ 66666666
155#define CONFIG_DDR_CLK_FREQ 66666666
156
157#define CONFIG_HWCONFIG
158
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400159/*
160 * These can be toggled for performance analysis, otherwise use default.
161 */
162#define CONFIG_L2_CACHE
163#define CONFIG_BTB
164
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400165#define CONFIG_ENABLE_36BIT_PHYS
166
167#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
168#define CONFIG_SYS_MEMTEST_END 0x1fffffff
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400169
170#define CONFIG_SYS_CCSRBAR 0xffe00000
171#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
172
173/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
174 SPL code*/
175#ifdef CONFIG_SPL_BUILD
176#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
177#endif
178
179/* DDR Setup */
180#define CONFIG_DDR_ECC_ENABLE
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400181#ifndef CONFIG_DDR_ECC_ENABLE
182#define CONFIG_SYS_DDR_RAW_TIMING
183#define CONFIG_DDR_SPD
184#endif
185#define CONFIG_SYS_SPD_BUS_NUM 1
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400186
187#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
188#define CONFIG_CHIP_SELECTS_PER_CTRL 1
189#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
190#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
191#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
192
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400193#define CONFIG_DIMM_SLOTS_PER_CTLR 1
194
195/* Default settings for DDR3 */
196#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
197#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
198#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
199#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
200#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
201#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
202
203#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
204#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
205#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
206#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
207
208#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
209#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
210#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
211#define CONFIG_SYS_DDR_RCW_1 0x00000000
212#define CONFIG_SYS_DDR_RCW_2 0x00000000
213#ifdef CONFIG_DDR_ECC_ENABLE
214#define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */
215#else
216#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
217#endif
218#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
219#define CONFIG_SYS_DDR_TIMING_4 0x00220001
220#define CONFIG_SYS_DDR_TIMING_5 0x03402400
221
222#define CONFIG_SYS_DDR_TIMING_3 0x00020000
223#define CONFIG_SYS_DDR_TIMING_0 0x00330004
224#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
225#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
226#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
227#define CONFIG_SYS_DDR_MODE_1 0x40461520
228#define CONFIG_SYS_DDR_MODE_2 0x8000c000
229#define CONFIG_SYS_DDR_INTERVAL 0x0C300000
230
231#undef CONFIG_CLOCKS_IN_MHZ
232
233/*
234 * Memory map
235 *
236 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
237 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2)
238 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
239 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable
240 * (early boot only)
241 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
242 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
243 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
244 */
245
246/*
247 * Local Bus Definitions
248 */
249#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
250#define CONFIG_SYS_FLASH_BASE 0xec000000
251
252#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
253
254#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
255 | BR_PS_16 | BR_V)
256
257#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
258
259#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
260#define CONFIG_SYS_FLASH_QUIET_TEST
261#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
262
263#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
264
265#undef CONFIG_SYS_FLASH_CHECKSUM
266#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
267#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
268
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400269#define CONFIG_SYS_FLASH_EMPTY_INFO
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400270
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400271#define CONFIG_SYS_INIT_RAM_LOCK
272#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
273/* Initial L1 address */
274#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
275#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
276#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
277/* Size of used area in RAM */
278#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
279
280#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
281 GENERATED_GBL_DATA_SIZE)
282#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
283
284#define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
285#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
286
287#define CONFIG_SYS_PMC_BASE 0xff980000
288#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
289#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
290 BR_PS_8 | BR_V)
291#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
292 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
293 OR_GPCM_EAD)
294
295#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
296#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
297#ifdef CONFIG_NAND_FSL_ELBC
298#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
299#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
300#endif
301
302/* Serial Port - controlled on board with jumper J8
303 * open - index 2
304 * shorted - index 1
305 */
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400306#undef CONFIG_SERIAL_SOFTWARE_FIFO
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400307#define CONFIG_SYS_NS16550_SERIAL
308#define CONFIG_SYS_NS16550_REG_SIZE 1
309#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
310#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
311#define CONFIG_NS16550_MIN_FUNCTIONS
312#endif
313
314#define CONFIG_SYS_BAUDRATE_TABLE \
315 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
316
317#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
318#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
319
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400320/* I2C */
321#define CONFIG_SYS_I2C
322#define CONFIG_SYS_I2C_FSL
323#define CONFIG_SYS_FSL_I2C_SPEED 400000
324#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
325#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
326#define CONFIG_SYS_FSL_I2C2_SPEED 400000
327#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
328#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
329#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
330#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
331
332#define CONFIG_RTC_DS1337
Chris Packham2bd3cab2017-05-30 12:03:33 +1200333#define CONFIG_RTC_DS1337_NOOSC
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400334#define CONFIG_SYS_I2C_RTC_ADDR 0x68
335#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
336#define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
337#define CONFIG_SYS_I2C_IDT6V49205B 0x69
338
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400339#if defined(CONFIG_PCI)
340/*
341 * General PCI
342 * Memory space is mapped 1-1, but I/O space must start from 0.
343 */
344
345/* controller 2, direct to uli, tgtid 2, Base address 9000 */
346#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9"
347#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
348#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
349#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
350#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
351#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
352#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
353#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
354#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
355
356/* controller 1, Slot 2, tgtid 1, Base address a000 */
357#define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10"
358#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
359#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
360#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
361#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
362#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
363#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
364#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
365#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
366
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400367#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400368#endif /* CONFIG_PCI */
369
370/*
371 * Environment
372 */
373#ifdef CONFIG_ENV_FIT_UCBOOT
374
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400375#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000)
376#define CONFIG_ENV_SIZE 0x20000
377#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
378
379#else
380
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400381
382#ifdef CONFIG_RAMBOOT_SPIFLASH
383
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400384#define CONFIG_ENV_SIZE 0x3000 /* 12KB */
385#define CONFIG_ENV_OFFSET 0x2000 /* 8KB */
386#define CONFIG_ENV_SECT_SIZE 0x1000
387
388#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
389/* Address and size of Redundant Environment Sector */
390#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
391#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
392#endif
393
394#elif defined(CONFIG_RAMBOOT_SDCARD)
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400395#define CONFIG_FSL_FIXED_MMC_LOCATION
396#define CONFIG_ENV_SIZE 0x2000
397#define CONFIG_SYS_MMC_ENV_DEV 0
398
399#elif defined(CONFIG_SYS_RAMBOOT)
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400400#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
401#define CONFIG_ENV_SIZE 0x2000
402
403#else
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400404#define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE)
405#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
406#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
407#define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000)
408#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
409/* Address and size of Redundant Environment Sector */
410#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
411#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
412#endif
413
414#endif
415
416#endif /* CONFIG_ENV_FIT_UCBOOT */
417
418#define CONFIG_LOADS_ECHO /* echo on for serial download */
419#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
420
421/*
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400422 * USB
423 */
424#define CONFIG_HAS_FSL_DR_USB
425
426#if defined(CONFIG_HAS_FSL_DR_USB)
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400427#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
428
Tom Rini8850c5d2017-05-12 22:33:27 -0400429#ifdef CONFIG_USB_EHCI_HCD
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400430#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
431#define CONFIG_USB_EHCI_FSL
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400432#endif
433#endif
434
435#undef CONFIG_WATCHDOG /* watchdog disabled */
436
437#ifdef CONFIG_MMC
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400438#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400439#endif
440
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400441/* Misc Extra Settings */
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400442#undef CONFIG_WATCHDOG /* watchdog disabled */
443
444/*
445 * Miscellaneous configurable options
446 */
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400447#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400448#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
449
450/*
451 * For booting Linux, the board info and command line data
452 * have to be in the first 64 MB of memory, since this is
453 * the maximum mapped by the Linux kernel during initialization.
454 */
455#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
456#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
457
458#if defined(CONFIG_CMD_KGDB)
459#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
460#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
461#endif
462
463/*
464 * Environment Configuration
465 */
466
467#if defined(CONFIG_TSEC_ENET)
468
Alexandru Gagniucfb92bc82017-07-07 11:36:58 -0700469#if defined(CONFIG_UCP1020_REV_1_2) || defined(CONFIG_UCP1020_REV_1_3)
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400470#else
471#error "UCP1020 module revision is not defined !!!"
472#endif
473
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400474#define CONFIG_BOOTP_SERVERIP
475
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400476#define CONFIG_TSEC1_NAME "eTSEC1"
477#define CONFIG_TSEC2_NAME "eTSEC2"
478#define CONFIG_TSEC3_NAME "eTSEC3"
479
480#define TSEC1_PHY_ADDR 4
481#define TSEC2_PHY_ADDR 0
482#define TSEC2_PHY_ADDR_SGMII 0x00
483#define TSEC3_PHY_ADDR 6
484
485#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
486#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
487#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
488
489#define TSEC1_PHYIDX 0
490#define TSEC2_PHYIDX 0
491#define TSEC3_PHYIDX 0
492
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400493#endif
494
Mario Six5bc05432018-03-28 14:38:20 +0200495#define CONFIG_HOSTNAME "UCP1020"
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400496#define CONFIG_ROOTPATH "/opt/nfsroot"
497#define CONFIG_BOOTFILE "uImage"
498#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
499
500/* default location for tftp and bootm */
501#define CONFIG_LOADADDR 1000000
502
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400503#if defined(CONFIG_DONGLE)
504
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400505#define CONFIG_EXTRA_ENV_SETTINGS \
506"bootcmd=run prog_spi_mbrbootcramfs\0" \
507"bootfile=uImage\0" \
508"consoledev=ttyS0\0" \
509"cramfsfile=image.cramfs\0" \
510"dtbaddr=0x00c00000\0" \
511"dtbfile=image.dtb\0" \
512"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
513"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
514"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
515"fileaddr=0x01000000\0" \
516"filesize=0x00080000\0" \
517"flashmbr=sf probe 0; " \
518 "tftp $loadaddr $mbr; " \
519 "sf erase $mbr_offset +$filesize; " \
520 "sf write $loadaddr $mbr_offset $filesize\0" \
521"flashrecovery=tftp $recoveryaddr $cramfsfile; " \
522 "protect off $nor_recoveryaddr +$filesize; " \
523 "erase $nor_recoveryaddr +$filesize; " \
524 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
525 "protect on $nor_recoveryaddr +$filesize\0 " \
526"flashuboot=tftp $ubootaddr $ubootfile; " \
527 "protect off $nor_ubootaddr +$filesize; " \
528 "erase $nor_ubootaddr +$filesize; " \
529 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
530 "protect on $nor_ubootaddr +$filesize\0 " \
531"flashworking=tftp $workingaddr $cramfsfile; " \
532 "protect off $nor_workingaddr +$filesize; " \
533 "erase $nor_workingaddr +$filesize; " \
534 "cp.b $workingaddr $nor_workingaddr $filesize; " \
535 "protect on $nor_workingaddr +$filesize\0 " \
536"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
537"kerneladdr=0x01100000\0" \
538"kernelfile=uImage\0" \
539"loadaddr=0x01000000\0" \
540"mbr=uCP1020d.mbr\0" \
541"mbr_offset=0x00000000\0" \
542"mmbr=uCP1020Quiet.mbr\0" \
543"mmcpart=0:2\0" \
544"mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
545 "mmc erase 1 1; " \
546 "mmc write $loadaddr 1 1\0" \
547"mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \
548 "mmc erase 0x40 0x400; " \
549 "mmc write $loadaddr 0x40 0x400\0" \
550"netdev=eth0\0" \
551"nor_recoveryaddr=0xEC0A0000\0" \
552"nor_ubootaddr=0xEFF80000\0" \
553"nor_workingaddr=0xECFA0000\0" \
554"norbootrecovery=setenv bootargs $recoverybootargs" \
555 " console=$consoledev,$baudrate $othbootargs; " \
556 "run norloadrecovery; " \
557 "bootm $kerneladdr - $dtbaddr\0" \
558"norbootworking=setenv bootargs $workingbootargs" \
559 " console=$consoledev,$baudrate $othbootargs; " \
560 "run norloadworking; " \
561 "bootm $kerneladdr - $dtbaddr\0" \
562"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
563 "setenv cramfsaddr $nor_recoveryaddr; " \
564 "cramfsload $dtbaddr $dtbfile; " \
565 "cramfsload $kerneladdr $kernelfile\0" \
566"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
567 "setenv cramfsaddr $nor_workingaddr; " \
568 "cramfsload $dtbaddr $dtbfile; " \
569 "cramfsload $kerneladdr $kernelfile\0" \
570"prog_spi_mbr=run spi__mbr\0" \
571"prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \
572"prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
573 "run spi__cramfs\0" \
574"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
575 " console=$consoledev,$baudrate $othbootargs; " \
576 "tftp $rootfsaddr $rootfsfile; " \
577 "tftp $loadaddr $kernelfile; " \
578 "tftp $dtbaddr $dtbfile; " \
579 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
580"ramdisk_size=120000\0" \
581"ramdiskfile=rootfs.ext2.gz.uboot\0" \
582"recoveryaddr=0x02F00000\0" \
583"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
584"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
585 "mw.l 0xffe0f008 0x00400000\0" \
586"rootfsaddr=0x02F00000\0" \
587"rootfsfile=rootfs.ext2.gz.uboot\0" \
588"rootpath=/opt/nfsroot\0" \
589"spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
590 "protect off 0xeC000000 +$filesize; " \
591 "erase 0xEC000000 +$filesize; " \
592 "cp.b $loadaddr 0xEC000000 $filesize; " \
593 "cmp.b $loadaddr 0xEC000000 $filesize; " \
594 "protect on 0xeC000000 +$filesize\0" \
595"spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
596 "protect off 0xeFF80000 +$filesize; " \
597 "erase 0xEFF80000 +$filesize; " \
598 "cp.b $loadaddr 0xEFF80000 $filesize; " \
599 "cmp.b $loadaddr 0xEFF80000 $filesize; " \
600 "protect on 0xeFF80000 +$filesize\0" \
601"spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \
602 "sf probe 0; sf erase 0x8000 +$filesize; " \
603 "sf write $loadaddr 0x8000 $filesize\0" \
604"spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \
605 "protect off 0xec0a0000 +$filesize; " \
606 "erase 0xeC0A0000 +$filesize; " \
607 "cp.b $loadaddr 0xeC0A0000 $filesize; " \
608 "protect on 0xec0a0000 +$filesize\0" \
609"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
610 "sf probe 1; sf erase 0 +$filesize; " \
611 "sf write $loadaddr 0 $filesize\0" \
612"spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
613 "sf probe 0; sf erase 0 +$filesize; " \
614 "sf write $loadaddr 0 $filesize\0" \
615"tftpflash=tftpboot $loadaddr $uboot; " \
616 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
617 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
618 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
619 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
620 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
621"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
622"ubootaddr=0x01000000\0" \
623"ubootfile=u-boot.bin\0" \
624"ubootd=u-boot4dongle.bin\0" \
625"upgrade=run flashworking\0" \
626"usb_phy_type=ulpi\0 " \
627"workingaddr=0x02F00000\0" \
628"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
629
630#else
631
632#if defined(CONFIG_UCP1020T1)
633
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400634#define CONFIG_EXTRA_ENV_SETTINGS \
635"bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \
636"bootfile=uImage\0" \
637"consoledev=ttyS0\0" \
638"cramfsfile=image.cramfs\0" \
639"dtbaddr=0x00c00000\0" \
640"dtbfile=image.dtb\0" \
641"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
642"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
643"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
644"fileaddr=0x01000000\0" \
645"filesize=0x00080000\0" \
646"flashmbr=sf probe 0; " \
647 "tftp $loadaddr $mbr; " \
648 "sf erase $mbr_offset +$filesize; " \
649 "sf write $loadaddr $mbr_offset $filesize\0" \
650"flashrecovery=tftp $recoveryaddr $cramfsfile; " \
651 "protect off $nor_recoveryaddr +$filesize; " \
652 "erase $nor_recoveryaddr +$filesize; " \
653 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
654 "protect on $nor_recoveryaddr +$filesize\0 " \
655"flashuboot=tftp $ubootaddr $ubootfile; " \
656 "protect off $nor_ubootaddr +$filesize; " \
657 "erase $nor_ubootaddr +$filesize; " \
658 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
659 "protect on $nor_ubootaddr +$filesize\0 " \
660"flashworking=tftp $workingaddr $cramfsfile; " \
661 "protect off $nor_workingaddr +$filesize; " \
662 "erase $nor_workingaddr +$filesize; " \
663 "cp.b $workingaddr $nor_workingaddr $filesize; " \
664 "protect on $nor_workingaddr +$filesize\0 " \
665"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
666"kerneladdr=0x01100000\0" \
667"kernelfile=uImage\0" \
668"loadaddr=0x01000000\0" \
669"mbr=uCP1020.mbr\0" \
670"mbr_offset=0x00000000\0" \
671"netdev=eth0\0" \
672"nor_recoveryaddr=0xEC0A0000\0" \
673"nor_ubootaddr=0xEFF80000\0" \
674"nor_workingaddr=0xECFA0000\0" \
675"norbootrecovery=setenv bootargs $recoverybootargs" \
676 " console=$consoledev,$baudrate $othbootargs; " \
677 "run norloadrecovery; " \
678 "bootm $kerneladdr - $dtbaddr\0" \
679"norbootworking=setenv bootargs $workingbootargs" \
680 " console=$consoledev,$baudrate $othbootargs; " \
681 "run norloadworking; " \
682 "bootm $kerneladdr - $dtbaddr\0" \
683"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
684 "setenv cramfsaddr $nor_recoveryaddr; " \
685 "cramfsload $dtbaddr $dtbfile; " \
686 "cramfsload $kerneladdr $kernelfile\0" \
687"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
688 "setenv cramfsaddr $nor_workingaddr; " \
689 "cramfsload $dtbaddr $dtbfile; " \
690 "cramfsload $kerneladdr $kernelfile\0" \
691"othbootargs=quiet\0" \
692"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
693 " console=$consoledev,$baudrate $othbootargs; " \
694 "tftp $rootfsaddr $rootfsfile; " \
695 "tftp $loadaddr $kernelfile; " \
696 "tftp $dtbaddr $dtbfile; " \
697 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
698"ramdisk_size=120000\0" \
699"ramdiskfile=rootfs.ext2.gz.uboot\0" \
700"recoveryaddr=0x02F00000\0" \
701"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
702"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
703 "mw.l 0xffe0f008 0x00400000\0" \
704"rootfsaddr=0x02F00000\0" \
705"rootfsfile=rootfs.ext2.gz.uboot\0" \
706"rootpath=/opt/nfsroot\0" \
707"silent=1\0" \
708"tftpflash=tftpboot $loadaddr $uboot; " \
709 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
710 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
711 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
712 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
713 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
714"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
715"ubootaddr=0x01000000\0" \
716"ubootfile=u-boot.bin\0" \
717"upgrade=run flashworking\0" \
718"workingaddr=0x02F00000\0" \
719"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
720
721#else /* For Arcturus Modules */
722
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400723#define CONFIG_EXTRA_ENV_SETTINGS \
724"bootcmd=run norkernel\0" \
725"bootfile=uImage\0" \
726"consoledev=ttyS0\0" \
727"dtbaddr=0x00c00000\0" \
728"dtbfile=image.dtb\0" \
729"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
730"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
731"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
732"fileaddr=0x01000000\0" \
733"filesize=0x00080000\0" \
734"flashmbr=sf probe 0; " \
735 "tftp $loadaddr $mbr; " \
736 "sf erase $mbr_offset +$filesize; " \
737 "sf write $loadaddr $mbr_offset $filesize\0" \
738"flashuboot=tftp $loadaddr $ubootfile; " \
739 "protect off $nor_ubootaddr0 +$filesize; " \
740 "erase $nor_ubootaddr0 +$filesize; " \
741 "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \
742 "protect on $nor_ubootaddr0 +$filesize; " \
743 "protect off $nor_ubootaddr1 +$filesize; " \
744 "erase $nor_ubootaddr1 +$filesize; " \
745 "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \
746 "protect on $nor_ubootaddr1 +$filesize\0 " \
747"format0=protect off $part0base +$part0size; " \
748 "erase $part0base +$part0size\0" \
749"format1=protect off $part1base +$part1size; " \
750 "erase $part1base +$part1size\0" \
751"format2=protect off $part2base +$part2size; " \
752 "erase $part2base +$part2size\0" \
753"format3=protect off $part3base +$part3size; " \
754 "erase $part3base +$part3size\0" \
755"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
756"kerneladdr=0x01100000\0" \
757"kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \
758"kernelfile=uImage\0" \
759"loadaddr=0x01000000\0" \
760"mbr=uCP1020.mbr\0" \
761"mbr_offset=0x00000000\0" \
762"netdev=eth0\0" \
763"nor_ubootaddr0=0xEC000000\0" \
764"nor_ubootaddr1=0xEFF80000\0" \
765"norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
766 "run norkernelload; " \
767 "bootm $kerneladdr - $dtbaddr\0" \
768"norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
769 "setenv cramfsaddr $part0base; " \
770 "cramfsload $dtbaddr $dtbfile; " \
771 "cramfsload $kerneladdr $kernelfile\0" \
772"part0base=0xEC100000\0" \
773"part0size=0x00700000\0" \
774"part1base=0xEC800000\0" \
775"part1size=0x02000000\0" \
776"part2base=0xEE800000\0" \
777"part2size=0x00800000\0" \
778"part3base=0xEF000000\0" \
779"part3size=0x00F80000\0" \
780"partENVbase=0xEC080000\0" \
781"partENVsize=0x00080000\0" \
782"program0=tftp part0-000000.bin; " \
783 "protect off $part0base +$filesize; " \
784 "erase $part0base +$filesize; " \
785 "cp.b $loadaddr $part0base $filesize; " \
786 "echo Verifying...; " \
787 "cmp.b $loadaddr $part0base $filesize\0" \
788"program1=tftp part1-000000.bin; " \
789 "protect off $part1base +$filesize; " \
790 "erase $part1base +$filesize; " \
791 "cp.b $loadaddr $part1base $filesize; " \
792 "echo Verifying...; " \
793 "cmp.b $loadaddr $part1base $filesize\0" \
794"program2=tftp part2-000000.bin; " \
795 "protect off $part2base +$filesize; " \
796 "erase $part2base +$filesize; " \
797 "cp.b $loadaddr $part2base $filesize; " \
798 "echo Verifying...; " \
799 "cmp.b $loadaddr $part2base $filesize\0" \
800"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
801 " console=$consoledev,$baudrate $othbootargs; " \
802 "tftp $rootfsaddr $rootfsfile; " \
803 "tftp $loadaddr $kernelfile; " \
804 "tftp $dtbaddr $dtbfile; " \
805 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
806"ramdisk_size=120000\0" \
807"ramdiskfile=rootfs.ext2.gz.uboot\0" \
808"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
809 "mw.l 0xffe0f008 0x00400000\0" \
810"rootfsaddr=0x02F00000\0" \
811"rootfsfile=rootfs.ext2.gz.uboot\0" \
812"rootpath=/opt/nfsroot\0" \
813"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
814 "sf probe 0; sf erase 0 +$filesize; " \
815 "sf write $loadaddr 0 $filesize\0" \
816"spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
817 "protect off 0xeC000000 +$filesize; " \
818 "erase 0xEC000000 +$filesize; " \
819 "cp.b $loadaddr 0xEC000000 $filesize; " \
820 "cmp.b $loadaddr 0xEC000000 $filesize; " \
821 "protect on 0xeC000000 +$filesize\0" \
822"tftpflash=tftpboot $loadaddr $uboot; " \
823 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
824 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
825 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
826 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
827 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
828"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
829"ubootfile=u-boot.bin\0" \
830"upgrade=run flashuboot\0" \
831"usb_phy_type=ulpi\0 " \
832"boot_nfs= " \
833 "setenv bootargs root=/dev/nfs rw " \
834 "nfsroot=$serverip:$rootpath " \
835 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
836 "console=$consoledev,$baudrate $othbootargs;" \
837 "tftp $loadaddr $bootfile;" \
838 "tftp $fdtaddr $fdtfile;" \
839 "bootm $loadaddr - $fdtaddr\0" \
840"boot_hd = " \
841 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
842 "console=$consoledev,$baudrate $othbootargs;" \
843 "usb start;" \
844 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
845 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
846 "bootm $loadaddr - $fdtaddr\0" \
847"boot_usb_fat = " \
848 "setenv bootargs root=/dev/ram rw " \
849 "console=$consoledev,$baudrate $othbootargs " \
850 "ramdisk_size=$ramdisk_size;" \
851 "usb start;" \
852 "fatload usb 0:2 $loadaddr $bootfile;" \
853 "fatload usb 0:2 $fdtaddr $fdtfile;" \
854 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
855 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
856"boot_usb_ext2 = " \
857 "setenv bootargs root=/dev/ram rw " \
858 "console=$consoledev,$baudrate $othbootargs " \
859 "ramdisk_size=$ramdisk_size;" \
860 "usb start;" \
861 "ext2load usb 0:4 $loadaddr $bootfile;" \
862 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
863 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
864 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
865"boot_nor = " \
866 "setenv bootargs root=/dev/$jffs2nor rw " \
867 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
868 "bootm $norbootaddr - $norfdtaddr\0 " \
869"boot_ram = " \
870 "setenv bootargs root=/dev/ram rw " \
871 "console=$consoledev,$baudrate $othbootargs " \
872 "ramdisk_size=$ramdisk_size;" \
873 "tftp $ramdiskaddr $ramdiskfile;" \
874 "tftp $loadaddr $bootfile;" \
875 "tftp $fdtaddr $fdtfile;" \
876 "bootm $loadaddr $ramdiskaddr $fdtaddr\0"
877
878#endif
879#endif
880
881#endif /* __CONFIG_H */