blob: 10f78155244d7ec6a00b1e2ad77274cc2d2be485 [file] [log] [blame]
Peter Crosthwaite9757b652014-08-28 21:16:39 +10001/*
2 * Digilent ZYBO board DTS
3 *
Michal Simek999667c2015-07-22 11:12:10 +02004 * Copyright (C) 2011 - 2015 Xilinx
5 * Copyright (C) 2012 National Instruments Corp.
Peter Crosthwaite9757b652014-08-28 21:16:39 +10006 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9/dts-v1/;
10#include "zynq-7000.dtsi"
11
12/ {
Michal Simek999667c2015-07-22 11:12:10 +020013 model = "Zynq ZYBO Development Board";
14 compatible = "digilent,zynq-zybo", "xlnx,zynq-7000";
Peter Crosthwaite9757b652014-08-28 21:16:39 +100015
16 aliases {
Michal Simek999667c2015-07-22 11:12:10 +020017 ethernet0 = &gem0;
Peter Crosthwaite9757b652014-08-28 21:16:39 +100018 serial0 = &uart1;
19 };
20
21 memory {
22 device_type = "memory";
Michal Simek999667c2015-07-22 11:12:10 +020023 reg = <0x0 0x20000000>;
Peter Crosthwaite9757b652014-08-28 21:16:39 +100024 };
Michal Simek999667c2015-07-22 11:12:10 +020025
26 chosen {
27 bootargs = "earlyprintk";
28 stdout-path = "serial0:115200n8";
29 };
30
31};
32
33&clkc {
34 ps-clk-frequency = <50000000>;
35};
36
37&gem0 {
38 status = "okay";
39 phy-mode = "rgmii-id";
40 phy-handle = <&ethernet_phy>;
41
42 ethernet_phy: ethernet-phy@0 {
43 reg = <0>;
44 };
45};
46
47&sdhci0 {
48 status = "okay";
49};
50
51&uart1 {
52 status = "okay";
Peter Crosthwaite9757b652014-08-28 21:16:39 +100053};