Marc Zyngier | ecf07a7 | 2014-07-12 14:24:04 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 - ARM Ltd |
| 3 | * Author: Marc Zyngier <marc.zyngier@arm.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 16 | */ |
| 17 | |
| 18 | #ifndef __ARM_PSCI_H__ |
| 19 | #define __ARM_PSCI_H__ |
| 20 | |
Hou Zhiqiang | 2c77416 | 2016-07-29 18:26:36 +0800 | [diff] [blame] | 21 | #define ARM_PSCI_VER_1_0 (0x00010000) |
| 22 | #define ARM_PSCI_VER_0_2 (0x00000002) |
| 23 | |
Beniamino Galvani | 5a07abb | 2016-05-08 08:30:14 +0200 | [diff] [blame] | 24 | /* PSCI 0.1 interface */ |
Marc Zyngier | ecf07a7 | 2014-07-12 14:24:04 +0100 | [diff] [blame] | 25 | #define ARM_PSCI_FN_BASE 0x95c1ba5e |
| 26 | #define ARM_PSCI_FN(n) (ARM_PSCI_FN_BASE + (n)) |
| 27 | |
| 28 | #define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(0) |
| 29 | #define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(1) |
| 30 | #define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(2) |
| 31 | #define ARM_PSCI_FN_MIGRATE ARM_PSCI_FN(3) |
| 32 | |
| 33 | #define ARM_PSCI_RET_SUCCESS 0 |
| 34 | #define ARM_PSCI_RET_NI (-1) |
| 35 | #define ARM_PSCI_RET_INVAL (-2) |
| 36 | #define ARM_PSCI_RET_DENIED (-3) |
Hongbo Zhang | 116339d | 2016-07-21 18:09:36 +0800 | [diff] [blame] | 37 | #define ARM_PSCI_RET_ALREADY_ON (-4) |
| 38 | #define ARM_PSCI_RET_ON_PENDING (-5) |
| 39 | #define ARM_PSCI_RET_INTERNAL_FAILURE (-6) |
| 40 | #define ARM_PSCI_RET_NOT_PRESENT (-7) |
| 41 | #define ARM_PSCI_RET_DISABLED (-8) |
| 42 | #define ARM_PSCI_RET_INVALID_ADDRESS (-9) |
Marc Zyngier | ecf07a7 | 2014-07-12 14:24:04 +0100 | [diff] [blame] | 43 | |
Beniamino Galvani | 5a07abb | 2016-05-08 08:30:14 +0200 | [diff] [blame] | 44 | /* PSCI 0.2 interface */ |
| 45 | #define ARM_PSCI_0_2_FN_BASE 0x84000000 |
| 46 | #define ARM_PSCI_0_2_FN(n) (ARM_PSCI_0_2_FN_BASE + (n)) |
| 47 | |
macro.wave.z@gmail.com | 14bf25d | 2016-12-08 11:58:24 +0800 | [diff] [blame] | 48 | #define ARM_PSCI_0_2_FN64_BASE 0xC4000000 |
| 49 | #define ARM_PSCI_0_2_FN64(n) (ARM_PSCI_0_2_FN64_BASE + (n)) |
| 50 | |
Beniamino Galvani | 5a07abb | 2016-05-08 08:30:14 +0200 | [diff] [blame] | 51 | #define ARM_PSCI_0_2_FN_PSCI_VERSION ARM_PSCI_0_2_FN(0) |
| 52 | #define ARM_PSCI_0_2_FN_CPU_SUSPEND ARM_PSCI_0_2_FN(1) |
| 53 | #define ARM_PSCI_0_2_FN_CPU_OFF ARM_PSCI_0_2_FN(2) |
| 54 | #define ARM_PSCI_0_2_FN_CPU_ON ARM_PSCI_0_2_FN(3) |
| 55 | #define ARM_PSCI_0_2_FN_AFFINITY_INFO ARM_PSCI_0_2_FN(4) |
| 56 | #define ARM_PSCI_0_2_FN_MIGRATE ARM_PSCI_0_2_FN(5) |
| 57 | #define ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE ARM_PSCI_0_2_FN(6) |
| 58 | #define ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU ARM_PSCI_0_2_FN(7) |
| 59 | #define ARM_PSCI_0_2_FN_SYSTEM_OFF ARM_PSCI_0_2_FN(8) |
| 60 | #define ARM_PSCI_0_2_FN_SYSTEM_RESET ARM_PSCI_0_2_FN(9) |
| 61 | |
macro.wave.z@gmail.com | 14bf25d | 2016-12-08 11:58:24 +0800 | [diff] [blame] | 62 | #define ARM_PSCI_0_2_FN64_CPU_SUSPEND ARM_PSCI_0_2_FN64(1) |
| 63 | #define ARM_PSCI_0_2_FN64_CPU_ON ARM_PSCI_0_2_FN64(3) |
| 64 | #define ARM_PSCI_0_2_FN64_AFFINITY_INFO ARM_PSCI_0_2_FN64(4) |
| 65 | #define ARM_PSCI_0_2_FN64_MIGRATE ARM_PSCI_0_2_FN64(5) |
| 66 | #define ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU ARM_PSCI_0_2_FN64(7) |
Rajesh Ravi | 41acbc5 | 2019-11-22 14:50:01 -0800 | [diff] [blame] | 67 | #define ARM_PSCI_0_2_FN64_SYSTEM_RESET2 ARM_PSCI_0_2_FN64(18) |
macro.wave.z@gmail.com | 14bf25d | 2016-12-08 11:58:24 +0800 | [diff] [blame] | 68 | |
Hongbo Zhang | 116339d | 2016-07-21 18:09:36 +0800 | [diff] [blame] | 69 | /* PSCI 1.0 interface */ |
| 70 | #define ARM_PSCI_1_0_FN_PSCI_FEATURES ARM_PSCI_0_2_FN(10) |
| 71 | #define ARM_PSCI_1_0_FN_CPU_FREEZE ARM_PSCI_0_2_FN(11) |
| 72 | #define ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND ARM_PSCI_0_2_FN(12) |
| 73 | #define ARM_PSCI_1_0_FN_NODE_HW_STATE ARM_PSCI_0_2_FN(13) |
| 74 | #define ARM_PSCI_1_0_FN_SYSTEM_SUSPEND ARM_PSCI_0_2_FN(14) |
| 75 | #define ARM_PSCI_1_0_FN_SET_SUSPEND_MODE ARM_PSCI_0_2_FN(15) |
| 76 | #define ARM_PSCI_1_0_FN_STAT_RESIDENCY ARM_PSCI_0_2_FN(16) |
| 77 | #define ARM_PSCI_1_0_FN_STAT_COUNT ARM_PSCI_0_2_FN(17) |
| 78 | |
macro.wave.z@gmail.com | 14bf25d | 2016-12-08 11:58:24 +0800 | [diff] [blame] | 79 | #define ARM_PSCI_1_0_FN64_CPU_DEFAULT_SUSPEND ARM_PSCI_0_2_FN64(12) |
| 80 | #define ARM_PSCI_1_0_FN64_NODE_HW_STATE ARM_PSCI_0_2_FN64(13) |
| 81 | #define ARM_PSCI_1_0_FN64_SYSTEM_SUSPEND ARM_PSCI_0_2_FN64(14) |
| 82 | #define ARM_PSCI_1_0_FN64_STAT_RESIDENCY ARM_PSCI_0_2_FN64(16) |
| 83 | #define ARM_PSCI_1_0_FN64_STAT_COUNT ARM_PSCI_0_2_FN64(17) |
| 84 | |
Chen-Yu Tsai | 980d6a5 | 2016-06-19 12:38:36 +0800 | [diff] [blame] | 85 | /* 1KB stack per core */ |
| 86 | #define ARM_PSCI_STACK_SHIFT 10 |
| 87 | #define ARM_PSCI_STACK_SIZE (1 << ARM_PSCI_STACK_SHIFT) |
| 88 | |
Hongbo Zhang | 7e742c2 | 2016-07-21 18:09:37 +0800 | [diff] [blame] | 89 | /* PSCI affinity level state returned by AFFINITY_INFO */ |
| 90 | #define PSCI_AFFINITY_LEVEL_ON 0 |
| 91 | #define PSCI_AFFINITY_LEVEL_OFF 1 |
| 92 | #define PSCI_AFFINITY_LEVEL_ON_PENDING 2 |
| 93 | |
Rajesh Ravi | 41acbc5 | 2019-11-22 14:50:01 -0800 | [diff] [blame] | 94 | #define PSCI_RESET2_TYPE_VENDOR_SHIFT 31 |
| 95 | #define PSCI_RESET2_TYPE_VENDOR BIT(PSCI_RESET2_TYPE_VENDOR_SHIFT) |
| 96 | |
Tom Rini | dd09f7e | 2015-03-05 20:19:36 -0500 | [diff] [blame] | 97 | #ifndef __ASSEMBLY__ |
Chen-Yu Tsai | cbeeb2a | 2016-06-07 10:54:26 +0800 | [diff] [blame] | 98 | #include <asm/types.h> |
| 99 | |
Patrick Delaunay | 9ce751a | 2018-04-16 10:15:12 +0200 | [diff] [blame] | 100 | /* These 3 helper functions assume cpu < CONFIG_ARMV7_PSCI_NR_CPUS */ |
Chen-Yu Tsai | 45c334e | 2016-07-05 21:45:07 +0800 | [diff] [blame] | 101 | u32 psci_get_target_pc(int cpu); |
Patrick Delaunay | 1a047c2 | 2018-04-16 10:13:22 +0200 | [diff] [blame] | 102 | u32 psci_get_context_id(int cpu); |
Patrick Delaunay | 1a047c2 | 2018-04-16 10:13:22 +0200 | [diff] [blame] | 103 | void psci_save(int cpu, u32 pc, u32 context_id); |
Chen-Yu Tsai | 45c334e | 2016-07-05 21:45:07 +0800 | [diff] [blame] | 104 | |
Chen-Yu Tsai | cbeeb2a | 2016-06-07 10:54:26 +0800 | [diff] [blame] | 105 | void psci_cpu_entry(void); |
| 106 | u32 psci_get_cpu_id(void); |
Chen-Yu Tsai | cbeeb2a | 2016-06-07 10:54:26 +0800 | [diff] [blame] | 107 | void psci_cpu_off_common(void); |
| 108 | |
Tom Rini | dd09f7e | 2015-03-05 20:19:36 -0500 | [diff] [blame] | 109 | int psci_update_dt(void *fdt); |
Jan Kiszka | ce416fa | 2015-04-21 07:18:34 +0200 | [diff] [blame] | 110 | void psci_board_init(void); |
Hou Zhiqiang | 45684ae | 2016-06-28 20:18:16 +0800 | [diff] [blame] | 111 | int fdt_psci(void *fdt); |
Hongbo Zhang | d38def1 | 2016-08-19 17:20:30 +0800 | [diff] [blame] | 112 | |
| 113 | void psci_v7_flush_dcache_all(void); |
Tom Rini | dd09f7e | 2015-03-05 20:19:36 -0500 | [diff] [blame] | 114 | #endif /* ! __ASSEMBLY__ */ |
| 115 | |
Marc Zyngier | ecf07a7 | 2014-07-12 14:24:04 +0100 | [diff] [blame] | 116 | #endif /* __ARM_PSCI_H__ */ |