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Andreas Bießmanna420dfe2012-09-04 11:33:29 +00001/*
2 * Copyright (C) 2006 Atmel Corporation
3 *
Andreas Bießmann09c2b8f2016-05-01 03:46:16 +02004 * Copyright (C) 2012 Andreas Bießmann <andreas@biessmann.org>
Andreas Bießmanna420dfe2012-09-04 11:33:29 +00005 *
6 * Configuration settings for the AVR32 Network Gateway
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Andreas Bießmanna420dfe2012-09-04 11:33:29 +00009 */
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#include <asm/arch/hardware.h>
14
Andreas Bießmanna420dfe2012-09-04 11:33:29 +000015#define CONFIG_AT32AP
16#define CONFIG_AT32AP7000
17#define CONFIG_ATNGW100MKII
18
Andreas Bießmanned78b112015-03-01 22:01:13 +010019#define CONFIG_BOARD_EARLY_INIT_R
20
Andreas Bießmanna420dfe2012-09-04 11:33:29 +000021/*
Andreas Bießmanna420dfe2012-09-04 11:33:29 +000022 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
23 * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
24 * and the PBA bus to run at 1/4 the PLL frequency.
25 */
26#define CONFIG_PLL
27#define CONFIG_SYS_POWER_MANAGER
28#define CONFIG_SYS_OSC0_HZ 20000000
29#define CONFIG_SYS_PLL0_DIV 1
30#define CONFIG_SYS_PLL0_MUL 7
31#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
32/*
33 * Set the CPU running at:
34 * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
35 */
36#define CONFIG_SYS_CLKDIV_CPU 0
37/*
38 * Set the HSB running at:
39 * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
40 */
41#define CONFIG_SYS_CLKDIV_HSB 1
42/*
43 * Set the PBA running at:
44 * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
45 */
46#define CONFIG_SYS_CLKDIV_PBA 2
47/*
48 * Set the PBB running at:
49 * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
50 */
51#define CONFIG_SYS_CLKDIV_PBB 1
52
53/* Reserve VM regions for NOR flash, NAND flash and SDRAM */
54#define CONFIG_SYS_NR_VM_REGIONS 3
55
56/*
57 * The PLLOPT register controls the PLL like this:
58 * icp = PLLOPT<2>
59 * ivco = PLLOPT<1:0>
60 *
61 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
62 */
63#define CONFIG_SYS_PLL0_OPT 0x04
64
65#define CONFIG_USART_BASE ATMEL_BASE_USART1
66#define CONFIG_USART_ID 1
67
68/* User serviceable stuff */
Andreas Bießmanna420dfe2012-09-04 11:33:29 +000069
70#define CONFIG_CMDLINE_TAG
71#define CONFIG_SETUP_MEMORY_TAGS
72#define CONFIG_INITRD_TAG
73
Andreas Bießmanna420dfe2012-09-04 11:33:29 +000074#define CONFIG_BOOTARGS \
75 "root=mtd:main rootfstype=jffs2"
76#define CONFIG_BOOTCOMMAND \
77 "fsload 0x10400000 /uImage; bootm"
78
Andreas Bießmanna420dfe2012-09-04 11:33:29 +000079
80/*
81 * After booting the board for the first time, new ethernet addresses
82 * should be generated and assigned to the environment variables
83 * "ethaddr" and "eth1addr". This is normally done during production.
84 */
85#define CONFIG_OVERWRITE_ETHADDR_ONCE
Andreas Bießmanna420dfe2012-09-04 11:33:29 +000086
87/*
88 * BOOTP/DHCP options
89 */
90#define CONFIG_BOOTP_SUBNETMASK
91#define CONFIG_BOOTP_GATEWAY
92
93/*
94 * Command line configuration.
95 */
Andreas Bießmanna420dfe2012-09-04 11:33:29 +000096
Andreas Bießmanna420dfe2012-09-04 11:33:29 +000097#define CONFIG_ATMEL_USART
98#define CONFIG_MACB
99#define CONFIG_PORTMUX_PIO
100#define CONFIG_SYS_NR_PIOS 5
101#define CONFIG_SYS_HSDRAMC
Andreas Bießmanna420dfe2012-09-04 11:33:29 +0000102#define CONFIG_GENERIC_ATMEL_MCI
Andreas Bießmanna420dfe2012-09-04 11:33:29 +0000103#define CONFIG_ATMEL_SPI
104
Andreas Bießmanna420dfe2012-09-04 11:33:29 +0000105#define CONFIG_SYS_DCACHE_LINESZ 32
106#define CONFIG_SYS_ICACHE_LINESZ 32
107
108#define CONFIG_NR_DRAM_BANKS 1
109
110#define CONFIG_SYS_FLASH_CFI
111#define CONFIG_FLASH_CFI_DRIVER
112#define CONFIG_SYS_FLASH_PROTECTION
113
114#define CONFIG_SYS_FLASH_BASE 0x00000000
115#define CONFIG_SYS_FLASH_SIZE 0x800000
116#define CONFIG_SYS_MAX_FLASH_BANKS 1
117#define CONFIG_SYS_MAX_FLASH_SECT 135
118
119#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
Andreas Bießmann024cd742014-05-16 12:17:41 +0200120#define CONFIG_SYS_TEXT_BASE 0x00000000
Andreas Bießmanna420dfe2012-09-04 11:33:29 +0000121
122#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
123#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
124#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
125
126#define CONFIG_ENV_IS_IN_FLASH
127#define CONFIG_ENV_SIZE 65536
128#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
129
130#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
131
132#define CONFIG_SYS_MALLOC_LEN (256*1024)
Andreas Bießmanna420dfe2012-09-04 11:33:29 +0000133
134/* Allow 4MB for the kernel run-time image */
135#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
136#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
137
138/* Other configuration settings that shouldn't have to change all that often */
Andreas Bießmanna420dfe2012-09-04 11:33:29 +0000139#define CONFIG_SYS_CBSIZE 256
140#define CONFIG_SYS_MAXARGS 16
141#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
142#define CONFIG_SYS_LONGHELP
143
144#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
145#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000)
146
147#define CONFIG_MTD_DEVICE
148#define CONFIG_MTD_PARTITIONS
149
150#endif /* __CONFIG_H */