Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / f1ee982506d8e58262ff0e5d1fb208e703640e34 / . / include / configs / CPU87.h
blob: a23d7e50b7bda3f2b64523ac223a08ec8a522291 [file] [log] [blame]
wdenk384cc682005-04-03 22:35:21 +0000[diff] [blame]1/*
2 * (C) Copyright 2001-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
37#define CONFIG_CPU87 1 /* ...on a CPU87 board */
38#define CONFIG_PCI
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500[diff] [blame]39#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenk384cc682005-04-03 22:35:21 +0000[diff] [blame]40
41/*
42 * select serial console configuration
43 *
44 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
45 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
46 * for SCC).
47 *
48 * if CONFIG_CONS_NONE is defined, then the serial console routines must
49 * defined elsewhere (for example, on the cogent platform, there are serial
50 * ports on the motherboard which are used for the serial console - see
51 * cogent/cma101/serial.[ch]).
52 */
53#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
54#define CONFIG_CONS_ON_SCC /* define if console on SCC */
55#undef CONFIG_CONS_NONE /* define if console on something else*/
56#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
57
58#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
59#define CONFIG_BAUDRATE 230400
60#else
61#define CONFIG_BAUDRATE 9600
62#endif
63
64/*
65 * select ethernet configuration
66 *
67 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
68 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
69 * for FCC)
70 *
71 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
72 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
73 * from CONFIG_COMMANDS to remove support for networking.
74 *
75 */
76#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
77#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
78#undef CONFIG_ETHER_NONE /* define if ether on something else */
79#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
80
81#define CONFIG_HAS_ETH1 1
82#define CONFIG_HAS_ETH2 1
83
84#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
85
86/*
87 * - Rx-CLK is CLK11
88 * - Tx-CLK is CLK12
89 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
90 * - Enable Full Duplex in FSMR
91 */
92# define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
93# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
94# define CFG_CPMFCR_RAMTYPE 0
95# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
96
97#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
98
99/*
100 * - Rx-CLK is CLK13
101 * - Tx-CLK is CLK14
102 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
103 * - Enable Full Duplex in FSMR
104 */
105# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
106# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
107# define CFG_CPMFCR_RAMTYPE 0
108# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
109
110#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
111
112/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
113#define CONFIG_8260_CLKIN 100000000 /* in Hz */
114
115#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
116
wdenk384cc682005-04-03 22:35:21 +0000[diff] [blame]117#define CONFIG_PREBOOT \
118 "echo; " \
119 "echo Type \"run flash_nfs\" to mount root filesystem over NFS; " \
120 "echo"
121
122#undef CONFIG_BOOTARGS
123#define CONFIG_BOOTCOMMAND \
124 "bootp; " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100[diff] [blame]125 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
126 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenk384cc682005-04-03 22:35:21 +0000[diff] [blame]127 "bootm"
128
129/*-----------------------------------------------------------------------
130 * I2C/EEPROM/RTC configuration
131 */
132#define CONFIG_SOFT_I2C /* Software I2C support enabled */
133
134# define CFG_I2C_SPEED 50000
135# define CFG_I2C_SLAVE 0xFE
136/*
137 * Software (bit-bang) I2C driver configuration
138 */
139#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
140#define I2C_ACTIVE (iop->pdir |= 0x00010000)
141#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
142#define I2C_READ ((iop->pdat & 0x00010000) != 0)
143#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
144 else iop->pdat &= ~0x00010000
145#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
146 else iop->pdat &= ~0x00020000
147#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
148
149#define CONFIG_RTC_PCF8563
150#define CFG_I2C_RTC_ADDR 0x51
151
152#undef CONFIG_WATCHDOG /* watchdog disabled */
153
154/*-----------------------------------------------------------------------
155 * Disk-On-Chip configuration
156 */
157
158#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
159
160#define CFG_DOC_SUPPORT_2000
161#define CFG_DOC_SUPPORT_MILLENNIUM
162
163/*-----------------------------------------------------------------------
164 * Miscellaneous configuration options
165 */
166
167#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
168#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
169
170#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
171
172#ifdef CONFIG_PCI
173#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
174 CFG_CMD_BEDBUG | \
175 CFG_CMD_DATE | \
176 CFG_CMD_DOC | \
177 CFG_CMD_EEPROM | \
178 CFG_CMD_I2C | \
179 CFG_CMD_PCI)
180#else /* ! PCI */
181#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
182 CFG_CMD_BEDBUG | \
183 CFG_CMD_DATE | \
184 CFG_CMD_DOC | \
185 CFG_CMD_EEPROM | \
186 CFG_CMD_I2C )
187#endif /* CONFIG_PCI */
188
189/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
190#include <cmd_confdefs.h>
191
192/*
193 * Miscellaneous configurable options
194 */
195#define CFG_LONGHELP /* undef to save memory */
196#define CFG_PROMPT "=> " /* Monitor Command Prompt */
197#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
198#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
199#else
200#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
201#endif
202#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
203#define CFG_MAXARGS 16 /* max number of command args */
204#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
205
206#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
207#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
208
209#define CFG_LOAD_ADDR 0x100000 /* default load address */
210
211#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
212
213#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
214
215#define CFG_RESET_ADDRESS 0xFFF00100 /* "bad" address */
216
217#define CONFIG_LOOPW
218
219/*
220 * For booting Linux, the board info and command line data
221 * have to be in the first 8 MB of memory, since this is
222 * the maximum mapped by the Linux kernel during initialization.
223 */
224#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
225
226/*-----------------------------------------------------------------------
227 * Flash configuration
228 */
229
230#define CFG_BOOTROM_BASE 0xFF800000
231#define CFG_BOOTROM_SIZE 0x00080000
232#define CFG_FLASH_BASE 0xFF000000
233#define CFG_FLASH_SIZE 0x00800000
234
235/*-----------------------------------------------------------------------
236 * FLASH organization
237 */
238#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
239#define CFG_MAX_FLASH_SECT 135 /* max num of sects on one chip */
240
241#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
242#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
243
244/*-----------------------------------------------------------------------
245 * Other areas to be mapped
246 */
247
248/* CS3: Dual ported SRAM */
249#define CFG_DPSRAM_BASE 0x40000000
250#define CFG_DPSRAM_SIZE 0x00100000
251
252/* CS4: DiskOnChip */
253#define CFG_DOC_BASE 0xF4000000
254#define CFG_DOC_SIZE 0x00100000
255
256/* CS5: FDC37C78 controller */
257#define CFG_FDC37C78_BASE 0xF1000000
258#define CFG_FDC37C78_SIZE 0x00100000
259
260/* CS6: Board configuration registers */
261#define CFG_BCRS_BASE 0xF2000000
262#define CFG_BCRS_SIZE 0x00010000
263
264/* CS7: VME Extended Access Range */
265#define CFG_VMEEAR_BASE 0x60000000
266#define CFG_VMEEAR_SIZE 0x01000000
267
268/* CS8: VME Standard Access Range */
269#define CFG_VMESAR_BASE 0xFE000000
270#define CFG_VMESAR_SIZE 0x01000000
271
272/* CS9: VME Short I/O Access Range */
273#define CFG_VMESIOAR_BASE 0xFD000000
274#define CFG_VMESIOAR_SIZE 0x01000000
275
276/*-----------------------------------------------------------------------
277 * Hard Reset Configuration Words
278 *
279 * if you change bits in the HRCW, you must also change the CFG_*
280 * defines for the various registers affected by the HRCW e.g. changing
281 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
282 */
283#if defined(CONFIG_BOOT_ROM)
284#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
285 HRCW_BPS01 | HRCW_CS10PC01)
286#else
287#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
288#endif
289
290/* no slaves so just fill with zeros */
291#define CFG_HRCW_SLAVE1 0
292#define CFG_HRCW_SLAVE2 0
293#define CFG_HRCW_SLAVE3 0
294#define CFG_HRCW_SLAVE4 0
295#define CFG_HRCW_SLAVE5 0
296#define CFG_HRCW_SLAVE6 0
297#define CFG_HRCW_SLAVE7 0
298
299/*-----------------------------------------------------------------------
300 * Internal Memory Mapped Register
301 */
302#define CFG_IMMR 0xF0000000
303
304/*-----------------------------------------------------------------------
305 * Definitions for initial stack pointer and data area (in DPRAM)
306 */
307#define CFG_INIT_RAM_ADDR CFG_IMMR
308#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
309#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
310#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
311#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
312
313/*-----------------------------------------------------------------------
314 * Start addresses for the final memory configuration
315 * (Set up by the startup code)
316 * Please note that CFG_SDRAM_BASE _must_ start at 0
317 *
318 * 60x SDRAM is mapped at CFG_SDRAM_BASE.
319 */
320#define CFG_SDRAM_BASE 0x00000000
321#define CFG_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
322#define CFG_MONITOR_BASE TEXT_BASE
323#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
324#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
325
326#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
327# define CFG_RAMBOOT
328#endif
329
330#ifdef CONFIG_PCI
331#define CONFIG_PCI_PNP
332#define CONFIG_EEPRO100
333#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
334#endif
335
336#if 0
337/* environment is in Flash */
338#define CFG_ENV_IS_IN_FLASH 1
339#ifdef CONFIG_BOOT_ROM
340# define CFG_ENV_ADDR (CFG_FLASH_BASE+0x70000)
341# define CFG_ENV_SIZE 0x10000
342# define CFG_ENV_SECT_SIZE 0x10000
343#endif
344#else
345/* environment is in EEPROM */
346#define CFG_ENV_IS_IN_EEPROM 1
347#define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM X24C16 */
348#define CFG_I2C_EEPROM_ADDR_LEN 1
349/* mask of address bits that overflow into the "EEPROM chip address" */
350#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
351#define CFG_EEPROM_PAGE_WRITE_BITS 4
352#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
353#define CFG_ENV_OFFSET 512
354#define CFG_ENV_SIZE (2048 - 512)
355#endif
356
357/*
358 * Internal Definitions
359 *
360 * Boot Flags
361 */
362#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
363#define BOOTFLAG_WARM 0x02 /* Software reboot */
364
365
366/*-----------------------------------------------------------------------
367 * Cache Configuration
368 */
369#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
370#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
371# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
372#endif
373
374/*-----------------------------------------------------------------------
375 * HIDx - Hardware Implementation-dependent Registers 2-11
376 *-----------------------------------------------------------------------
377 * HID0 also contains cache control - initially enable both caches and
378 * invalidate contents, then the final state leaves only the instruction
379 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
380 * but Soft reset does not.
381 *
382 * HID1 has only read-only information - nothing to set.
383 */
384#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\
385 HID0_DCI|HID0_IFEM|HID0_ABE)
386#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE)
387#define CFG_HID2 0
388
389/*-----------------------------------------------------------------------
390 * RMR - Reset Mode Register 5-5
391 *-----------------------------------------------------------------------
392 * turn on Checkstop Reset Enable
393 */
394#define CFG_RMR RMR_CSRE
395
396/*-----------------------------------------------------------------------
397 * BCR - Bus Configuration 4-25
398 *-----------------------------------------------------------------------
399 */
400#define BCR_APD01 0x10000000
401#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
402
403/*-----------------------------------------------------------------------
404 * SIUMCR - SIU Module Configuration 4-31
405 *-----------------------------------------------------------------------
406 */
407#define CFG_SIUMCR (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
408 SIUMCR_CS10PC01|SIUMCR_BCTLC10)
409
410/*-----------------------------------------------------------------------
411 * SYPCR - System Protection Control 4-35
412 * SYPCR can only be written once after reset!
413 *-----------------------------------------------------------------------
414 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
415 */
416#if defined(CONFIG_WATCHDOG)
417#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
418 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
419#else
420#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
421 SYPCR_SWRI|SYPCR_SWP)
422#endif /* CONFIG_WATCHDOG */
423
424/*-----------------------------------------------------------------------
425 * TMCNTSC - Time Counter Status and Control 4-40
426 *-----------------------------------------------------------------------
427 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
428 * and enable Time Counter
429 */
430#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
431
432/*-----------------------------------------------------------------------
433 * PISCR - Periodic Interrupt Status and Control 4-42
434 *-----------------------------------------------------------------------
435 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
436 * Periodic timer
437 */
438#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
439
440/*-----------------------------------------------------------------------
441 * SCCR - System Clock Control 9-8
442 *-----------------------------------------------------------------------
443 * Ensure DFBRG is Divide by 16
444 */
445#define CFG_SCCR SCCR_DFBRG01
446
447/*-----------------------------------------------------------------------
448 * RCCR - RISC Controller Configuration 13-7
449 *-----------------------------------------------------------------------
450 */
451#define CFG_RCCR 0
452
453#define CFG_MIN_AM_MASK 0xC0000000
454
455/*
456 * we use the same values for 32 MB and 128 MB SDRAM
457 * refresh rate = 7.68 uS (100 MHz Bus Clock)
458 */
459
460/*-----------------------------------------------------------------------
461 * MPTPR - Memory Refresh Timer Prescaler Register 10-18
462 *-----------------------------------------------------------------------
463 */
464#define CFG_MPTPR 0x2000
465
466/*-----------------------------------------------------------------------
467 * PSRT - Refresh Timer Register 10-16
468 *-----------------------------------------------------------------------
469 */
470#define CFG_PSRT 0x16
471
472/*-----------------------------------------------------------------------
473 * PSRT - SDRAM Mode Register 10-10
474 *-----------------------------------------------------------------------
475 */
476
477 /* SDRAM initialization values for 8-column chips
478 */
479#define CFG_OR2_8COL (CFG_MIN_AM_MASK |\
480 ORxS_BPD_4 |\
481 ORxS_ROWST_PBI0_A9 |\
482 ORxS_NUMR_12)
483
484#define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\
485 PSDMR_BSMA_A14_A16 |\
486 PSDMR_SDA10_PBI0_A10 |\
487 PSDMR_RFRC_7_CLK |\
488 PSDMR_PRETOACT_2W |\
489 PSDMR_ACTTORW_2W |\
490 PSDMR_LDOTOPRE_1C |\
491 PSDMR_WRC_1C |\
492 PSDMR_CL_2)
493
494 /* SDRAM initialization values for 9-column chips
495 */
496#define CFG_OR2_9COL (CFG_MIN_AM_MASK |\
497 ORxS_BPD_4 |\
498 ORxS_ROWST_PBI0_A7 |\
499 ORxS_NUMR_13)
500
501#define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\
502 PSDMR_BSMA_A13_A15 |\
503 PSDMR_SDA10_PBI0_A9 |\
504 PSDMR_RFRC_7_CLK |\
505 PSDMR_PRETOACT_2W |\
506 PSDMR_ACTTORW_2W |\
507 PSDMR_LDOTOPRE_1C |\
508 PSDMR_WRC_1C |\
509 PSDMR_CL_2)
510
511/*
512 * Init Memory Controller:
513 *
514 * Bank Bus Machine PortSz Device
515 * ---- --- ------- ------ ------
516 * 0 60x GPCM 8 bit Boot ROM
517 * 1 60x GPCM 64 bit FLASH
518 * 2 60x SDRAM 64 bit SDRAM
519 *
520 */
521
522#define CFG_MRS_OFFS 0x00000000
523
524#ifdef CONFIG_BOOT_ROM
525/* Bank 0 - Boot ROM
526 */
527#define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
528 BRx_PS_8 |\
529 BRx_MS_GPCM_P |\
530 BRx_V)
531
532#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\
533 ORxG_CSNT |\
534 ORxG_ACS_DIV1 |\
535 ORxG_SCY_5_CLK |\
536 ORxU_EHTR_8IDLE)
537
538/* Bank 1 - FLASH
539 */
540#define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
541 BRx_PS_64 |\
542 BRx_MS_GPCM_P |\
543 BRx_V)
544
545#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
546 ORxG_CSNT |\
547 ORxG_ACS_DIV1 |\
548 ORxG_SCY_5_CLK |\
549 ORxU_EHTR_8IDLE)
550
551#else /* CONFIG_BOOT_ROM */
552/* Bank 0 - FLASH
553 */
554#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
555 BRx_PS_64 |\
556 BRx_MS_GPCM_P |\
557 BRx_V)
558
559#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
560 ORxG_CSNT |\
561 ORxG_ACS_DIV1 |\
562 ORxG_SCY_5_CLK |\
563 ORxU_EHTR_8IDLE)
564
565/* Bank 1 - Boot ROM
566 */
567#define CFG_BR1_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
568 BRx_PS_8 |\
569 BRx_MS_GPCM_P |\
570 BRx_V)
571
572#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\
573 ORxG_CSNT |\
574 ORxG_ACS_DIV1 |\
575 ORxG_SCY_5_CLK |\
576 ORxU_EHTR_8IDLE)
577
578#endif /* CONFIG_BOOT_ROM */
579
580
581/* Bank 2 - 60x bus SDRAM
582 */
583#ifndef CFG_RAMBOOT
584#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
585 BRx_PS_64 |\
586 BRx_MS_SDRAM_P |\
587 BRx_V)
588
589#define CFG_OR2_PRELIM CFG_OR2_9COL
590
591#define CFG_PSDMR CFG_PSDMR_9COL
592#endif /* CFG_RAMBOOT */
593
594/* Bank 3 - Dual Ported SRAM
595 */
596#define CFG_BR3_PRELIM ((CFG_DPSRAM_BASE & BRx_BA_MSK) |\
597 BRx_PS_16 |\
598 BRx_MS_GPCM_P |\
599 BRx_V)
600
601#define CFG_OR3_PRELIM (P2SZ_TO_AM(CFG_DPSRAM_SIZE) |\
602 ORxG_CSNT |\
603 ORxG_ACS_DIV1 |\
604 ORxG_SCY_7_CLK |\
605 ORxG_SETA)
606
607/* Bank 4 - DiskOnChip
608 */
609#define CFG_BR4_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) |\
610 BRx_PS_8 |\
611 BRx_MS_GPCM_P |\
612 BRx_V)
613
614#define CFG_OR4_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) |\
615 ORxG_CSNT |\
616 ORxG_ACS_DIV2 |\
617 ORxG_SCY_9_CLK |\
618 ORxU_EHTR_8IDLE)
619
620/* Bank 5 - FDC37C78 controller
621 */
622#define CFG_BR5_PRELIM ((CFG_FDC37C78_BASE & BRx_BA_MSK) |\
623 BRx_PS_8 |\
624 BRx_MS_GPCM_P |\
625 BRx_V)
626
627#define CFG_OR5_PRELIM (P2SZ_TO_AM(CFG_FDC37C78_SIZE) |\
628 ORxG_ACS_DIV2 |\
629 ORxG_SCY_10_CLK |\
630 ORxU_EHTR_8IDLE)
631
632/* Bank 6 - Board control registers
633 */
634#define CFG_BR6_PRELIM ((CFG_BCRS_BASE & BRx_BA_MSK) |\
635 BRx_PS_8 |\
636 BRx_MS_GPCM_P |\
637 BRx_V)
638
639#define CFG_OR6_PRELIM (P2SZ_TO_AM(CFG_BCRS_SIZE) |\
640 ORxG_CSNT |\
641 ORxG_SCY_7_CLK)
642
643/* Bank 7 - VME Extended Access Range
644 */
645#define CFG_BR7_PRELIM ((CFG_VMEEAR_BASE & BRx_BA_MSK) |\
646 BRx_PS_32 |\
647 BRx_MS_GPCM_P |\
648 BRx_V)
649
650#define CFG_OR7_PRELIM (P2SZ_TO_AM(CFG_VMEEAR_SIZE) |\
651 ORxG_CSNT |\
652 ORxG_ACS_DIV1 |\
653 ORxG_SCY_7_CLK |\
654 ORxG_SETA)
655
656/* Bank 8 - VME Standard Access Range
657 */
658#define CFG_BR8_PRELIM ((CFG_VMESAR_BASE & BRx_BA_MSK) |\
659 BRx_PS_16 |\
660 BRx_MS_GPCM_P |\
661 BRx_V)
662
663#define CFG_OR8_PRELIM (P2SZ_TO_AM(CFG_VMESAR_SIZE) |\
664 ORxG_CSNT |\
665 ORxG_ACS_DIV1 |\
666 ORxG_SCY_7_CLK |\
667 ORxG_SETA)
668
669/* Bank 9 - VME Short I/O Access Range
670 */
671#define CFG_BR9_PRELIM ((CFG_VMESIOAR_BASE & BRx_BA_MSK) |\
672 BRx_PS_16 |\
673 BRx_MS_GPCM_P |\
674 BRx_V)
675
676#define CFG_OR9_PRELIM (P2SZ_TO_AM(CFG_VMESIOAR_SIZE) |\
677 ORxG_CSNT |\
678 ORxG_ACS_DIV1 |\
679 ORxG_SCY_7_CLK |\
680 ORxG_SETA)
681
682#endif /* __CONFIG_H */