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wdenkcc1c8a12002-11-02 22:58:18 +00001/*
2 * U-Boot configuration for SIXNET SXNI855T CPU board.
3 * This board is based (loosely) on the Motorola FADS board, so this
4 * file is based (loosely) on config_FADS860T.h, see it for additional
5 * credits.
6 *
7 * Copyright (c) 2000-2002 Dave Ellis, SIXNET, dge@sixnetio.com
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 *
27 */
28
29/*
30 * Memory map:
31 *
32 * ff100000 -> ff13ffff : FPGA CS1
33 * ff030000 -> ff03ffff : EXPANSION CS7
34 * ff020000 -> ff02ffff : DATA FLASH CS4
35 * ff018000 -> ff01ffff : UART B CS6/UPMB
36 * ff010000 -> ff017fff : UART A CS5/UPMB
37 * ff000000 -> ff00ffff : IMAP internal to the MPC855T
38 * f8000000 -> fbffffff : FLASH CS0 up to 64MB
39 * f4000000 -> f7ffffff : NVSRAM CS2 up to 64MB
40 * 00000000 -> 0fffffff : SDRAM CS3/UPMA up to 256MB
41 */
42
43/* ------------------------------------------------------------------------- */
44
45/*
46 * board/config.h - configuration options, board specific
47 */
48
49#ifndef __CONFIG_H
50#define __CONFIG_H
51
52/*
53 * High Level Configuration Options
54 * (easy to change)
55 */
56#include <mpc8xx_irq.h>
57
58#define CONFIG_SXNI855T 1 /* SIXNET IPm 855T CPU module */
59
60/* The 855T is just a stripped 860T and needs code for 860, so for now
61 * at least define 860, 860T and 855T
62 */
63#define CONFIG_MPC860 1
64#define CONFIG_MPC860T 1
65#define CONFIG_MPC855T 1
66
67#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
68#undef CONFIG_8xx_CONS_SMC2
69#undef CONFIG_8xx_CONS_SCC1
70#undef CONFIG_8xx_CONS_NONE
71#define CONFIG_BAUDRATE 9600
72#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
73
74#define MPC8XX_FACT 10 /* 50 MHz is 5 MHz in times 10 */
75
76#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
77
78#if 0
79#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
80#else
81#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
82#endif
83
wdenke2ffd592004-12-31 09:32:47 +000084#define CONFIG_HAS_ETH1
85
wdenk506f0442003-03-28 14:40:36 +000086/*-----------------------------------------------------------------------
87 * Definitions for status LED
88 */
89#define CONFIG_STATUS_LED 1 /* Status LED enabled */
90
91# define STATUS_LED_PAR im_ioport.iop_papar
92# define STATUS_LED_DIR im_ioport.iop_padir
93# define STATUS_LED_ODR im_ioport.iop_paodr
94# define STATUS_LED_DAT im_ioport.iop_padat
95
96# define STATUS_LED_BIT 0x8000 /* LED 0 is on PA.0 */
97# define STATUS_LED_PERIOD ((CFG_HZ / 2) / 5) /* blink at 5 Hz */
98# define STATUS_LED_STATE STATUS_LED_BLINKING
99
100# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
101
102# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
103
104#ifdef DEV /* development (debug) settings */
105#define CONFIG_BOOT_LED_STATE STATUS_LED_OFF
106#else /* production settings */
107#define CONFIG_BOOT_LED_STATE STATUS_LED_ON
108#endif
109
110#define CONFIG_SHOW_BOOT_PROGRESS 1
111
wdenkcc1c8a12002-11-02 22:58:18 +0000112#define CONFIG_BOOTCOMMAND "bootm f8040000 f8100000" /* autoboot command */
113#define CONFIG_BOOTARGS "root=/dev/ram ip=off"
114
115#define CONFIG_MISC_INIT_R /* have misc_init_r() function */
116#define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */
117
118#undef CONFIG_WATCHDOG /* watchdog disabled */
119
120#define CONFIG_RTC_DS1306 /* Dallas 1306 real time clock */
121
122#define CONFIG_SOFT_I2C /* I2C bit-banged */
123/*
124 * Software (bit-bang) I2C driver configuration
125 */
126#define PB_SCL 0x00000020 /* PB 26 */
127#define PB_SDA 0x00000010 /* PB 27 */
128
129#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
130#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
131#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
132#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
133#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
134 else immr->im_cpm.cp_pbdat &= ~PB_SDA
135#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
136 else immr->im_cpm.cp_pbdat &= ~PB_SCL
137#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
138
139# define CFG_I2C_SPEED 50000
140# define CFG_I2C_SLAVE 0xFE
141# define CFG_I2C_EEPROM_ADDR 0x50 /* Atmel 24C64 */
142# define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
143
144#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200145#define CONFIG_MII 1
wdenkcc1c8a12002-11-02 22:58:18 +0000146
147#define CFG_DISCOVER_PHY
148
wdenk7a8e9bed2003-05-31 18:35:21 +0000149#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
150 CFG_CMD_EEPROM | \
wdenk7205e402003-09-10 22:30:53 +0000151 CFG_CMD_JFFS2 | \
wdenk7a8e9bed2003-05-31 18:35:21 +0000152 CFG_CMD_NAND | \
153 CFG_CMD_DATE)
wdenkcc1c8a12002-11-02 22:58:18 +0000154
155/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
156#include <cmd_confdefs.h>
157
wdenk7205e402003-09-10 22:30:53 +0000158#define CFG_JFFS2_SORT_FRAGMENTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200159
160/*
161 * JFFS2 partitions
162 *
163 */
164/* No command line, one static partition */
165#undef CONFIG_JFFS2_CMDLINE
166
167/*
168#define CONFIG_JFFS2_DEV "nor0"
169#define CONFIG_JFFS2_PART_SIZE 0x00780000
170#define CONFIG_JFFS2_PART_OFFSET 0x00080000
171*/
172
173#define CONFIG_JFFS2_DEV "nand0"
174#define CONFIG_JFFS2_PART_SIZE 0x00200000
175#define CONFIG_JFFS2_PART_OFFSET 0x00000000
176
177/* mtdparts command line support */
178/* Note: fake mtd_id used, no linux mtd map file */
179/*
180#define CONFIG_JFFS2_CMDLINE
181#define MTDIDS_DEFAULT "nor0=sixnet-0,nand0=sixnet-nand"
182#define MTDPARTS_DEFAULT "mtdparts=sixnet-0:7680k@512k();sixnet-nand:2m(jffs2-nand)"
183*/
wdenk7205e402003-09-10 22:30:53 +0000184
wdenk7a8e9bed2003-05-31 18:35:21 +0000185/* NAND flash support */
186#define CONFIG_MTD_NAND_ECC_JFFS2
187#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
188#define SECTORSIZE 512
189
190#define ADDR_COLUMN 1
191#define ADDR_PAGE 2
192#define ADDR_COLUMN_PAGE 3
193
194#define NAND_ChipID_UNKNOWN 0x00
195#define NAND_MAX_FLOORS 1
196#define NAND_MAX_CHIPS 1
197
198/* DFBUSY is available on Port C, bit 12; 0 if busy */
199#define NAND_WAIT_READY(nand) \
200 while (!(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & 0x0008));
201#define WRITE_NAND_COMMAND(d, adr) WRITE_NAND((d), (adr))
202#define WRITE_NAND_ADDRESS(d, adr) WRITE_NAND((d), (adr))
203#define WRITE_NAND(d, adr) \
204 do { (*(volatile uint8_t *)(adr) = (uint8_t)(d)); } while (0)
205#define READ_NAND(adr) (*(volatile uint8_t *)(adr))
206#define CLE_LO 0x01 /* 0 selects CLE mode (CLE high) */
207#define ALE_LO 0x02 /* 0 selects ALE mode (ALE high) */
208#define CE_LO 0x04 /* 1 selects chip (CE low) */
209#define nand_setcr(cr, val) do {*(volatile uint8_t*)(cr) = (val);} while (0)
210#define NAND_DISABLE_CE(nand) \
211 nand_setcr((nand)->IO_ADDR + 1, ALE_LO | CLE_LO)
212#define NAND_ENABLE_CE(nand) \
213 nand_setcr((nand)->IO_ADDR + 1, CE_LO | ALE_LO | CLE_LO)
214#define NAND_CTL_CLRALE(nandptr) \
215 nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO)
216#define NAND_CTL_SETALE(nandptr) \
217 nand_setcr((nandptr) + 1, CE_LO | CLE_LO)
218#define NAND_CTL_CLRCLE(nandptr) \
219 nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO)
220#define NAND_CTL_SETCLE(nandptr) \
221 nand_setcr((nandptr) + 1, CE_LO | ALE_LO)
222
wdenkcc1c8a12002-11-02 22:58:18 +0000223/*
224 * Miscellaneous configurable options
225 */
226#define CFG_LONGHELP /* undef to save a little memory */
227#define CFG_PROMPT "=>" /* Monitor Command Prompt */
228#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
229#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
230#else
231#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
232#endif
233#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
234#define CFG_MAXARGS 16 /* max number of command args */
235#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
236
237#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
238#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
239
240#define CFG_LOAD_ADDR 0x00100000
241
242#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
243
244#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
245
246/*
247 * Low Level Configuration Settings
248 * (address mappings, register initial values, etc.)
249 * You should know what you are doing if you make changes here.
250 */
251/*-----------------------------------------------------------------------
252 * Internal Memory Mapped Register
253 */
254#define CFG_IMMR 0xFF000000
255#define CFG_IMMR_SIZE ((uint)(64 * 1024))
256
257/*-----------------------------------------------------------------------
258 * Definitions for initial stack pointer and data area (in DPRAM)
259 */
260#define CFG_INIT_RAM_ADDR CFG_IMMR
261#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
262#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
263#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
264#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
265
266/*-----------------------------------------------------------------------
267 * Start addresses for the final memory configuration
268 * (Set up by the startup code)
269 * Please note that CFG_SDRAM_BASE _must_ start at 0
270 */
271#define CFG_SDRAM_BASE 0x00000000
272#define CFG_SRAM_BASE 0xF4000000
273#define CFG_SRAM_SIZE 0x04000000 /* autosize up to 64Mbyte */
274
275#define CFG_FLASH_BASE 0xF8000000
276#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
277
278#define CFG_DFLASH_BASE 0xff020000 /* DiskOnChip or NAND FLASH */
279#define CFG_DFLASH_SIZE 0x00010000
280
281#define CFG_FPGA_BASE 0xFF100000 /* Xilinx FPGA */
282#define CFG_FPGA_PROG 0xFF130000 /* Programming address */
283#define CFG_FPGA_SIZE 0x00040000 /* 256KiB usable */
284
285#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
286#define CFG_MONITOR_BASE CFG_FLASH_BASE
287#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
288
289/*
290 * For booting Linux, the board info and command line data
291 * have to be in the first 8 MB of memory, since this is
292 * the maximum mapped by the Linux kernel during initialization.
293 */
294#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
295/*-----------------------------------------------------------------------
296 * FLASH organization
297 */
298#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
299/* Intel 28F640 has 135, 127 64K sectors in 8MB, + 8 more for 8K boot blocks.
300 * AMD 29LV641 has 128 64K sectors in 8MB
301 */
302#define CFG_MAX_FLASH_SECT 135 /* max number of sectors on one chip */
303
304#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
305#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
306
307/*-----------------------------------------------------------------------
308 * Cache Configuration
309 */
310#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
311#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
312#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
313#endif
314
315/*-----------------------------------------------------------------------
316 * SYPCR - System Protection Control 11-9
317 * SYPCR can only be written once after reset!
318 *-----------------------------------------------------------------------
319 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
320 */
321#if defined(CONFIG_WATCHDOG)
322#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
323 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
324#else
325#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
326#endif
327
328/*-----------------------------------------------------------------------
329 * SIUMCR - SIU Module Configuration 11-6
330 *-----------------------------------------------------------------------
331 * PCMCIA config., multi-function pin tri-state
332 */
333#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
334
335/*-----------------------------------------------------------------------
336 * TBSCR - Time Base Status and Control 11-26
337 *-----------------------------------------------------------------------
338 * Clear Reference Interrupt Status, Timebase freezing enabled
339 */
340#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
341
342/*-----------------------------------------------------------------------
343 * PISCR - Periodic Interrupt Status and Control 11-31
344 *-----------------------------------------------------------------------
345 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
346 */
347#define CFG_PISCR (PISCR_PS | PISCR_PITF)
348
349/*-----------------------------------------------------------------------
350 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
351 *-----------------------------------------------------------------------
352 * set the PLL, the low-power modes and the reset control (15-29)
353 */
354#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
355 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
356
357/*-----------------------------------------------------------------------
358 * SCCR - System Clock and reset Control Register 15-27
359 *-----------------------------------------------------------------------
360 * Set clock output, timebase and RTC source and divider,
361 * power management and some other internal clocks
362 */
363#define SCCR_MASK SCCR_EBDF11
364#define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
365
366 /*-----------------------------------------------------------------------
367 *
368 *-----------------------------------------------------------------------
369 *
370 */
371#define CFG_DER 0
372
373/* Because of the way the 860 starts up and assigns CS0 the
374 * entire address space, we have to set the memory controller
375 * differently. Normally, you write the option register
376 * first, and then enable the chip select by writing the
377 * base register. For CS0, you must write the base register
378 * first, followed by the option register.
379 */
380
381/*
382 * Init Memory Controller:
383 *
384 **********************************************************
385 * BR0 and OR0 (FLASH)
386 */
387
388#define CFG_PRELIM_OR0_AM 0xFC000000 /* OR addr mask */
389
390/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
391#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
392
393#define CFG_OR0_PRELIM (CFG_PRELIM_OR0_AM | CFG_OR_TIMING_FLASH)
394
395#define CONFIG_FLASH_16BIT
396#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V )
397#define CFG_FLASH_PROTECTION /* need to lock/unlock sectors in hardware */
398
399/**********************************************************
400 * BR1 and OR1 (FPGA)
401 * These preliminary values are also the final values.
402 */
403#define CFG_OR_TIMING_FPGA \
wdenk7a8e9bed2003-05-31 18:35:21 +0000404 (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_4_CLK | OR_EHTR | OR_TRLX)
wdenkcc1c8a12002-11-02 22:58:18 +0000405#define CFG_BR1_PRELIM ((CFG_FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
406#define CFG_OR1_PRELIM (((-CFG_FPGA_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_FPGA)
407
408/**********************************************************
409 * BR4 and OR4 (data flash)
410 * These preliminary values are also the final values.
411 */
412#define CFG_OR_TIMING_DFLASH \
wdenk7a8e9bed2003-05-31 18:35:21 +0000413 (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK | OR_EHTR | OR_TRLX)
wdenkcc1c8a12002-11-02 22:58:18 +0000414#define CFG_BR4_PRELIM ((CFG_DFLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
415#define CFG_OR4_PRELIM (((-CFG_DFLASH_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_DFLASH)
416
417/**********************************************************
418 * BR5/6 and OR5/6 (Dual UART)
419 */
420#define CFG_DUART_SIZE 0x8000 /* 32K window, only uses 8 bytes */
421#define CFG_DUARTA_BASE 0xff010000
422#define CFG_DUARTB_BASE 0xff018000
423
424#define DUART_MBMR 0
425#define DUART_OR_VALUE (ORMASK(CFG_DUART_SIZE) | OR_G5LS| OR_BI)
426#define DUART_BR_VALUE (BR_MS_UPMB | BR_PS_8 | BR_V)
427#define DUART_BR5_VALUE ((CFG_DUARTA_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
428#define DUART_BR6_VALUE ((CFG_DUARTB_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
429
430/**********************************************************
431 *
432 * Boot Flags
433 */
434#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
435#define BOOTFLAG_WARM 0x02 /* Software reboot */
436
437#define CONFIG_RESET_ON_PANIC /* reset if system panic() */
438
wdenk7205e402003-09-10 22:30:53 +0000439#define CFG_ENV_IS_IN_FLASH
440#ifdef CFG_ENV_IS_IN_FLASH
441 /* environment is in FLASH */
442 #define CFG_ENV_ADDR 0xF8040000 /* AM29LV641 or AM29LV800BT */
443 #define CFG_ENV_ADDR_REDUND 0xF8050000 /* AM29LV641 or AM29LV800BT */
444 #define CFG_ENV_SECT_SIZE 0x00010000
445 #define CFG_ENV_SIZE 0x00002000
446#else
447 /* environment is in EEPROM */
448 #define CFG_ENV_IS_IN_EEPROM 1
449 #define CFG_ENV_OFFSET 0 /* at beginning of EEPROM */
450 #define CFG_ENV_SIZE 1024 /* Use only a part of it*/
wdenkcc1c8a12002-11-02 22:58:18 +0000451#endif
452
453#if 1
454#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
455#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
456#define CONFIG_AUTOBOOT_DELAY_STR "delayabit"
457#define CONFIG_AUTOBOOT_STOP_STR " " /* easy to stop for now */
458#endif
459
460#endif /* __CONFIG_H */