blob: 403eb64895e69ce23fd25a9711f767a6f56de546 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Marek Vasute40095f2016-05-24 23:29:09 +02002/*
3 * Atheros AR71xx / AR9xxx GMAC driver
4 *
5 * Copyright (C) 2016 Marek Vasut <marex@denx.de>
Marek Vasute40095f2016-05-24 23:29:09 +02006 */
7
8#include <common.h>
9#include <dm.h>
10#include <errno.h>
11#include <miiphy.h>
12#include <malloc.h>
13#include <linux/compiler.h>
14#include <linux/err.h>
15#include <linux/mii.h>
16#include <wait_bit.h>
17#include <asm/io.h>
18
19#include <mach/ath79.h>
20
21DECLARE_GLOBAL_DATA_PTR;
22
23enum ag7xxx_model {
24 AG7XXX_MODEL_AG933X,
25 AG7XXX_MODEL_AG934X,
Rosy Songf1f943e2019-02-05 17:50:44 +080026 AG7XXX_MODEL_AG953X
Marek Vasute40095f2016-05-24 23:29:09 +020027};
28
Joe Hershberger9240a2f2017-06-26 14:40:08 -050029/* MAC Configuration 1 */
Marek Vasute40095f2016-05-24 23:29:09 +020030#define AG7XXX_ETH_CFG1 0x00
31#define AG7XXX_ETH_CFG1_SOFT_RST BIT(31)
32#define AG7XXX_ETH_CFG1_RX_RST BIT(19)
33#define AG7XXX_ETH_CFG1_TX_RST BIT(18)
34#define AG7XXX_ETH_CFG1_LOOPBACK BIT(8)
35#define AG7XXX_ETH_CFG1_RX_EN BIT(2)
36#define AG7XXX_ETH_CFG1_TX_EN BIT(0)
37
Joe Hershberger9240a2f2017-06-26 14:40:08 -050038/* MAC Configuration 2 */
Marek Vasute40095f2016-05-24 23:29:09 +020039#define AG7XXX_ETH_CFG2 0x04
40#define AG7XXX_ETH_CFG2_IF_1000 BIT(9)
41#define AG7XXX_ETH_CFG2_IF_10_100 BIT(8)
42#define AG7XXX_ETH_CFG2_IF_SPEED_MASK (3 << 8)
43#define AG7XXX_ETH_CFG2_HUGE_FRAME_EN BIT(5)
44#define AG7XXX_ETH_CFG2_LEN_CHECK BIT(4)
45#define AG7XXX_ETH_CFG2_PAD_CRC_EN BIT(2)
46#define AG7XXX_ETH_CFG2_FDX BIT(0)
47
Joe Hershberger9240a2f2017-06-26 14:40:08 -050048/* MII Configuration */
Marek Vasute40095f2016-05-24 23:29:09 +020049#define AG7XXX_ETH_MII_MGMT_CFG 0x20
50#define AG7XXX_ETH_MII_MGMT_CFG_RESET BIT(31)
51
Joe Hershberger9240a2f2017-06-26 14:40:08 -050052/* MII Command */
Marek Vasute40095f2016-05-24 23:29:09 +020053#define AG7XXX_ETH_MII_MGMT_CMD 0x24
54#define AG7XXX_ETH_MII_MGMT_CMD_READ 0x1
55
Joe Hershberger9240a2f2017-06-26 14:40:08 -050056/* MII Address */
Marek Vasute40095f2016-05-24 23:29:09 +020057#define AG7XXX_ETH_MII_MGMT_ADDRESS 0x28
58#define AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT 8
59
Joe Hershberger9240a2f2017-06-26 14:40:08 -050060/* MII Control */
Marek Vasute40095f2016-05-24 23:29:09 +020061#define AG7XXX_ETH_MII_MGMT_CTRL 0x2c
62
Joe Hershberger9240a2f2017-06-26 14:40:08 -050063/* MII Status */
Marek Vasute40095f2016-05-24 23:29:09 +020064#define AG7XXX_ETH_MII_MGMT_STATUS 0x30
65
Joe Hershberger9240a2f2017-06-26 14:40:08 -050066/* MII Indicators */
Marek Vasute40095f2016-05-24 23:29:09 +020067#define AG7XXX_ETH_MII_MGMT_IND 0x34
68#define AG7XXX_ETH_MII_MGMT_IND_INVALID BIT(2)
69#define AG7XXX_ETH_MII_MGMT_IND_BUSY BIT(0)
70
Joe Hershberger9240a2f2017-06-26 14:40:08 -050071/* STA Address 1 & 2 */
Marek Vasute40095f2016-05-24 23:29:09 +020072#define AG7XXX_ETH_ADDR1 0x40
73#define AG7XXX_ETH_ADDR2 0x44
74
Joe Hershberger9240a2f2017-06-26 14:40:08 -050075/* ETH Configuration 0 - 5 */
Marek Vasute40095f2016-05-24 23:29:09 +020076#define AG7XXX_ETH_FIFO_CFG_0 0x48
77#define AG7XXX_ETH_FIFO_CFG_1 0x4c
78#define AG7XXX_ETH_FIFO_CFG_2 0x50
79#define AG7XXX_ETH_FIFO_CFG_3 0x54
80#define AG7XXX_ETH_FIFO_CFG_4 0x58
81#define AG7XXX_ETH_FIFO_CFG_5 0x5c
82
Joe Hershberger9240a2f2017-06-26 14:40:08 -050083/* DMA Transfer Control for Queue 0 */
Marek Vasute40095f2016-05-24 23:29:09 +020084#define AG7XXX_ETH_DMA_TX_CTRL 0x180
85#define AG7XXX_ETH_DMA_TX_CTRL_TXE BIT(0)
86
Joe Hershberger9240a2f2017-06-26 14:40:08 -050087/* Descriptor Address for Queue 0 Tx */
Marek Vasute40095f2016-05-24 23:29:09 +020088#define AG7XXX_ETH_DMA_TX_DESC 0x184
89
Joe Hershberger9240a2f2017-06-26 14:40:08 -050090/* DMA Tx Status */
Marek Vasute40095f2016-05-24 23:29:09 +020091#define AG7XXX_ETH_DMA_TX_STATUS 0x188
92
Joe Hershberger9240a2f2017-06-26 14:40:08 -050093/* Rx Control */
Marek Vasute40095f2016-05-24 23:29:09 +020094#define AG7XXX_ETH_DMA_RX_CTRL 0x18c
95#define AG7XXX_ETH_DMA_RX_CTRL_RXE BIT(0)
96
Joe Hershberger9240a2f2017-06-26 14:40:08 -050097/* Pointer to Rx Descriptor */
Marek Vasute40095f2016-05-24 23:29:09 +020098#define AG7XXX_ETH_DMA_RX_DESC 0x190
99
Joe Hershberger9240a2f2017-06-26 14:40:08 -0500100/* Rx Status */
Marek Vasute40095f2016-05-24 23:29:09 +0200101#define AG7XXX_ETH_DMA_RX_STATUS 0x194
102
Rosy Songf1f943e2019-02-05 17:50:44 +0800103/* Custom register at 0x1805002C */
104#define AG7XXX_ETH_XMII 0x2C
105#define AG7XXX_ETH_XMII_TX_INVERT BIT(31)
106#define AG7XXX_ETH_XMII_RX_DELAY_LSB 28
107#define AG7XXX_ETH_XMII_RX_DELAY_MASK 0x30000000
108#define AG7XXX_ETH_XMII_RX_DELAY_SET(x) \
109 (((x) << AG7XXX_ETH_XMII_RX_DELAY_LSB) & AG7XXX_ETH_XMII_RX_DELAY_MASK)
110#define AG7XXX_ETH_XMII_TX_DELAY_LSB 26
111#define AG7XXX_ETH_XMII_TX_DELAY_MASK 0x0c000000
112#define AG7XXX_ETH_XMII_TX_DELAY_SET(x) \
113 (((x) << AG7XXX_ETH_XMII_TX_DELAY_LSB) & AG7XXX_ETH_XMII_TX_DELAY_MASK)
114#define AG7XXX_ETH_XMII_GIGE BIT(25)
115
Marek Vasute40095f2016-05-24 23:29:09 +0200116/* Custom register at 0x18070000 */
117#define AG7XXX_GMAC_ETH_CFG 0x00
Rosy Songf1f943e2019-02-05 17:50:44 +0800118#define AG7XXX_ETH_CFG_RXDV_DELAY_LSB 16
119#define AG7XXX_ETH_CFG_RXDV_DELAY_MASK 0x00030000
120#define AG7XXX_ETH_CFG_RXDV_DELAY_SET(x) \
121 (((x) << AG7XXX_ETH_CFG_RXDV_DELAY_LSB) & AG7XXX_ETH_CFG_RXDV_DELAY_MASK)
122#define AG7XXX_ETH_CFG_RXD_DELAY_LSB 14
123#define AG7XXX_ETH_CFG_RXD_DELAY_MASK 0x0000c000
124#define AG7XXX_ETH_CFG_RXD_DELAY_SET(x) \
125 (((x) << AG7XXX_ETH_CFG_RXD_DELAY_LSB) & AG7XXX_ETH_CFG_RXD_DELAY_MASK)
Marek Vasute40095f2016-05-24 23:29:09 +0200126#define AG7XXX_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
127#define AG7XXX_ETH_CFG_SW_PHY_SWAP BIT(7)
128#define AG7XXX_ETH_CFG_SW_ONLY_MODE BIT(6)
129#define AG7XXX_ETH_CFG_GE0_ERR_EN BIT(5)
130#define AG7XXX_ETH_CFG_MII_GE0_SLAVE BIT(4)
131#define AG7XXX_ETH_CFG_MII_GE0_MASTER BIT(3)
132#define AG7XXX_ETH_CFG_GMII_GE0 BIT(2)
133#define AG7XXX_ETH_CFG_MII_GE0 BIT(1)
134#define AG7XXX_ETH_CFG_RGMII_GE0 BIT(0)
135
136#define CONFIG_TX_DESCR_NUM 8
137#define CONFIG_RX_DESCR_NUM 8
138#define CONFIG_ETH_BUFSIZE 2048
139#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
140#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
141
142/* DMA descriptor. */
143struct ag7xxx_dma_desc {
144 u32 data_addr;
145#define AG7XXX_DMADESC_IS_EMPTY BIT(31)
146#define AG7XXX_DMADESC_FTPP_OVERRIDE_OFFSET 16
147#define AG7XXX_DMADESC_PKT_SIZE_OFFSET 0
148#define AG7XXX_DMADESC_PKT_SIZE_MASK 0xfff
149 u32 config;
150 u32 next_desc;
151 u32 _pad[5];
152};
153
154struct ar7xxx_eth_priv {
155 struct ag7xxx_dma_desc tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
156 struct ag7xxx_dma_desc rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
157 char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
158 char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
159
160 void __iomem *regs;
161 void __iomem *phyregs;
162
163 struct eth_device *dev;
164 struct phy_device *phydev;
165 struct mii_dev *bus;
166
167 u32 interface;
168 u32 tx_currdescnum;
169 u32 rx_currdescnum;
170 enum ag7xxx_model model;
171};
172
173/*
174 * Switch and MDIO access
175 */
176static int ag7xxx_switch_read(struct mii_dev *bus, int addr, int reg, u16 *val)
177{
178 struct ar7xxx_eth_priv *priv = bus->priv;
179 void __iomem *regs = priv->phyregs;
180 int ret;
181
182 writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD);
183 writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg,
184 regs + AG7XXX_ETH_MII_MGMT_ADDRESS);
185 writel(AG7XXX_ETH_MII_MGMT_CMD_READ,
186 regs + AG7XXX_ETH_MII_MGMT_CMD);
187
Álvaro Fernández Rojas48263502018-01-23 17:14:55 +0100188 ret = wait_for_bit_le32(regs + AG7XXX_ETH_MII_MGMT_IND,
189 AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
Marek Vasute40095f2016-05-24 23:29:09 +0200190 if (ret)
191 return ret;
192
193 *val = readl(regs + AG7XXX_ETH_MII_MGMT_STATUS) & 0xffff;
194 writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD);
195
196 return 0;
197}
198
199static int ag7xxx_switch_write(struct mii_dev *bus, int addr, int reg, u16 val)
200{
201 struct ar7xxx_eth_priv *priv = bus->priv;
202 void __iomem *regs = priv->phyregs;
203 int ret;
204
205 writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg,
206 regs + AG7XXX_ETH_MII_MGMT_ADDRESS);
207 writel(val, regs + AG7XXX_ETH_MII_MGMT_CTRL);
208
Álvaro Fernández Rojas48263502018-01-23 17:14:55 +0100209 ret = wait_for_bit_le32(regs + AG7XXX_ETH_MII_MGMT_IND,
210 AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
Marek Vasute40095f2016-05-24 23:29:09 +0200211
212 return ret;
213}
214
215static int ag7xxx_switch_reg_read(struct mii_dev *bus, int reg, u32 *val)
216{
217 struct ar7xxx_eth_priv *priv = bus->priv;
218 u32 phy_addr;
219 u32 reg_addr;
220 u32 phy_temp;
221 u32 reg_temp;
222 u16 rv = 0;
223 int ret;
224
Rosy Songf1f943e2019-02-05 17:50:44 +0800225 if (priv->model == AG7XXX_MODEL_AG933X ||
226 priv->model == AG7XXX_MODEL_AG953X) {
Marek Vasute40095f2016-05-24 23:29:09 +0200227 phy_addr = 0x1f;
228 reg_addr = 0x10;
229 } else if (priv->model == AG7XXX_MODEL_AG934X) {
230 phy_addr = 0x18;
231 reg_addr = 0x00;
232 } else
233 return -EINVAL;
234
235 ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
236 if (ret)
237 return ret;
238
239 phy_temp = ((reg >> 6) & 0x7) | 0x10;
240 reg_temp = (reg >> 1) & 0x1e;
241 *val = 0;
242
243 ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 0, &rv);
244 if (ret < 0)
245 return ret;
246 *val |= rv;
247
248 ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 1, &rv);
249 if (ret < 0)
250 return ret;
251 *val |= (rv << 16);
252
253 return 0;
254}
255
256static int ag7xxx_switch_reg_write(struct mii_dev *bus, int reg, u32 val)
257{
258 struct ar7xxx_eth_priv *priv = bus->priv;
259 u32 phy_addr;
260 u32 reg_addr;
261 u32 phy_temp;
262 u32 reg_temp;
263 int ret;
264
Rosy Songf1f943e2019-02-05 17:50:44 +0800265 if (priv->model == AG7XXX_MODEL_AG933X ||
266 priv->model == AG7XXX_MODEL_AG953X) {
Marek Vasute40095f2016-05-24 23:29:09 +0200267 phy_addr = 0x1f;
268 reg_addr = 0x10;
269 } else if (priv->model == AG7XXX_MODEL_AG934X) {
270 phy_addr = 0x18;
271 reg_addr = 0x00;
272 } else
273 return -EINVAL;
274
275 ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
276 if (ret)
277 return ret;
278
279 phy_temp = ((reg >> 6) & 0x7) | 0x10;
280 reg_temp = (reg >> 1) & 0x1e;
281
282 /*
283 * The switch on AR933x has some special register behavior, which
284 * expects particular write order of their nibbles:
285 * 0x40 ..... MSB first, LSB second
286 * 0x50 ..... MSB first, LSB second
287 * 0x98 ..... LSB first, MSB second
288 * others ... don't care
289 */
290 if ((priv->model == AG7XXX_MODEL_AG933X) && (reg == 0x98)) {
291 ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff);
292 if (ret < 0)
293 return ret;
294
295 ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16);
296 if (ret < 0)
297 return ret;
298 } else {
299 ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16);
300 if (ret < 0)
301 return ret;
302
303 ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff);
304 if (ret < 0)
305 return ret;
306 }
307
308 return 0;
309}
310
Joe Hershberger2fd519f2017-06-26 14:40:09 -0500311static int ag7xxx_mdio_rw(struct mii_dev *bus, int addr, int reg, u32 val)
Marek Vasute40095f2016-05-24 23:29:09 +0200312{
313 u32 data;
Joe Hershberger2fd519f2017-06-26 14:40:09 -0500314 unsigned long start;
315 int ret;
316 /* No idea if this is long enough or too long */
317 int timeout_ms = 1000;
Marek Vasute40095f2016-05-24 23:29:09 +0200318
319 /* Dummy read followed by PHY read/write command. */
Joe Hershberger2fd519f2017-06-26 14:40:09 -0500320 ret = ag7xxx_switch_reg_read(bus, 0x98, &data);
321 if (ret < 0)
322 return ret;
Marek Vasute40095f2016-05-24 23:29:09 +0200323 data = val | (reg << 16) | (addr << 21) | BIT(30) | BIT(31);
Joe Hershberger2fd519f2017-06-26 14:40:09 -0500324 ret = ag7xxx_switch_reg_write(bus, 0x98, data);
325 if (ret < 0)
326 return ret;
327
328 start = get_timer(0);
Marek Vasute40095f2016-05-24 23:29:09 +0200329
330 /* Wait for operation to finish */
331 do {
Joe Hershberger2fd519f2017-06-26 14:40:09 -0500332 ret = ag7xxx_switch_reg_read(bus, 0x98, &data);
333 if (ret < 0)
334 return ret;
335
336 if (get_timer(start) > timeout_ms)
337 return -ETIMEDOUT;
Marek Vasute40095f2016-05-24 23:29:09 +0200338 } while (data & BIT(31));
339
340 return data & 0xffff;
341}
342
343static int ag7xxx_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
344{
345 return ag7xxx_mdio_rw(bus, addr, reg, BIT(27));
346}
347
348static int ag7xxx_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
349 u16 val)
350{
Joe Hershberger2fd519f2017-06-26 14:40:09 -0500351 int ret;
352
353 ret = ag7xxx_mdio_rw(bus, addr, reg, val);
354 if (ret < 0)
355 return ret;
Marek Vasute40095f2016-05-24 23:29:09 +0200356 return 0;
357}
358
359/*
360 * DMA ring handlers
361 */
362static void ag7xxx_dma_clean_tx(struct udevice *dev)
363{
364 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
365 struct ag7xxx_dma_desc *curr, *next;
366 u32 start, end;
367 int i;
368
369 for (i = 0; i < CONFIG_TX_DESCR_NUM; i++) {
370 curr = &priv->tx_mac_descrtable[i];
371 next = &priv->tx_mac_descrtable[(i + 1) % CONFIG_TX_DESCR_NUM];
372
373 curr->data_addr = virt_to_phys(&priv->txbuffs[i * CONFIG_ETH_BUFSIZE]);
374 curr->config = AG7XXX_DMADESC_IS_EMPTY;
375 curr->next_desc = virt_to_phys(next);
376 }
377
378 priv->tx_currdescnum = 0;
379
380 /* Cache: Flush descriptors, don't care about buffers. */
381 start = (u32)(&priv->tx_mac_descrtable[0]);
382 end = start + sizeof(priv->tx_mac_descrtable);
383 flush_dcache_range(start, end);
384}
385
386static void ag7xxx_dma_clean_rx(struct udevice *dev)
387{
388 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
389 struct ag7xxx_dma_desc *curr, *next;
390 u32 start, end;
391 int i;
392
393 for (i = 0; i < CONFIG_RX_DESCR_NUM; i++) {
394 curr = &priv->rx_mac_descrtable[i];
395 next = &priv->rx_mac_descrtable[(i + 1) % CONFIG_RX_DESCR_NUM];
396
397 curr->data_addr = virt_to_phys(&priv->rxbuffs[i * CONFIG_ETH_BUFSIZE]);
398 curr->config = AG7XXX_DMADESC_IS_EMPTY;
399 curr->next_desc = virt_to_phys(next);
400 }
401
402 priv->rx_currdescnum = 0;
403
404 /* Cache: Flush+Invalidate descriptors, Invalidate buffers. */
405 start = (u32)(&priv->rx_mac_descrtable[0]);
406 end = start + sizeof(priv->rx_mac_descrtable);
407 flush_dcache_range(start, end);
408 invalidate_dcache_range(start, end);
409
410 start = (u32)&priv->rxbuffs;
411 end = start + sizeof(priv->rxbuffs);
412 invalidate_dcache_range(start, end);
413}
414
415/*
416 * Ethernet I/O
417 */
418static int ag7xxx_eth_send(struct udevice *dev, void *packet, int length)
419{
420 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
421 struct ag7xxx_dma_desc *curr;
422 u32 start, end;
423
424 curr = &priv->tx_mac_descrtable[priv->tx_currdescnum];
425
426 /* Cache: Invalidate descriptor. */
427 start = (u32)curr;
428 end = start + sizeof(*curr);
429 invalidate_dcache_range(start, end);
430
431 if (!(curr->config & AG7XXX_DMADESC_IS_EMPTY)) {
432 printf("ag7xxx: Out of TX DMA descriptors!\n");
433 return -EPERM;
434 }
435
436 /* Copy the packet into the data buffer. */
437 memcpy(phys_to_virt(curr->data_addr), packet, length);
438 curr->config = length & AG7XXX_DMADESC_PKT_SIZE_MASK;
439
440 /* Cache: Flush descriptor, Flush buffer. */
441 start = (u32)curr;
442 end = start + sizeof(*curr);
443 flush_dcache_range(start, end);
444 start = (u32)phys_to_virt(curr->data_addr);
445 end = start + length;
446 flush_dcache_range(start, end);
447
448 /* Load the DMA descriptor and start TX DMA. */
449 writel(AG7XXX_ETH_DMA_TX_CTRL_TXE,
450 priv->regs + AG7XXX_ETH_DMA_TX_CTRL);
451
452 /* Switch to next TX descriptor. */
453 priv->tx_currdescnum = (priv->tx_currdescnum + 1) % CONFIG_TX_DESCR_NUM;
454
455 return 0;
456}
457
458static int ag7xxx_eth_recv(struct udevice *dev, int flags, uchar **packetp)
459{
460 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
461 struct ag7xxx_dma_desc *curr;
462 u32 start, end, length;
463
464 curr = &priv->rx_mac_descrtable[priv->rx_currdescnum];
465
466 /* Cache: Invalidate descriptor. */
467 start = (u32)curr;
468 end = start + sizeof(*curr);
469 invalidate_dcache_range(start, end);
470
471 /* No packets received. */
472 if (curr->config & AG7XXX_DMADESC_IS_EMPTY)
473 return -EAGAIN;
474
475 length = curr->config & AG7XXX_DMADESC_PKT_SIZE_MASK;
476
477 /* Cache: Invalidate buffer. */
478 start = (u32)phys_to_virt(curr->data_addr);
479 end = start + length;
480 invalidate_dcache_range(start, end);
481
482 /* Receive one packet and return length. */
483 *packetp = phys_to_virt(curr->data_addr);
484 return length;
485}
486
487static int ag7xxx_eth_free_pkt(struct udevice *dev, uchar *packet,
488 int length)
489{
490 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
491 struct ag7xxx_dma_desc *curr;
492 u32 start, end;
493
494 curr = &priv->rx_mac_descrtable[priv->rx_currdescnum];
495
496 curr->config = AG7XXX_DMADESC_IS_EMPTY;
497
498 /* Cache: Flush descriptor. */
499 start = (u32)curr;
500 end = start + sizeof(*curr);
501 flush_dcache_range(start, end);
502
503 /* Switch to next RX descriptor. */
504 priv->rx_currdescnum = (priv->rx_currdescnum + 1) % CONFIG_RX_DESCR_NUM;
505
506 return 0;
507}
508
509static int ag7xxx_eth_start(struct udevice *dev)
510{
511 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
512
513 /* FIXME: Check if link up */
514
515 /* Clear the DMA rings. */
516 ag7xxx_dma_clean_tx(dev);
517 ag7xxx_dma_clean_rx(dev);
518
519 /* Load DMA descriptors and start the RX DMA. */
520 writel(virt_to_phys(&priv->tx_mac_descrtable[priv->tx_currdescnum]),
521 priv->regs + AG7XXX_ETH_DMA_TX_DESC);
522 writel(virt_to_phys(&priv->rx_mac_descrtable[priv->rx_currdescnum]),
523 priv->regs + AG7XXX_ETH_DMA_RX_DESC);
524 writel(AG7XXX_ETH_DMA_RX_CTRL_RXE,
525 priv->regs + AG7XXX_ETH_DMA_RX_CTRL);
526
527 return 0;
528}
529
530static void ag7xxx_eth_stop(struct udevice *dev)
531{
532 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
533
534 /* Stop the TX DMA. */
535 writel(0, priv->regs + AG7XXX_ETH_DMA_TX_CTRL);
Álvaro Fernández Rojas48263502018-01-23 17:14:55 +0100536 wait_for_bit_le32(priv->regs + AG7XXX_ETH_DMA_TX_CTRL, ~0, 0,
537 1000, 0);
Marek Vasute40095f2016-05-24 23:29:09 +0200538
539 /* Stop the RX DMA. */
540 writel(0, priv->regs + AG7XXX_ETH_DMA_RX_CTRL);
Álvaro Fernández Rojas48263502018-01-23 17:14:55 +0100541 wait_for_bit_le32(priv->regs + AG7XXX_ETH_DMA_RX_CTRL, ~0, 0,
542 1000, 0);
Marek Vasute40095f2016-05-24 23:29:09 +0200543}
544
545/*
546 * Hardware setup
547 */
548static int ag7xxx_eth_write_hwaddr(struct udevice *dev)
549{
550 struct eth_pdata *pdata = dev_get_platdata(dev);
551 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
552 unsigned char *mac = pdata->enetaddr;
553 u32 macid_lo, macid_hi;
554
555 macid_hi = mac[3] | (mac[2] << 8) | (mac[1] << 16) | (mac[0] << 24);
556 macid_lo = (mac[5] << 16) | (mac[4] << 24);
557
558 writel(macid_lo, priv->regs + AG7XXX_ETH_ADDR1);
559 writel(macid_hi, priv->regs + AG7XXX_ETH_ADDR2);
560
561 return 0;
562}
563
564static void ag7xxx_hw_setup(struct udevice *dev)
565{
566 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
567 u32 speed;
568
569 setbits_be32(priv->regs + AG7XXX_ETH_CFG1,
570 AG7XXX_ETH_CFG1_RX_RST | AG7XXX_ETH_CFG1_TX_RST |
571 AG7XXX_ETH_CFG1_SOFT_RST);
572
573 mdelay(10);
574
575 writel(AG7XXX_ETH_CFG1_RX_EN | AG7XXX_ETH_CFG1_TX_EN,
576 priv->regs + AG7XXX_ETH_CFG1);
577
578 if (priv->interface == PHY_INTERFACE_MODE_RMII)
579 speed = AG7XXX_ETH_CFG2_IF_10_100;
580 else
581 speed = AG7XXX_ETH_CFG2_IF_1000;
582
583 clrsetbits_be32(priv->regs + AG7XXX_ETH_CFG2,
584 AG7XXX_ETH_CFG2_IF_SPEED_MASK,
585 speed | AG7XXX_ETH_CFG2_PAD_CRC_EN |
586 AG7XXX_ETH_CFG2_LEN_CHECK);
587
588 writel(0xfff0000, priv->regs + AG7XXX_ETH_FIFO_CFG_1);
589 writel(0x1fff, priv->regs + AG7XXX_ETH_FIFO_CFG_2);
590
591 writel(0x1f00, priv->regs + AG7XXX_ETH_FIFO_CFG_0);
592 setbits_be32(priv->regs + AG7XXX_ETH_FIFO_CFG_4, 0x3ffff);
593 writel(0x10ffff, priv->regs + AG7XXX_ETH_FIFO_CFG_1);
594 writel(0xaaa0555, priv->regs + AG7XXX_ETH_FIFO_CFG_2);
595 writel(0x7eccf, priv->regs + AG7XXX_ETH_FIFO_CFG_5);
596 writel(0x1f00140, priv->regs + AG7XXX_ETH_FIFO_CFG_3);
597}
598
599static int ag7xxx_mii_get_div(void)
600{
601 ulong freq = get_bus_freq(0);
602
603 switch (freq / 1000000) {
604 case 150: return 0x7;
605 case 175: return 0x5;
606 case 200: return 0x4;
607 case 210: return 0x9;
608 case 220: return 0x9;
609 default: return 0x7;
610 }
611}
612
613static int ag7xxx_mii_setup(struct udevice *dev)
614{
615 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
616 int i, ret, div = ag7xxx_mii_get_div();
617 u32 reg;
618
619 if (priv->model == AG7XXX_MODEL_AG933X) {
620 /* Unit 0 is PHY-less on AR9331, see datasheet Figure 2-3 */
621 if (priv->interface == PHY_INTERFACE_MODE_RMII)
622 return 0;
623 }
624
Rosy Songf1f943e2019-02-05 17:50:44 +0800625 if (priv->model == AG7XXX_MODEL_AG934X)
626 reg = 0x4;
627 else if (priv->model == AG7XXX_MODEL_AG953X)
628 reg = 0x2;
629
630 if (priv->model == AG7XXX_MODEL_AG934X ||
631 priv->model == AG7XXX_MODEL_AG953X) {
632 writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | reg,
Marek Vasute40095f2016-05-24 23:29:09 +0200633 priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
Rosy Songf1f943e2019-02-05 17:50:44 +0800634 writel(reg, priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
Marek Vasute40095f2016-05-24 23:29:09 +0200635 return 0;
636 }
637
638 for (i = 0; i < 10; i++) {
639 writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | div,
640 priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
641 writel(div, priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
642
643 /* Check the switch */
644 ret = ag7xxx_switch_reg_read(priv->bus, 0x10c, &reg);
645 if (ret)
646 continue;
647
648 if (reg != 0x18007fff)
649 continue;
650
651 return 0;
652 }
653
654 return -EINVAL;
655}
656
657static int ag933x_phy_setup_wan(struct udevice *dev)
658{
659 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
660
661 /* Configure switch port 4 (GMAC0) */
662 return ag7xxx_mdio_write(priv->bus, 4, 0, MII_BMCR, 0x9000);
663}
664
665static int ag933x_phy_setup_lan(struct udevice *dev)
666{
667 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
668 int i, ret;
669 u32 reg;
670
671 /* Reset the switch */
672 ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg);
673 if (ret)
674 return ret;
675 reg |= BIT(31);
676 ret = ag7xxx_switch_reg_write(priv->bus, 0, reg);
677 if (ret)
678 return ret;
679
680 do {
681 ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg);
682 if (ret)
683 return ret;
684 } while (reg & BIT(31));
685
686 /* Configure switch ports 0...3 (GMAC1) */
687 for (i = 0; i < 4; i++) {
688 ret = ag7xxx_mdio_write(priv->bus, 0x4, 0, MII_BMCR, 0x9000);
689 if (ret)
690 return ret;
691 }
692
693 /* Enable CPU port */
694 ret = ag7xxx_switch_reg_write(priv->bus, 0x78, BIT(8));
695 if (ret)
696 return ret;
697
698 for (i = 0; i < 4; i++) {
699 ret = ag7xxx_switch_reg_write(priv->bus, i * 0x100, BIT(9));
700 if (ret)
701 return ret;
702 }
703
704 /* QM Control */
705 ret = ag7xxx_switch_reg_write(priv->bus, 0x38, 0xc000050e);
706 if (ret)
707 return ret;
708
709 /* Disable Atheros header */
710 ret = ag7xxx_switch_reg_write(priv->bus, 0x104, 0x4004);
711 if (ret)
712 return ret;
713
714 /* Tag priority mapping */
715 ret = ag7xxx_switch_reg_write(priv->bus, 0x70, 0xfa50);
716 if (ret)
717 return ret;
718
719 /* Enable ARP packets to the CPU */
720 ret = ag7xxx_switch_reg_read(priv->bus, 0x5c, &reg);
721 if (ret)
722 return ret;
723 reg |= 0x100000;
724 ret = ag7xxx_switch_reg_write(priv->bus, 0x5c, reg);
725 if (ret)
726 return ret;
727
728 return 0;
729}
730
Rosy Songf1f943e2019-02-05 17:50:44 +0800731static int ag953x_phy_setup_wan(struct udevice *dev)
732{
733 int ret;
734 u32 reg = 0;
735 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
736
737 /* Set wan port connect to GE0 */
738 ret = ag7xxx_switch_reg_read(priv->bus, 0x8, &reg);
739 if (ret)
740 return ret;
741
742 ret = ag7xxx_switch_reg_write(priv->bus, 0x8, reg | BIT(28));
743 if (ret)
744 return ret;
745
746 /* Configure switch port 4 (GMAC0) */
747 ret = ag7xxx_switch_write(priv->bus, 4, MII_BMCR, 0x9000);
748 if (ret)
749 return ret;
750
751 return 0;
752}
753
754static int ag953x_phy_setup_lan(struct udevice *dev)
755{
756 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
757 int i, ret;
758 u32 reg = 0;
759
760 /* Reset the switch */
761 ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg);
762 if (ret)
763 return ret;
764
765 ret = ag7xxx_switch_reg_write(priv->bus, 0, reg | BIT(31));
766 if (ret)
767 return ret;
768
769 do {
770 ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg);
771 if (ret)
772 return ret;
773 } while (reg & BIT(31));
774
775 ret = ag7xxx_switch_reg_write(priv->bus, 0x100, 0x4e);
776 if (ret)
777 return ret;
778
779 /* Set GMII mode */
780 ret = ag7xxx_switch_reg_read(priv->bus, 0x4, &reg);
781 if (ret)
782 return ret;
783
784 ret = ag7xxx_switch_reg_write(priv->bus, 0x4, reg | BIT(6));
785 if (ret)
786 return ret;
787
788 /* Configure switch ports 0...4 (GMAC1) */
789 for (i = 0; i < 5; i++) {
790 ret = ag7xxx_switch_write(priv->bus, i, MII_BMCR, 0x9000);
791 if (ret)
792 return ret;
793 }
794
795 for (i = 0; i < 5; i++) {
796 ret = ag7xxx_switch_reg_write(priv->bus, (i + 2) * 0x100, BIT(9));
797 if (ret)
798 return ret;
799 }
800
801 /* QM Control */
802 ret = ag7xxx_switch_reg_write(priv->bus, 0x38, 0xc000050e);
803 if (ret)
804 return ret;
805
806 /* Disable Atheros header */
807 ret = ag7xxx_switch_reg_write(priv->bus, 0x104, 0x4004);
808 if (ret)
809 return ret;
810
811 /* Tag priority mapping */
812 ret = ag7xxx_switch_reg_write(priv->bus, 0x70, 0xfa50);
813 if (ret)
814 return ret;
815
816 /* Enable ARP packets to the CPU */
817 ret = ag7xxx_switch_reg_read(priv->bus, 0x5c, &reg);
818 if (ret)
819 return ret;
820
821 ret = ag7xxx_switch_reg_write(priv->bus, 0x5c, reg | 0x100000);
822 if (ret)
823 return ret;
824
825 /* Enable broadcast packets to the CPU */
826 ret = ag7xxx_switch_reg_read(priv->bus, 0x2c, &reg);
827 if (ret)
828 return ret;
829
830 ret = ag7xxx_switch_reg_write(priv->bus, 0x2c, reg | BIT(25) | BIT(26));
831 if (ret)
832 return ret;
833
834 return 0;
835}
836
Marek Vasute40095f2016-05-24 23:29:09 +0200837static int ag933x_phy_setup_reset_set(struct udevice *dev, int port)
838{
839 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
840 int ret;
841
Rosy Songf1f943e2019-02-05 17:50:44 +0800842 if (priv->model == AG7XXX_MODEL_AG953X) {
843 ret = ag7xxx_switch_write(priv->bus, port, MII_ADVERTISE,
844 ADVERTISE_ALL);
845 } else {
846 ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_ADVERTISE,
847 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
848 ADVERTISE_PAUSE_ASYM);
849 }
Marek Vasute40095f2016-05-24 23:29:09 +0200850 if (ret)
851 return ret;
852
853 if (priv->model == AG7XXX_MODEL_AG934X) {
854 ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_CTRL1000,
855 ADVERTISE_1000FULL);
856 if (ret)
857 return ret;
858 }
859
Rosy Songf1f943e2019-02-05 17:50:44 +0800860 if (priv->model == AG7XXX_MODEL_AG953X)
861 return ag7xxx_switch_write(priv->bus, port, MII_BMCR,
862 BMCR_ANENABLE | BMCR_RESET);
863
Marek Vasute40095f2016-05-24 23:29:09 +0200864 return ag7xxx_mdio_write(priv->bus, port, 0, MII_BMCR,
865 BMCR_ANENABLE | BMCR_RESET);
866}
867
868static int ag933x_phy_setup_reset_fin(struct udevice *dev, int port)
869{
870 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
871 int ret;
Rosy Songf1f943e2019-02-05 17:50:44 +0800872 u16 reg;
Marek Vasute40095f2016-05-24 23:29:09 +0200873
Rosy Songf1f943e2019-02-05 17:50:44 +0800874 if (priv->model == AG7XXX_MODEL_AG953X) {
875 do {
876 ret = ag7xxx_switch_read(priv->bus, port, MII_BMCR, &reg);
877 if (ret < 0)
878 return ret;
879 mdelay(10);
880 } while (reg & BMCR_RESET);
881 } else {
882 do {
883 ret = ag7xxx_mdio_read(priv->bus, port, 0, MII_BMCR);
884 if (ret < 0)
885 return ret;
886 mdelay(10);
887 } while (ret & BMCR_RESET);
888 }
Marek Vasute40095f2016-05-24 23:29:09 +0200889
890 return 0;
891}
892
893static int ag933x_phy_setup_common(struct udevice *dev)
894{
895 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
896 int i, ret, phymax;
Rosy Songf1f943e2019-02-05 17:50:44 +0800897 u16 reg;
Marek Vasute40095f2016-05-24 23:29:09 +0200898
899 if (priv->model == AG7XXX_MODEL_AG933X)
900 phymax = 4;
Rosy Songf1f943e2019-02-05 17:50:44 +0800901 else if (priv->model == AG7XXX_MODEL_AG934X ||
902 priv->model == AG7XXX_MODEL_AG953X)
Marek Vasute40095f2016-05-24 23:29:09 +0200903 phymax = 5;
904 else
905 return -EINVAL;
906
907 if (priv->interface == PHY_INTERFACE_MODE_RMII) {
908 ret = ag933x_phy_setup_reset_set(dev, phymax);
909 if (ret)
910 return ret;
911
912 ret = ag933x_phy_setup_reset_fin(dev, phymax);
913 if (ret)
914 return ret;
915
916 /* Read out link status */
Rosy Songf1f943e2019-02-05 17:50:44 +0800917 if (priv->model == AG7XXX_MODEL_AG953X)
918 ret = ag7xxx_switch_read(priv->bus, phymax, MII_MIPSCR, &reg);
919 else
920 ret = ag7xxx_mdio_read(priv->bus, phymax, 0, MII_MIPSCR);
Marek Vasute40095f2016-05-24 23:29:09 +0200921 if (ret < 0)
922 return ret;
923
924 return 0;
925 }
926
927 /* Switch ports */
928 for (i = 0; i < phymax; i++) {
929 ret = ag933x_phy_setup_reset_set(dev, i);
930 if (ret)
931 return ret;
932 }
933
934 for (i = 0; i < phymax; i++) {
935 ret = ag933x_phy_setup_reset_fin(dev, i);
936 if (ret)
937 return ret;
938 }
939
940 for (i = 0; i < phymax; i++) {
941 /* Read out link status */
Rosy Songf1f943e2019-02-05 17:50:44 +0800942 if (priv->model == AG7XXX_MODEL_AG953X)
943 ret = ag7xxx_switch_read(priv->bus, i, MII_MIPSCR, &reg);
944 else
945 ret = ag7xxx_mdio_read(priv->bus, i, 0, MII_MIPSCR);
Marek Vasute40095f2016-05-24 23:29:09 +0200946 if (ret < 0)
947 return ret;
948 }
949
950 return 0;
951}
952
953static int ag934x_phy_setup(struct udevice *dev)
954{
955 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
956 int i, ret;
957 u32 reg;
958
959 ret = ag7xxx_switch_reg_write(priv->bus, 0x624, 0x7f7f7f7f);
960 if (ret)
961 return ret;
962 ret = ag7xxx_switch_reg_write(priv->bus, 0x10, 0x40000000);
963 if (ret)
964 return ret;
965 ret = ag7xxx_switch_reg_write(priv->bus, 0x4, 0x07600000);
966 if (ret)
967 return ret;
968 ret = ag7xxx_switch_reg_write(priv->bus, 0xc, 0x01000000);
969 if (ret)
970 return ret;
971 ret = ag7xxx_switch_reg_write(priv->bus, 0x7c, 0x0000007e);
972 if (ret)
973 return ret;
974
975 /* AR8327/AR8328 v1.0 fixup */
976 ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg);
977 if (ret)
978 return ret;
979 if ((reg & 0xffff) == 0x1201) {
980 for (i = 0; i < 5; i++) {
981 ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x0);
982 if (ret)
983 return ret;
984 ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x02ea);
985 if (ret)
986 return ret;
987 ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x3d);
988 if (ret)
989 return ret;
990 ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x68a0);
991 if (ret)
992 return ret;
993 }
994 }
995
996 ret = ag7xxx_switch_reg_read(priv->bus, 0x66c, &reg);
997 if (ret)
998 return ret;
999 reg &= ~0x70000;
1000 ret = ag7xxx_switch_reg_write(priv->bus, 0x66c, reg);
1001 if (ret)
1002 return ret;
1003
1004 return 0;
1005}
1006
1007static int ag7xxx_mac_probe(struct udevice *dev)
1008{
1009 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
1010 int ret;
1011
1012 ag7xxx_hw_setup(dev);
1013 ret = ag7xxx_mii_setup(dev);
1014 if (ret)
1015 return ret;
1016
1017 ag7xxx_eth_write_hwaddr(dev);
1018
1019 if (priv->model == AG7XXX_MODEL_AG933X) {
1020 if (priv->interface == PHY_INTERFACE_MODE_RMII)
1021 ret = ag933x_phy_setup_wan(dev);
1022 else
1023 ret = ag933x_phy_setup_lan(dev);
Rosy Songf1f943e2019-02-05 17:50:44 +08001024 } else if (priv->model == AG7XXX_MODEL_AG953X) {
1025 if (priv->interface == PHY_INTERFACE_MODE_RMII)
1026 ret = ag953x_phy_setup_wan(dev);
1027 else
1028 ret = ag953x_phy_setup_lan(dev);
Marek Vasute40095f2016-05-24 23:29:09 +02001029 } else if (priv->model == AG7XXX_MODEL_AG934X) {
1030 ret = ag934x_phy_setup(dev);
1031 } else {
1032 return -EINVAL;
1033 }
1034
1035 if (ret)
1036 return ret;
1037
1038 return ag933x_phy_setup_common(dev);
1039}
1040
1041static int ag7xxx_mdio_probe(struct udevice *dev)
1042{
1043 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
1044 struct mii_dev *bus = mdio_alloc();
1045
1046 if (!bus)
1047 return -ENOMEM;
1048
1049 bus->read = ag7xxx_mdio_read;
1050 bus->write = ag7xxx_mdio_write;
1051 snprintf(bus->name, sizeof(bus->name), dev->name);
1052
1053 bus->priv = (void *)priv;
1054
1055 return mdio_register(bus);
1056}
1057
1058static int ag7xxx_get_phy_iface_offset(struct udevice *dev)
1059{
1060 int offset;
1061
Simon Glasse160f7d2017-01-17 16:52:55 -07001062 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev), "phy");
Marek Vasute40095f2016-05-24 23:29:09 +02001063 if (offset <= 0) {
1064 debug("%s: PHY OF node not found (ret=%i)\n", __func__, offset);
1065 return -EINVAL;
1066 }
1067
1068 offset = fdt_parent_offset(gd->fdt_blob, offset);
1069 if (offset <= 0) {
1070 debug("%s: PHY OF node parent MDIO bus not found (ret=%i)\n",
1071 __func__, offset);
1072 return -EINVAL;
1073 }
1074
1075 offset = fdt_parent_offset(gd->fdt_blob, offset);
1076 if (offset <= 0) {
1077 debug("%s: PHY MDIO OF node parent MAC not found (ret=%i)\n",
1078 __func__, offset);
1079 return -EINVAL;
1080 }
1081
1082 return offset;
1083}
1084
1085static int ag7xxx_eth_probe(struct udevice *dev)
1086{
1087 struct eth_pdata *pdata = dev_get_platdata(dev);
1088 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
1089 void __iomem *iobase, *phyiobase;
1090 int ret, phyreg;
1091
1092 /* Decoding of convoluted PHY wiring on Atheros MIPS. */
1093 ret = ag7xxx_get_phy_iface_offset(dev);
1094 if (ret <= 0)
1095 return ret;
1096 phyreg = fdtdec_get_int(gd->fdt_blob, ret, "reg", -1);
1097
1098 iobase = map_physmem(pdata->iobase, 0x200, MAP_NOCACHE);
1099 phyiobase = map_physmem(phyreg, 0x200, MAP_NOCACHE);
1100
1101 debug("%s, iobase=%p, phyiobase=%p, priv=%p\n",
1102 __func__, iobase, phyiobase, priv);
1103 priv->regs = iobase;
1104 priv->phyregs = phyiobase;
1105 priv->interface = pdata->phy_interface;
1106 priv->model = dev_get_driver_data(dev);
1107
1108 ret = ag7xxx_mdio_probe(dev);
1109 if (ret)
1110 return ret;
1111
1112 priv->bus = miiphy_get_dev_by_name(dev->name);
1113
1114 ret = ag7xxx_mac_probe(dev);
1115 debug("%s, ret=%d\n", __func__, ret);
1116
1117 return ret;
1118}
1119
1120static int ag7xxx_eth_remove(struct udevice *dev)
1121{
1122 struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
1123
1124 free(priv->phydev);
1125 mdio_unregister(priv->bus);
1126 mdio_free(priv->bus);
1127
1128 return 0;
1129}
1130
1131static const struct eth_ops ag7xxx_eth_ops = {
1132 .start = ag7xxx_eth_start,
1133 .send = ag7xxx_eth_send,
1134 .recv = ag7xxx_eth_recv,
1135 .free_pkt = ag7xxx_eth_free_pkt,
1136 .stop = ag7xxx_eth_stop,
1137 .write_hwaddr = ag7xxx_eth_write_hwaddr,
1138};
1139
1140static int ag7xxx_eth_ofdata_to_platdata(struct udevice *dev)
1141{
1142 struct eth_pdata *pdata = dev_get_platdata(dev);
1143 const char *phy_mode;
1144 int ret;
1145
Simon Glassa821c4a2017-05-17 17:18:05 -06001146 pdata->iobase = devfdt_get_addr(dev);
Marek Vasute40095f2016-05-24 23:29:09 +02001147 pdata->phy_interface = -1;
1148
1149 /* Decoding of convoluted PHY wiring on Atheros MIPS. */
1150 ret = ag7xxx_get_phy_iface_offset(dev);
1151 if (ret <= 0)
1152 return ret;
1153
1154 phy_mode = fdt_getprop(gd->fdt_blob, ret, "phy-mode", NULL);
1155 if (phy_mode)
1156 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
1157 if (pdata->phy_interface == -1) {
1158 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1159 return -EINVAL;
1160 }
1161
1162 return 0;
1163}
1164
1165static const struct udevice_id ag7xxx_eth_ids[] = {
1166 { .compatible = "qca,ag933x-mac", .data = AG7XXX_MODEL_AG933X },
1167 { .compatible = "qca,ag934x-mac", .data = AG7XXX_MODEL_AG934X },
Rosy Songf1f943e2019-02-05 17:50:44 +08001168 { .compatible = "qca,ag953x-mac", .data = AG7XXX_MODEL_AG953X },
Marek Vasute40095f2016-05-24 23:29:09 +02001169 { }
1170};
1171
1172U_BOOT_DRIVER(eth_ag7xxx) = {
1173 .name = "eth_ag7xxx",
1174 .id = UCLASS_ETH,
1175 .of_match = ag7xxx_eth_ids,
1176 .ofdata_to_platdata = ag7xxx_eth_ofdata_to_platdata,
1177 .probe = ag7xxx_eth_probe,
1178 .remove = ag7xxx_eth_remove,
1179 .ops = &ag7xxx_eth_ops,
1180 .priv_auto_alloc_size = sizeof(struct ar7xxx_eth_priv),
1181 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1182 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1183};