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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +01002/*
3 * [origin: Linux kernel drivers/watchdog/at91sam9_wdt.c]
4 *
5 * Watchdog driver for Atmel AT91SAM9x processors.
6 *
7 * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8 * Copyright (C) 2008 Renaud CERRATO r.cerrato@til-technologies.fr
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +01009 */
10
11/*
12 * The Watchdog Timer Mode Register can be only written to once. If the
13 * timeout need to be set from U-Boot, be sure that the bootstrap doesn't
14 * write to this register. Inform Linux to it too
15 */
16
17#include <common.h>
18#include <watchdog.h>
19#include <asm/arch/hardware.h>
Reinhard Meyer7f6ed7f2011-02-04 20:17:33 +010020#include <asm/io.h>
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010021#include <asm/arch/at91_wdt.h>
22
23/*
24 * AT91SAM9 watchdog runs a 12bit counter @ 256Hz,
25 * use this to convert a watchdog
26 * value from/to milliseconds.
27 */
28#define ms_to_ticks(t) (((t << 8) / 1000) - 1)
29#define ticks_to_ms(t) (((t + 1) * 1000) >> 8)
30
31/* Hardware timeout in seconds */
Heiko Schocher7bae0d62015-01-21 08:38:22 +010032#if !defined(CONFIG_AT91_HW_WDT_TIMEOUT)
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010033#define WDT_HW_TIMEOUT 2
Heiko Schocher7bae0d62015-01-21 08:38:22 +010034#else
35#define WDT_HW_TIMEOUT CONFIG_AT91_HW_WDT_TIMEOUT
36#endif
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010037
38/*
39 * Set the watchdog time interval in 1/256Hz (write-once)
40 * Counter is 12 bit.
41 */
42static int at91_wdt_settimeout(unsigned int timeout)
43{
44 unsigned int reg;
Reinhard Meyer372f2782010-11-03 15:47:20 +010045 at91_wdt_t *wd = (at91_wdt_t *) ATMEL_BASE_WDT;
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010046
47 /* Check if disabled */
Achim Ehrlichf936aa02010-03-17 14:50:29 +010048 if (readl(&wd->mr) & AT91_WDT_MR_WDDIS) {
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010049 printf("sorry, watchdog is disabled\n");
50 return -1;
51 }
52
53 /*
54 * All counting occurs at SLOW_CLOCK / 128 = 256 Hz
55 *
56 * Since WDV is a 12-bit counter, the maximum period is
57 * 4096 / 256 = 16 seconds.
58 */
Achim Ehrlichf936aa02010-03-17 14:50:29 +010059
60 reg = AT91_WDT_MR_WDRSTEN /* causes watchdog reset */
61 | AT91_WDT_MR_WDDBGHLT /* disabled in debug mode */
62 | AT91_WDT_MR_WDD(0xfff) /* restart at any time */
63 | AT91_WDT_MR_WDV(timeout); /* timer value */
64
65 writel(reg, &wd->mr);
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010066
67 return 0;
68}
69
70void hw_watchdog_reset(void)
71{
Reinhard Meyer372f2782010-11-03 15:47:20 +010072 at91_wdt_t *wd = (at91_wdt_t *) ATMEL_BASE_WDT;
Achim Ehrlichf936aa02010-03-17 14:50:29 +010073 writel(AT91_WDT_CR_WDRSTT | AT91_WDT_CR_KEY, &wd->cr);
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010074}
75
76void hw_watchdog_init(void)
77{
78 /* 16 seconds timer, resets enabled */
79 at91_wdt_settimeout(ms_to_ticks(WDT_HW_TIMEOUT * 1000));
80}