blob: ac53239363c7478bc0d7f86f26f17983437b21ff [file] [log] [blame]
Simon Glass99c15652015-08-30 16:55:31 -06001/*
2 * (C) Copyright 2015 Google, Inc
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7#include <common.h>
David Wuef4cf5a2017-09-20 14:28:19 +08008#include <bitfield.h>
Stephen Warren135aa952016-06-17 09:44:00 -06009#include <clk-uclass.h>
Simon Glass99c15652015-08-30 16:55:31 -060010#include <dm.h>
Simon Glass2d143bd2016-07-04 11:58:29 -060011#include <dt-structs.h>
Simon Glass99c15652015-08-30 16:55:31 -060012#include <errno.h>
Simon Glass2d143bd2016-07-04 11:58:29 -060013#include <mapmem.h>
Simon Glass99c15652015-08-30 16:55:31 -060014#include <syscon.h>
15#include <asm/io.h>
16#include <asm/arch/clock.h>
17#include <asm/arch/cru_rk3288.h>
18#include <asm/arch/grf_rk3288.h>
19#include <asm/arch/hardware.h>
Simon Glass898d6432016-01-21 19:43:38 -070020#include <dt-bindings/clock/rk3288-cru.h>
Simon Glass64b7faa2016-01-21 19:43:41 -070021#include <dm/device-internal.h>
Simon Glass99c15652015-08-30 16:55:31 -060022#include <dm/lists.h>
Simon Glass64b7faa2016-01-21 19:43:41 -070023#include <dm/uclass-internal.h>
Heiko Stübnerabd01282016-07-22 23:51:06 +020024#include <linux/log2.h>
Simon Glass99c15652015-08-30 16:55:31 -060025
26DECLARE_GLOBAL_DATA_PTR;
27
Simon Glass2d143bd2016-07-04 11:58:29 -060028struct rk3288_clk_plat {
29#if CONFIG_IS_ENABLED(OF_PLATDATA)
30 struct dtd_rockchip_rk3288_cru dtd;
31#endif
32};
33
Simon Glass99c15652015-08-30 16:55:31 -060034struct pll_div {
35 u32 nr;
36 u32 nf;
37 u32 no;
38};
39
40enum {
41 VCO_MAX_HZ = 2200U * 1000000,
42 VCO_MIN_HZ = 440 * 1000000,
43 OUTPUT_MAX_HZ = 2200U * 1000000,
44 OUTPUT_MIN_HZ = 27500000,
45 FREF_MAX_HZ = 2200U * 1000000,
Heiko Stübnerc3f03ff2016-07-16 00:17:17 +020046 FREF_MIN_HZ = 269 * 1000,
Simon Glass99c15652015-08-30 16:55:31 -060047};
48
49enum {
50 /* PLL CON0 */
51 PLL_OD_MASK = 0x0f,
52
53 /* PLL CON1 */
54 PLL_NF_MASK = 0x1fff,
55
56 /* PLL CON2 */
57 PLL_BWADJ_MASK = 0x0fff,
58
59 /* PLL CON3 */
60 PLL_RESET_SHIFT = 5,
61
Simon Glassdae594f2016-01-21 19:45:17 -070062 /* CLKSEL0 */
Simon Glassdae594f2016-01-21 19:45:17 -070063 CORE_SEL_PLL_SHIFT = 15,
Simon Glassb223c1a2017-05-31 17:57:31 -060064 CORE_SEL_PLL_MASK = 1 << CORE_SEL_PLL_SHIFT,
Simon Glassdae594f2016-01-21 19:45:17 -070065 A17_DIV_SHIFT = 8,
Simon Glassb223c1a2017-05-31 17:57:31 -060066 A17_DIV_MASK = 0x1f << A17_DIV_SHIFT,
Simon Glassdae594f2016-01-21 19:45:17 -070067 MP_DIV_SHIFT = 4,
Simon Glassb223c1a2017-05-31 17:57:31 -060068 MP_DIV_MASK = 0xf << MP_DIV_SHIFT,
Simon Glassdae594f2016-01-21 19:45:17 -070069 M0_DIV_SHIFT = 0,
Simon Glassb223c1a2017-05-31 17:57:31 -060070 M0_DIV_MASK = 0xf << M0_DIV_SHIFT,
Simon Glassdae594f2016-01-21 19:45:17 -070071
Simon Glass99c15652015-08-30 16:55:31 -060072 /* CLKSEL1: pd bus clk pll sel: codec or general */
73 PD_BUS_SEL_PLL_MASK = 15,
74 PD_BUS_SEL_CPLL = 0,
75 PD_BUS_SEL_GPLL,
76
77 /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */
78 PD_BUS_PCLK_DIV_SHIFT = 12,
Simon Glassb223c1a2017-05-31 17:57:31 -060079 PD_BUS_PCLK_DIV_MASK = 7 << PD_BUS_PCLK_DIV_SHIFT,
Simon Glass99c15652015-08-30 16:55:31 -060080
81 /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
82 PD_BUS_HCLK_DIV_SHIFT = 8,
Simon Glassb223c1a2017-05-31 17:57:31 -060083 PD_BUS_HCLK_DIV_MASK = 3 << PD_BUS_HCLK_DIV_SHIFT,
Simon Glass99c15652015-08-30 16:55:31 -060084
85 /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */
86 PD_BUS_ACLK_DIV0_SHIFT = 3,
Simon Glassb223c1a2017-05-31 17:57:31 -060087 PD_BUS_ACLK_DIV0_MASK = 0x1f << PD_BUS_ACLK_DIV0_SHIFT,
Simon Glass99c15652015-08-30 16:55:31 -060088 PD_BUS_ACLK_DIV1_SHIFT = 0,
Simon Glassb223c1a2017-05-31 17:57:31 -060089 PD_BUS_ACLK_DIV1_MASK = 0x7 << PD_BUS_ACLK_DIV1_SHIFT,
Simon Glass99c15652015-08-30 16:55:31 -060090
91 /*
92 * CLKSEL10
93 * peripheral bus pclk div:
94 * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1
95 */
Simon Glassc87c1292016-01-21 19:45:15 -070096 PERI_SEL_PLL_SHIFT = 15,
Simon Glassb223c1a2017-05-31 17:57:31 -060097 PERI_SEL_PLL_MASK = 1 << PERI_SEL_PLL_SHIFT,
Simon Glassc87c1292016-01-21 19:45:15 -070098 PERI_SEL_CPLL = 0,
99 PERI_SEL_GPLL,
100
Simon Glass99c15652015-08-30 16:55:31 -0600101 PERI_PCLK_DIV_SHIFT = 12,
Simon Glassb223c1a2017-05-31 17:57:31 -0600102 PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT,
Simon Glass99c15652015-08-30 16:55:31 -0600103
104 /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
105 PERI_HCLK_DIV_SHIFT = 8,
Simon Glassb223c1a2017-05-31 17:57:31 -0600106 PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT,
Simon Glass99c15652015-08-30 16:55:31 -0600107
108 /*
109 * peripheral bus aclk div:
110 * aclk_periph = periph_clk_src / (peri_aclk_div_con + 1)
111 */
112 PERI_ACLK_DIV_SHIFT = 0,
Simon Glassb223c1a2017-05-31 17:57:31 -0600113 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
Simon Glass99c15652015-08-30 16:55:31 -0600114
David Wuef4cf5a2017-09-20 14:28:19 +0800115 /*
116 * CLKSEL24
117 * saradc_div_con:
118 * clk_saradc=24MHz/(saradc_div_con+1)
119 */
120 CLK_SARADC_DIV_CON_SHIFT = 8,
121 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
122 CLK_SARADC_DIV_CON_WIDTH = 8,
123
Simon Glass99c15652015-08-30 16:55:31 -0600124 SOCSTS_DPLL_LOCK = 1 << 5,
125 SOCSTS_APLL_LOCK = 1 << 6,
126 SOCSTS_CPLL_LOCK = 1 << 7,
127 SOCSTS_GPLL_LOCK = 1 << 8,
128 SOCSTS_NPLL_LOCK = 1 << 9,
129};
130
Simon Glass99c15652015-08-30 16:55:31 -0600131#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
132
133#define PLL_DIVISORS(hz, _nr, _no) {\
134 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
135 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
136 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
137 "divisors on line " __stringify(__LINE__));
138
139/* Keep divisors as low as possible to reduce jitter and power usage */
140static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
141static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
142static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
143
144static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
145 const struct pll_div *div)
146{
147 int pll_id = rk_pll_id(clk_id);
148 struct rk3288_pll *pll = &cru->pll[pll_id];
149 /* All PLLs have same VCO and output frequency range restrictions. */
150 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
151 uint output_hz = vco_hz / div->no;
152
Simon Glassc87c1292016-01-21 19:45:15 -0700153 debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
154 (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
Simon Glass99c15652015-08-30 16:55:31 -0600155 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
156 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
157 (div->no == 1 || !(div->no % 2)));
158
Simon Glassc87c1292016-01-21 19:45:15 -0700159 /* enter reset */
Simon Glass99c15652015-08-30 16:55:31 -0600160 rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
161
Simon Glassb223c1a2017-05-31 17:57:31 -0600162 rk_clrsetreg(&pll->con0, CLKR_MASK | PLL_OD_MASK,
Simon Glass99c15652015-08-30 16:55:31 -0600163 ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
164 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
165 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
166
167 udelay(10);
168
Simon Glassc87c1292016-01-21 19:45:15 -0700169 /* return from reset */
Simon Glass99c15652015-08-30 16:55:31 -0600170 rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
171
172 return 0;
173}
174
Simon Glass99c15652015-08-30 16:55:31 -0600175static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,
176 unsigned int hz)
177{
178 static const struct pll_div dpll_cfg[] = {
179 {.nf = 25, .nr = 2, .no = 1},
180 {.nf = 400, .nr = 9, .no = 2},
181 {.nf = 500, .nr = 9, .no = 2},
182 {.nf = 100, .nr = 3, .no = 1},
183 };
184 int cfg;
185
Simon Glass99c15652015-08-30 16:55:31 -0600186 switch (hz) {
187 case 300000000:
188 cfg = 0;
189 break;
190 case 533000000: /* actually 533.3P MHz */
191 cfg = 1;
192 break;
193 case 666000000: /* actually 666.6P MHz */
194 cfg = 2;
195 break;
196 case 800000000:
197 cfg = 3;
198 break;
199 default:
Simon Glassc87c1292016-01-21 19:45:15 -0700200 debug("Unsupported SDRAM frequency");
Simon Glass99c15652015-08-30 16:55:31 -0600201 return -EINVAL;
202 }
203
204 /* pll enter slow-mode */
Simon Glassb223c1a2017-05-31 17:57:31 -0600205 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
Simon Glass99c15652015-08-30 16:55:31 -0600206 DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
207
208 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
209
210 /* wait for pll lock */
211 while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK))
212 udelay(1);
213
214 /* PLL enter normal-mode */
Simon Glassb223c1a2017-05-31 17:57:31 -0600215 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
Simon Glass009741f2016-01-21 19:45:01 -0700216 DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
Simon Glass99c15652015-08-30 16:55:31 -0600217
218 return 0;
219}
220
Simon Glass830a6082016-01-21 19:45:02 -0700221#ifndef CONFIG_SPL_BUILD
222#define VCO_MAX_KHZ 2200000
223#define VCO_MIN_KHZ 440000
224#define FREF_MAX_KHZ 2200000
225#define FREF_MIN_KHZ 269
226
227static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
228{
229 uint ref_khz = OSC_HZ / 1000, nr, nf = 0;
230 uint fref_khz;
231 uint diff_khz, best_diff_khz;
232 const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4;
233 uint vco_khz;
234 uint no = 1;
235 uint freq_khz = freq_hz / 1000;
236
237 if (!freq_hz) {
238 printf("%s: the frequency can not be 0 Hz\n", __func__);
239 return -EINVAL;
240 }
241
242 no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
243 if (ext_div) {
244 *ext_div = DIV_ROUND_UP(no, max_no);
245 no = DIV_ROUND_UP(no, *ext_div);
246 }
247
248 /* only even divisors (and 1) are supported */
249 if (no > 1)
250 no = DIV_ROUND_UP(no, 2) * 2;
251
252 vco_khz = freq_khz * no;
253 if (ext_div)
254 vco_khz *= *ext_div;
255
256 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) {
257 printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n",
258 __func__, freq_hz);
259 return -1;
260 }
261
262 div->no = no;
263
264 best_diff_khz = vco_khz;
265 for (nr = 1; nr < max_nr && best_diff_khz; nr++) {
266 fref_khz = ref_khz / nr;
267 if (fref_khz < FREF_MIN_KHZ)
268 break;
269 if (fref_khz > FREF_MAX_KHZ)
270 continue;
271
272 nf = vco_khz / fref_khz;
273 if (nf >= max_nf)
274 continue;
275 diff_khz = vco_khz - nf * fref_khz;
276 if (nf + 1 < max_nf && diff_khz > fref_khz / 2) {
277 nf++;
278 diff_khz = fref_khz - diff_khz;
279 }
280
281 if (diff_khz >= best_diff_khz)
282 continue;
283
284 best_diff_khz = diff_khz;
285 div->nr = nr;
286 div->nf = nf;
287 }
288
289 if (best_diff_khz > 4 * 1000) {
290 printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n",
291 __func__, freq_hz, best_diff_khz * 1000);
292 return -EINVAL;
293 }
294
295 return 0;
296}
297
Sjoerd Simons0aefc0b2016-02-28 22:24:59 +0100298static int rockchip_mac_set_clk(struct rk3288_cru *cru,
299 int periph, uint freq)
300{
301 /* Assuming mac_clk is fed by an external clock */
302 rk_clrsetreg(&cru->cru_clksel_con[21],
Simon Glassb223c1a2017-05-31 17:57:31 -0600303 RMII_EXTCLK_MASK,
Sjoerd Simons0aefc0b2016-02-28 22:24:59 +0100304 RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
305
306 return 0;
307}
308
Simon Glass830a6082016-01-21 19:45:02 -0700309static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
310 int periph, unsigned int rate_hz)
311{
312 struct pll_div npll_config = {0};
313 u32 lcdc_div;
314 int ret;
315
316 ret = pll_para_config(rate_hz, &npll_config, &lcdc_div);
317 if (ret)
318 return ret;
319
Simon Glassb223c1a2017-05-31 17:57:31 -0600320 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,
Simon Glass830a6082016-01-21 19:45:02 -0700321 NPLL_MODE_SLOW << NPLL_MODE_SHIFT);
322 rkclk_set_pll(cru, CLK_NEW, &npll_config);
323
324 /* waiting for pll lock */
325 while (1) {
326 if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK)
327 break;
328 udelay(1);
329 }
330
Simon Glassb223c1a2017-05-31 17:57:31 -0600331 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,
Simon Glass830a6082016-01-21 19:45:02 -0700332 NPLL_MODE_NORMAL << NPLL_MODE_SHIFT);
333
334 /* vop dclk source clk: npll,dclk_div: 1 */
335 switch (periph) {
336 case DCLK_VOP0:
337 rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0,
338 (lcdc_div - 1) << 8 | 2 << 0);
339 break;
340 case DCLK_VOP1:
341 rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6,
342 (lcdc_div - 1) << 8 | 2 << 6);
343 break;
344 }
345
346 return 0;
347}
Simon Glassd3cb46a2017-05-31 17:57:32 -0600348#endif /* CONFIG_SPL_BUILD */
Simon Glass830a6082016-01-21 19:45:02 -0700349
Simon Glass99c15652015-08-30 16:55:31 -0600350static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
351{
352 u32 aclk_div;
353 u32 hclk_div;
354 u32 pclk_div;
355
356 /* pll enter slow-mode */
357 rk_clrsetreg(&cru->cru_mode_con,
Simon Glassb223c1a2017-05-31 17:57:31 -0600358 GPLL_MODE_MASK | CPLL_MODE_MASK,
Simon Glass99c15652015-08-30 16:55:31 -0600359 GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
360 CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
361
362 /* init pll */
363 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
364 rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
365
366 /* waiting for pll lock */
367 while ((readl(&grf->soc_status[1]) &
368 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
369 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
370 udelay(1);
371
372 /*
373 * pd_bus clock pll source selection and
374 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
375 */
376 aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1;
377 assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
378 hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1;
379 assert((hclk_div + 1) * PD_BUS_HCLK_HZ ==
380 PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2));
381
382 pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1;
383 assert((pclk_div + 1) * PD_BUS_PCLK_HZ ==
384 PD_BUS_ACLK_HZ && pclk_div < 0x7);
385
386 rk_clrsetreg(&cru->cru_clksel_con[1],
Simon Glassb223c1a2017-05-31 17:57:31 -0600387 PD_BUS_PCLK_DIV_MASK | PD_BUS_HCLK_DIV_MASK |
388 PD_BUS_ACLK_DIV0_MASK | PD_BUS_ACLK_DIV1_MASK,
Simon Glass99c15652015-08-30 16:55:31 -0600389 pclk_div << PD_BUS_PCLK_DIV_SHIFT |
390 hclk_div << PD_BUS_HCLK_DIV_SHIFT |
391 aclk_div << PD_BUS_ACLK_DIV0_SHIFT |
392 0 << 0);
393
394 /*
395 * peri clock pll source selection and
396 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
397 */
398 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
399 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
400
Heiko Stübnerabd01282016-07-22 23:51:06 +0200401 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
Simon Glass99c15652015-08-30 16:55:31 -0600402 assert((1 << hclk_div) * PERI_HCLK_HZ ==
403 PERI_ACLK_HZ && (hclk_div < 0x4));
404
Heiko Stübnerabd01282016-07-22 23:51:06 +0200405 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
Simon Glass99c15652015-08-30 16:55:31 -0600406 assert((1 << pclk_div) * PERI_PCLK_HZ ==
407 PERI_ACLK_HZ && (pclk_div < 0x4));
408
409 rk_clrsetreg(&cru->cru_clksel_con[10],
Simon Glassb223c1a2017-05-31 17:57:31 -0600410 PERI_PCLK_DIV_MASK | PERI_HCLK_DIV_MASK |
411 PERI_ACLK_DIV_MASK,
Simon Glassc87c1292016-01-21 19:45:15 -0700412 PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
Simon Glass99c15652015-08-30 16:55:31 -0600413 pclk_div << PERI_PCLK_DIV_SHIFT |
414 hclk_div << PERI_HCLK_DIV_SHIFT |
415 aclk_div << PERI_ACLK_DIV_SHIFT);
416
417 /* PLL enter normal-mode */
418 rk_clrsetreg(&cru->cru_mode_con,
Simon Glassb223c1a2017-05-31 17:57:31 -0600419 GPLL_MODE_MASK | CPLL_MODE_MASK,
Simon Glass009741f2016-01-21 19:45:01 -0700420 GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
421 CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
Simon Glass99c15652015-08-30 16:55:31 -0600422}
Simon Glass99c15652015-08-30 16:55:31 -0600423
Heiko Stübnerb339b5d2016-07-16 00:17:16 +0200424void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
Simon Glassdae594f2016-01-21 19:45:17 -0700425{
426 /* pll enter slow-mode */
Simon Glassb223c1a2017-05-31 17:57:31 -0600427 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
Simon Glassdae594f2016-01-21 19:45:17 -0700428 APLL_MODE_SLOW << APLL_MODE_SHIFT);
429
430 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
431
432 /* waiting for pll lock */
433 while (!(readl(&grf->soc_status[1]) & SOCSTS_APLL_LOCK))
434 udelay(1);
435
436 /*
437 * core clock pll source selection and
438 * set up dependent divisors for MPAXI/M0AXI and ARM clocks.
439 * core clock select apll, apll clk = 1800MHz
440 * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz
441 */
442 rk_clrsetreg(&cru->cru_clksel_con[0],
Simon Glassb223c1a2017-05-31 17:57:31 -0600443 CORE_SEL_PLL_MASK | A17_DIV_MASK | MP_DIV_MASK |
444 M0_DIV_MASK,
Simon Glassdae594f2016-01-21 19:45:17 -0700445 0 << A17_DIV_SHIFT |
446 3 << MP_DIV_SHIFT |
447 1 << M0_DIV_SHIFT);
448
449 /*
450 * set up dependent divisors for L2RAM/ATCLK and PCLK clocks.
451 * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz
452 */
453 rk_clrsetreg(&cru->cru_clksel_con[37],
Simon Glassb223c1a2017-05-31 17:57:31 -0600454 CLK_L2RAM_DIV_MASK | ATCLK_CORE_DIV_CON_MASK |
455 PCLK_CORE_DBG_DIV_MASK,
Simon Glassdae594f2016-01-21 19:45:17 -0700456 1 << CLK_L2RAM_DIV_SHIFT |
457 3 << ATCLK_CORE_DIV_CON_SHIFT |
458 3 << PCLK_CORE_DBG_DIV_SHIFT);
459
460 /* PLL enter normal-mode */
Simon Glassb223c1a2017-05-31 17:57:31 -0600461 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
Simon Glassdae594f2016-01-21 19:45:17 -0700462 APLL_MODE_NORMAL << APLL_MODE_SHIFT);
463}
464
Simon Glass99c15652015-08-30 16:55:31 -0600465/* Get pll rate by id */
466static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
467 enum rk_clk_id clk_id)
468{
469 uint32_t nr, no, nf;
470 uint32_t con;
471 int pll_id = rk_pll_id(clk_id);
472 struct rk3288_pll *pll = &cru->pll[pll_id];
473 static u8 clk_shift[CLK_COUNT] = {
Simon Glass009741f2016-01-21 19:45:01 -0700474 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
475 GPLL_MODE_SHIFT, NPLL_MODE_SHIFT
Simon Glass99c15652015-08-30 16:55:31 -0600476 };
477 uint shift;
478
479 con = readl(&cru->cru_mode_con);
480 shift = clk_shift[clk_id];
Simon Glassb223c1a2017-05-31 17:57:31 -0600481 switch ((con >> shift) & CRU_MODE_MASK) {
Simon Glass009741f2016-01-21 19:45:01 -0700482 case APLL_MODE_SLOW:
Simon Glass99c15652015-08-30 16:55:31 -0600483 return OSC_HZ;
Simon Glass009741f2016-01-21 19:45:01 -0700484 case APLL_MODE_NORMAL:
Simon Glass99c15652015-08-30 16:55:31 -0600485 /* normal mode */
486 con = readl(&pll->con0);
Simon Glassb223c1a2017-05-31 17:57:31 -0600487 no = ((con & CLKOD_MASK) >> CLKOD_SHIFT) + 1;
488 nr = ((con & CLKR_MASK) >> CLKR_SHIFT) + 1;
Simon Glass99c15652015-08-30 16:55:31 -0600489 con = readl(&pll->con1);
Simon Glassb223c1a2017-05-31 17:57:31 -0600490 nf = ((con & CLKF_MASK) >> CLKF_SHIFT) + 1;
Simon Glass99c15652015-08-30 16:55:31 -0600491
492 return (24 * nf / (nr * no)) * 1000000;
Simon Glass009741f2016-01-21 19:45:01 -0700493 case APLL_MODE_DEEP:
Simon Glass99c15652015-08-30 16:55:31 -0600494 default:
495 return 32768;
496 }
497}
498
Simon Glass542635a2016-01-21 19:43:39 -0700499static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
Simon Glass898d6432016-01-21 19:43:38 -0700500 int periph)
Simon Glass99c15652015-08-30 16:55:31 -0600501{
502 uint src_rate;
503 uint div, mux;
504 u32 con;
505
506 switch (periph) {
Simon Glass898d6432016-01-21 19:43:38 -0700507 case HCLK_EMMC:
Xu Ziyuan45112272017-04-16 17:44:45 +0800508 case SCLK_EMMC:
Simon Glass99c15652015-08-30 16:55:31 -0600509 con = readl(&cru->cru_clksel_con[12]);
Simon Glassb223c1a2017-05-31 17:57:31 -0600510 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
511 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
Simon Glass99c15652015-08-30 16:55:31 -0600512 break;
Simon Glass898d6432016-01-21 19:43:38 -0700513 case HCLK_SDMMC:
Xu Ziyuan45112272017-04-16 17:44:45 +0800514 case SCLK_SDMMC:
Simon Glass898d6432016-01-21 19:43:38 -0700515 con = readl(&cru->cru_clksel_con[11]);
Simon Glassb223c1a2017-05-31 17:57:31 -0600516 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
517 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
Simon Glass99c15652015-08-30 16:55:31 -0600518 break;
Simon Glass898d6432016-01-21 19:43:38 -0700519 case HCLK_SDIO0:
Xu Ziyuan45112272017-04-16 17:44:45 +0800520 case SCLK_SDIO0:
Simon Glass99c15652015-08-30 16:55:31 -0600521 con = readl(&cru->cru_clksel_con[12]);
Simon Glassb223c1a2017-05-31 17:57:31 -0600522 mux = (con & SDIO0_PLL_MASK) >> SDIO0_PLL_SHIFT;
523 div = (con & SDIO0_DIV_MASK) >> SDIO0_DIV_SHIFT;
Simon Glass99c15652015-08-30 16:55:31 -0600524 break;
525 default:
526 return -EINVAL;
527 }
528
Simon Glass542635a2016-01-21 19:43:39 -0700529 src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate;
Simon Glass99c15652015-08-30 16:55:31 -0600530 return DIV_TO_RATE(src_rate, div);
531}
532
Simon Glass542635a2016-01-21 19:43:39 -0700533static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
Simon Glass898d6432016-01-21 19:43:38 -0700534 int periph, uint freq)
Simon Glass99c15652015-08-30 16:55:31 -0600535{
536 int src_clk_div;
537 int mux;
538
Simon Glass542635a2016-01-21 19:43:39 -0700539 debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
Kever Yang3a94d752017-07-27 12:54:01 +0800540 /* mmc clock default div 2 internal, need provide double in cru */
541 src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq);
Simon Glass99c15652015-08-30 16:55:31 -0600542
543 if (src_clk_div > 0x3f) {
Kever Yang3a94d752017-07-27 12:54:01 +0800544 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
Kever Yang217273c2017-07-27 12:54:02 +0800545 assert(src_clk_div < 0x40);
Simon Glass99c15652015-08-30 16:55:31 -0600546 mux = EMMC_PLL_SELECT_24MHZ;
547 assert((int)EMMC_PLL_SELECT_24MHZ ==
548 (int)MMC0_PLL_SELECT_24MHZ);
549 } else {
550 mux = EMMC_PLL_SELECT_GENERAL;
551 assert((int)EMMC_PLL_SELECT_GENERAL ==
552 (int)MMC0_PLL_SELECT_GENERAL);
553 }
554 switch (periph) {
Simon Glass898d6432016-01-21 19:43:38 -0700555 case HCLK_EMMC:
Xu Ziyuan45112272017-04-16 17:44:45 +0800556 case SCLK_EMMC:
Simon Glass99c15652015-08-30 16:55:31 -0600557 rk_clrsetreg(&cru->cru_clksel_con[12],
Simon Glassb223c1a2017-05-31 17:57:31 -0600558 EMMC_PLL_MASK | EMMC_DIV_MASK,
Simon Glass99c15652015-08-30 16:55:31 -0600559 mux << EMMC_PLL_SHIFT |
560 (src_clk_div - 1) << EMMC_DIV_SHIFT);
561 break;
Simon Glass898d6432016-01-21 19:43:38 -0700562 case HCLK_SDMMC:
Xu Ziyuan45112272017-04-16 17:44:45 +0800563 case SCLK_SDMMC:
Simon Glass99c15652015-08-30 16:55:31 -0600564 rk_clrsetreg(&cru->cru_clksel_con[11],
Simon Glassb223c1a2017-05-31 17:57:31 -0600565 MMC0_PLL_MASK | MMC0_DIV_MASK,
Simon Glass99c15652015-08-30 16:55:31 -0600566 mux << MMC0_PLL_SHIFT |
567 (src_clk_div - 1) << MMC0_DIV_SHIFT);
568 break;
Simon Glass898d6432016-01-21 19:43:38 -0700569 case HCLK_SDIO0:
Xu Ziyuan45112272017-04-16 17:44:45 +0800570 case SCLK_SDIO0:
Simon Glass99c15652015-08-30 16:55:31 -0600571 rk_clrsetreg(&cru->cru_clksel_con[12],
Simon Glassb223c1a2017-05-31 17:57:31 -0600572 SDIO0_PLL_MASK | SDIO0_DIV_MASK,
Simon Glass99c15652015-08-30 16:55:31 -0600573 mux << SDIO0_PLL_SHIFT |
574 (src_clk_div - 1) << SDIO0_DIV_SHIFT);
575 break;
576 default:
577 return -EINVAL;
578 }
579
Simon Glass542635a2016-01-21 19:43:39 -0700580 return rockchip_mmc_get_clk(cru, gclk_rate, periph);
Simon Glass99c15652015-08-30 16:55:31 -0600581}
582
Simon Glass542635a2016-01-21 19:43:39 -0700583static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
Simon Glass898d6432016-01-21 19:43:38 -0700584 int periph)
Simon Glass99c15652015-08-30 16:55:31 -0600585{
586 uint div, mux;
587 u32 con;
588
589 switch (periph) {
Simon Glass898d6432016-01-21 19:43:38 -0700590 case SCLK_SPI0:
Simon Glass99c15652015-08-30 16:55:31 -0600591 con = readl(&cru->cru_clksel_con[25]);
Simon Glassb223c1a2017-05-31 17:57:31 -0600592 mux = (con & SPI0_PLL_MASK) >> SPI0_PLL_SHIFT;
593 div = (con & SPI0_DIV_MASK) >> SPI0_DIV_SHIFT;
Simon Glass99c15652015-08-30 16:55:31 -0600594 break;
Simon Glass898d6432016-01-21 19:43:38 -0700595 case SCLK_SPI1:
Simon Glass99c15652015-08-30 16:55:31 -0600596 con = readl(&cru->cru_clksel_con[25]);
Simon Glassb223c1a2017-05-31 17:57:31 -0600597 mux = (con & SPI1_PLL_MASK) >> SPI1_PLL_SHIFT;
598 div = (con & SPI1_DIV_MASK) >> SPI1_DIV_SHIFT;
Simon Glass99c15652015-08-30 16:55:31 -0600599 break;
Simon Glass898d6432016-01-21 19:43:38 -0700600 case SCLK_SPI2:
Simon Glass99c15652015-08-30 16:55:31 -0600601 con = readl(&cru->cru_clksel_con[39]);
Simon Glassb223c1a2017-05-31 17:57:31 -0600602 mux = (con & SPI2_PLL_MASK) >> SPI2_PLL_SHIFT;
603 div = (con & SPI2_DIV_MASK) >> SPI2_DIV_SHIFT;
Simon Glass99c15652015-08-30 16:55:31 -0600604 break;
605 default:
606 return -EINVAL;
607 }
608 assert(mux == SPI0_PLL_SELECT_GENERAL);
609
Simon Glass542635a2016-01-21 19:43:39 -0700610 return DIV_TO_RATE(gclk_rate, div);
Simon Glass99c15652015-08-30 16:55:31 -0600611}
612
Simon Glass542635a2016-01-21 19:43:39 -0700613static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
Simon Glass898d6432016-01-21 19:43:38 -0700614 int periph, uint freq)
Simon Glass99c15652015-08-30 16:55:31 -0600615{
616 int src_clk_div;
617
Simon Glass542635a2016-01-21 19:43:39 -0700618 debug("%s: clk_general_rate=%u\n", __func__, gclk_rate);
Kever Yang217273c2017-07-27 12:54:02 +0800619 src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1;
620 assert(src_clk_div < 128);
Simon Glass99c15652015-08-30 16:55:31 -0600621 switch (periph) {
Simon Glass898d6432016-01-21 19:43:38 -0700622 case SCLK_SPI0:
Simon Glass99c15652015-08-30 16:55:31 -0600623 rk_clrsetreg(&cru->cru_clksel_con[25],
Simon Glassb223c1a2017-05-31 17:57:31 -0600624 SPI0_PLL_MASK | SPI0_DIV_MASK,
Simon Glass99c15652015-08-30 16:55:31 -0600625 SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT |
626 src_clk_div << SPI0_DIV_SHIFT);
627 break;
Simon Glass898d6432016-01-21 19:43:38 -0700628 case SCLK_SPI1:
Simon Glass99c15652015-08-30 16:55:31 -0600629 rk_clrsetreg(&cru->cru_clksel_con[25],
Simon Glassb223c1a2017-05-31 17:57:31 -0600630 SPI1_PLL_MASK | SPI1_DIV_MASK,
Simon Glass99c15652015-08-30 16:55:31 -0600631 SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT |
632 src_clk_div << SPI1_DIV_SHIFT);
633 break;
Simon Glass898d6432016-01-21 19:43:38 -0700634 case SCLK_SPI2:
Simon Glass99c15652015-08-30 16:55:31 -0600635 rk_clrsetreg(&cru->cru_clksel_con[39],
Simon Glassb223c1a2017-05-31 17:57:31 -0600636 SPI2_PLL_MASK | SPI2_DIV_MASK,
Simon Glass99c15652015-08-30 16:55:31 -0600637 SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT |
638 src_clk_div << SPI2_DIV_SHIFT);
639 break;
640 default:
641 return -EINVAL;
642 }
643
Simon Glass542635a2016-01-21 19:43:39 -0700644 return rockchip_spi_get_clk(cru, gclk_rate, periph);
Simon Glass99c15652015-08-30 16:55:31 -0600645}
646
David Wuef4cf5a2017-09-20 14:28:19 +0800647static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru)
648{
649 u32 div, val;
650
651 val = readl(&cru->cru_clksel_con[24]);
652 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
653 CLK_SARADC_DIV_CON_WIDTH);
654
655 return DIV_TO_RATE(OSC_HZ, div);
656}
657
658static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz)
659{
660 int src_clk_div;
661
662 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
663 assert(src_clk_div < 128);
664
665 rk_clrsetreg(&cru->cru_clksel_con[24],
666 CLK_SARADC_DIV_CON_MASK,
667 src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
668
669 return rockchip_saradc_get_clk(cru);
670}
671
Stephen Warren135aa952016-06-17 09:44:00 -0600672static ulong rk3288_clk_get_rate(struct clk *clk)
Simon Glass4f436732016-01-21 19:43:40 -0700673{
Stephen Warren135aa952016-06-17 09:44:00 -0600674 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
Simon Glass4f436732016-01-21 19:43:40 -0700675 ulong new_rate, gclk_rate;
Simon Glass4f436732016-01-21 19:43:40 -0700676
Stephen Warren135aa952016-06-17 09:44:00 -0600677 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
678 switch (clk->id) {
679 case 0 ... 63:
680 new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
681 break;
Simon Glass4f436732016-01-21 19:43:40 -0700682 case HCLK_EMMC:
Simon Glass342999f2016-01-21 19:43:45 -0700683 case HCLK_SDMMC:
Simon Glass4f436732016-01-21 19:43:40 -0700684 case HCLK_SDIO0:
Xu Ziyuan45112272017-04-16 17:44:45 +0800685 case SCLK_EMMC:
686 case SCLK_SDMMC:
687 case SCLK_SDIO0:
Stephen Warren135aa952016-06-17 09:44:00 -0600688 new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
Simon Glass4f436732016-01-21 19:43:40 -0700689 break;
690 case SCLK_SPI0:
691 case SCLK_SPI1:
692 case SCLK_SPI2:
Stephen Warren135aa952016-06-17 09:44:00 -0600693 new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id);
Simon Glass4f436732016-01-21 19:43:40 -0700694 break;
695 case PCLK_I2C0:
696 case PCLK_I2C1:
697 case PCLK_I2C2:
698 case PCLK_I2C3:
699 case PCLK_I2C4:
700 case PCLK_I2C5:
701 return gclk_rate;
Kever Yang4f0b8ef2016-08-12 17:57:05 +0800702 case PCLK_PWM:
703 return PD_BUS_PCLK_HZ;
David Wuef4cf5a2017-09-20 14:28:19 +0800704 case SCLK_SARADC:
705 new_rate = rockchip_saradc_get_clk(priv->cru);
706 break;
Simon Glass4f436732016-01-21 19:43:40 -0700707 default:
708 return -ENOENT;
709 }
710
711 return new_rate;
712}
713
Stephen Warren135aa952016-06-17 09:44:00 -0600714static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
Simon Glass99c15652015-08-30 16:55:31 -0600715{
Stephen Warren135aa952016-06-17 09:44:00 -0600716 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
Simon Glass830a6082016-01-21 19:45:02 -0700717 struct rk3288_cru *cru = priv->cru;
Simon Glass898d6432016-01-21 19:43:38 -0700718 ulong new_rate, gclk_rate;
Simon Glass99c15652015-08-30 16:55:31 -0600719
Stephen Warren135aa952016-06-17 09:44:00 -0600720 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
721 switch (clk->id) {
Simon Glass3a8a42d2016-11-13 14:22:13 -0700722 case PLL_APLL:
723 /* We only support a fixed rate here */
724 if (rate != 1800000000)
725 return -EINVAL;
726 rk3288_clk_configure_cpu(priv->cru, priv->grf);
727 new_rate = rate;
728 break;
Stephen Warren135aa952016-06-17 09:44:00 -0600729 case CLK_DDR:
730 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate);
731 break;
Simon Glass898d6432016-01-21 19:43:38 -0700732 case HCLK_EMMC:
733 case HCLK_SDMMC:
734 case HCLK_SDIO0:
Xu Ziyuan45112272017-04-16 17:44:45 +0800735 case SCLK_EMMC:
736 case SCLK_SDMMC:
737 case SCLK_SDIO0:
Stephen Warren135aa952016-06-17 09:44:00 -0600738 new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate);
Simon Glass99c15652015-08-30 16:55:31 -0600739 break;
Simon Glass898d6432016-01-21 19:43:38 -0700740 case SCLK_SPI0:
741 case SCLK_SPI1:
742 case SCLK_SPI2:
Stephen Warren135aa952016-06-17 09:44:00 -0600743 new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate);
Simon Glass99c15652015-08-30 16:55:31 -0600744 break;
Simon Glass830a6082016-01-21 19:45:02 -0700745#ifndef CONFIG_SPL_BUILD
Sjoerd Simons0aefc0b2016-02-28 22:24:59 +0100746 case SCLK_MAC:
Stephen Warren135aa952016-06-17 09:44:00 -0600747 new_rate = rockchip_mac_set_clk(priv->cru, clk->id, rate);
Sjoerd Simons0aefc0b2016-02-28 22:24:59 +0100748 break;
Simon Glass830a6082016-01-21 19:45:02 -0700749 case DCLK_VOP0:
750 case DCLK_VOP1:
Stephen Warren135aa952016-06-17 09:44:00 -0600751 new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate);
Simon Glass830a6082016-01-21 19:45:02 -0700752 break;
753 case SCLK_EDP_24M:
754 /* clk_edp_24M source: 24M */
755 rk_setreg(&cru->cru_clksel_con[28], 1 << 15);
756
757 /* rst edp */
758 rk_setreg(&cru->cru_clksel_con[6], 1 << 15);
759 udelay(1);
760 rk_clrreg(&cru->cru_clksel_con[6], 1 << 15);
761 new_rate = rate;
762 break;
763 case ACLK_VOP0:
764 case ACLK_VOP1: {
765 u32 div;
766
767 /* vop aclk source clk: cpll */
768 div = CPLL_HZ / rate;
769 assert((div - 1 < 64) && (div * rate == CPLL_HZ));
770
Stephen Warren135aa952016-06-17 09:44:00 -0600771 switch (clk->id) {
Simon Glass830a6082016-01-21 19:45:02 -0700772 case ACLK_VOP0:
773 rk_clrsetreg(&cru->cru_clksel_con[31],
774 3 << 6 | 0x1f << 0,
775 0 << 6 | (div - 1) << 0);
776 break;
777 case ACLK_VOP1:
778 rk_clrsetreg(&cru->cru_clksel_con[31],
779 3 << 14 | 0x1f << 8,
780 0 << 14 | (div - 1) << 8);
781 break;
782 }
783 new_rate = rate;
784 break;
785 }
786 case PCLK_HDMI_CTRL:
787 /* enable pclk hdmi ctrl */
788 rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9);
789
790 /* software reset hdmi */
791 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9);
792 udelay(1);
793 rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9);
794 new_rate = rate;
795 break;
796#endif
David Wuef4cf5a2017-09-20 14:28:19 +0800797 case SCLK_SARADC:
798 new_rate = rockchip_saradc_set_clk(priv->cru, rate);
799 break;
Simon Glass99c15652015-08-30 16:55:31 -0600800 default:
801 return -ENOENT;
802 }
803
804 return new_rate;
805}
806
807static struct clk_ops rk3288_clk_ops = {
808 .get_rate = rk3288_clk_get_rate,
809 .set_rate = rk3288_clk_set_rate,
Simon Glass99c15652015-08-30 16:55:31 -0600810};
811
Simon Glass08fd82c2016-07-04 11:58:28 -0600812static int rk3288_clk_ofdata_to_platdata(struct udevice *dev)
Simon Glass99c15652015-08-30 16:55:31 -0600813{
Simon Glass2d143bd2016-07-04 11:58:29 -0600814#if !CONFIG_IS_ENABLED(OF_PLATDATA)
Simon Glass99c15652015-08-30 16:55:31 -0600815 struct rk3288_clk_priv *priv = dev_get_priv(dev);
816
Simon Glassa821c4a2017-05-17 17:18:05 -0600817 priv->cru = (struct rk3288_cru *)devfdt_get_addr(dev);
Simon Glass2d143bd2016-07-04 11:58:29 -0600818#endif
Simon Glass08fd82c2016-07-04 11:58:28 -0600819
820 return 0;
821}
822
823static int rk3288_clk_probe(struct udevice *dev)
824{
825 struct rk3288_clk_priv *priv = dev_get_priv(dev);
Simon Glassd3cb46a2017-05-31 17:57:32 -0600826 bool init_clocks = false;
Simon Glass08fd82c2016-07-04 11:58:28 -0600827
Simon Glass99c15652015-08-30 16:55:31 -0600828 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
Simon Glass08fd82c2016-07-04 11:58:28 -0600829 if (IS_ERR(priv->grf))
830 return PTR_ERR(priv->grf);
Simon Glass99c15652015-08-30 16:55:31 -0600831#ifdef CONFIG_SPL_BUILD
Simon Glass2d143bd2016-07-04 11:58:29 -0600832#if CONFIG_IS_ENABLED(OF_PLATDATA)
833 struct rk3288_clk_plat *plat = dev_get_platdata(dev);
834
835 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
836#endif
Simon Glassd3cb46a2017-05-31 17:57:32 -0600837 init_clocks = true;
Simon Glass99c15652015-08-30 16:55:31 -0600838#endif
Simon Glassd3cb46a2017-05-31 17:57:32 -0600839 if (!(gd->flags & GD_FLG_RELOC)) {
840 u32 reg;
841
842 /*
843 * Init clocks in U-Boot proper if the NPLL is runnning. This
844 * indicates that a previous boot loader set up the clocks, so
845 * we need to redo it. U-Boot's SPL does not set this clock.
846 */
847 reg = readl(&priv->cru->cru_mode_con);
848 if (((reg & NPLL_MODE_MASK) >> NPLL_MODE_SHIFT) ==
849 NPLL_MODE_NORMAL)
850 init_clocks = true;
851 }
852
853 if (init_clocks)
854 rkclk_init(priv->cru, priv->grf);
Simon Glass99c15652015-08-30 16:55:31 -0600855
856 return 0;
857}
858
Simon Glass99c15652015-08-30 16:55:31 -0600859static int rk3288_clk_bind(struct udevice *dev)
860{
Stephen Warren135aa952016-06-17 09:44:00 -0600861 int ret;
Kever Yangf24e36d2017-11-03 15:16:13 +0800862 struct udevice *sys_child;
863 struct sysreset_reg *priv;
Simon Glass99c15652015-08-30 16:55:31 -0600864
865 /* The reset driver does not have a device node, so bind it here */
Kever Yangf24e36d2017-11-03 15:16:13 +0800866 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
867 &sys_child);
868 if (ret) {
869 debug("Warning: No sysreset driver: ret=%d\n", ret);
870 } else {
871 priv = malloc(sizeof(struct sysreset_reg));
872 priv->glb_srst_fst_value = offsetof(struct rk3288_cru,
873 cru_glb_srst_fst_value);
874 priv->glb_srst_snd_value = offsetof(struct rk3288_cru,
875 cru_glb_srst_snd_value);
876 sys_child->priv = priv;
877 }
Simon Glass99c15652015-08-30 16:55:31 -0600878
879 return 0;
880}
881
882static const struct udevice_id rk3288_clk_ids[] = {
883 { .compatible = "rockchip,rk3288-cru" },
884 { }
885};
886
Simon Glass2d143bd2016-07-04 11:58:29 -0600887U_BOOT_DRIVER(rockchip_rk3288_cru) = {
888 .name = "rockchip_rk3288_cru",
Simon Glass99c15652015-08-30 16:55:31 -0600889 .id = UCLASS_CLK,
890 .of_match = rk3288_clk_ids,
891 .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv),
Simon Glass2d143bd2016-07-04 11:58:29 -0600892 .platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat),
Simon Glass99c15652015-08-30 16:55:31 -0600893 .ops = &rk3288_clk_ops,
894 .bind = rk3288_clk_bind,
Simon Glass08fd82c2016-07-04 11:58:28 -0600895 .ofdata_to_platdata = rk3288_clk_ofdata_to_platdata,
Simon Glass99c15652015-08-30 16:55:31 -0600896 .probe = rk3288_clk_probe,
897};