blob: 299c147298c35120f9b122ef780e61ef8f18c31b [file] [log] [blame]
Chris Packham060c85d2018-05-08 22:34:10 +12001// SPDX-License-Identifier: GPL-2.0
2/ {
3 mbus@f1000000 {
4 pciec: pcie@82000000 {
5 compatible = "marvell,kirkwood-pcie";
6 status = "disabled";
7 device_type = "pci";
8
9 #address-cells = <3>;
10 #size-cells = <2>;
11
12 bus-range = <0x00 0xff>;
13
14 ranges =
15 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
16 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
17 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
18
19 pcie0: pcie@1,0 {
20 device_type = "pci";
21 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
22 reg = <0x0800 0 0 0 0>;
23 #address-cells = <3>;
24 #size-cells = <2>;
25 #interrupt-cells = <1>;
26 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
27 0x81000000 0 0 0x81000000 0x1 0 1 0>;
28 bus-range = <0x00 0xff>;
29 interrupt-map-mask = <0 0 0 0>;
30 interrupt-map = <0 0 0 0 &intc 9>;
31 marvell,pcie-port = <0>;
32 marvell,pcie-lane = <0>;
33 clocks = <&gate_clk 2>;
34 status = "disabled";
35 };
36 };
37 };
38
39 ocp@f1000000 {
40 pinctrl: pin-controller@10000 {
41 compatible = "marvell,98dx4122-pinctrl";
42
43 };
44 };
45};
46
47&sata_phy0 {
48 status = "disabled";
49};
50
51&sata_phy1 {
52 status = "disabled";
53};