Heiko Schocher | b61cbbd | 2019-10-14 11:29:39 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * (C) Copyright 2019 |
| 4 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. |
| 5 | * |
| 6 | */ |
| 7 | #include <common.h> |
Simon Glass | cd93d62 | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 8 | #include <asm/bitops.h> |
Heiko Schocher | b61cbbd | 2019-10-14 11:29:39 +0200 | [diff] [blame] | 9 | #include <pci.h> |
| 10 | #include <dm.h> |
| 11 | #include <asm/fsl_law.h> |
| 12 | |
| 13 | struct mpc85xx_pci_priv { |
| 14 | void __iomem *cfg_addr; |
| 15 | void __iomem *cfg_data; |
| 16 | }; |
| 17 | |
Simon Glass | c4e72c4 | 2020-01-27 08:49:37 -0700 | [diff] [blame] | 18 | static int mpc85xx_pci_dm_read_config(const struct udevice *dev, pci_dev_t bdf, |
Heiko Schocher | b61cbbd | 2019-10-14 11:29:39 +0200 | [diff] [blame] | 19 | uint offset, ulong *value, |
| 20 | enum pci_size_t size) |
| 21 | { |
| 22 | struct mpc85xx_pci_priv *priv = dev_get_priv(dev); |
| 23 | u32 addr; |
| 24 | |
Pali Rohár | 247ffc6 | 2021-11-26 11:42:43 +0100 | [diff] [blame] | 25 | addr = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset); |
Heiko Schocher | b61cbbd | 2019-10-14 11:29:39 +0200 | [diff] [blame] | 26 | out_be32(priv->cfg_addr, addr); |
| 27 | sync(); |
| 28 | *value = pci_conv_32_to_size(in_le32(priv->cfg_data), offset, size); |
| 29 | |
| 30 | return 0; |
| 31 | } |
| 32 | |
| 33 | static int mpc85xx_pci_dm_write_config(struct udevice *dev, pci_dev_t bdf, |
| 34 | uint offset, ulong value, |
| 35 | enum pci_size_t size) |
| 36 | { |
| 37 | struct mpc85xx_pci_priv *priv = dev_get_priv(dev); |
| 38 | u32 addr; |
| 39 | |
Pali Rohár | 247ffc6 | 2021-11-26 11:42:43 +0100 | [diff] [blame] | 40 | addr = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset); |
Heiko Schocher | b61cbbd | 2019-10-14 11:29:39 +0200 | [diff] [blame] | 41 | out_be32(priv->cfg_addr, addr); |
| 42 | sync(); |
| 43 | out_le32(priv->cfg_data, pci_conv_size_to_32(0, value, offset, size)); |
| 44 | |
| 45 | return 0; |
| 46 | } |
| 47 | |
Bin Meng | 5a40f5c | 2021-02-25 17:22:40 +0800 | [diff] [blame] | 48 | #ifdef CONFIG_FSL_LAW |
Heiko Schocher | b61cbbd | 2019-10-14 11:29:39 +0200 | [diff] [blame] | 49 | static int |
| 50 | mpc85xx_pci_dm_setup_laws(struct pci_region *io, struct pci_region *mem, |
| 51 | struct pci_region *pre) |
| 52 | { |
| 53 | /* |
| 54 | * Unfortunately we have defines for this addresse, |
| 55 | * as we have to setup the TLB, and at this stage |
| 56 | * we have no access to DT ... may we check here |
| 57 | * if the value in the define is the same ? |
| 58 | */ |
| 59 | if (mem) |
| 60 | set_next_law(mem->phys_start, law_size_bits(mem->size), |
| 61 | LAW_TRGT_IF_PCI); |
| 62 | if (io) |
| 63 | set_next_law(io->phys_start, law_size_bits(io->size), |
| 64 | LAW_TRGT_IF_PCI); |
| 65 | if (pre) |
| 66 | set_next_law(pre->phys_start, law_size_bits(pre->size), |
| 67 | LAW_TRGT_IF_PCI); |
| 68 | |
| 69 | return 0; |
| 70 | } |
Bin Meng | 5a40f5c | 2021-02-25 17:22:40 +0800 | [diff] [blame] | 71 | #endif |
Heiko Schocher | b61cbbd | 2019-10-14 11:29:39 +0200 | [diff] [blame] | 72 | |
| 73 | static int mpc85xx_pci_dm_probe(struct udevice *dev) |
| 74 | { |
| 75 | struct mpc85xx_pci_priv *priv = dev_get_priv(dev); |
| 76 | struct pci_region *io; |
| 77 | struct pci_region *mem; |
| 78 | struct pci_region *pre; |
| 79 | int count; |
| 80 | ccsr_pcix_t *pcix; |
| 81 | |
| 82 | count = pci_get_regions(dev, &io, &mem, &pre); |
| 83 | if (count != 2) { |
| 84 | printf("%s: wrong count of regions %d only 2 allowed\n", |
| 85 | __func__, count); |
| 86 | return -EINVAL; |
| 87 | } |
| 88 | |
Bin Meng | 5a40f5c | 2021-02-25 17:22:40 +0800 | [diff] [blame] | 89 | #ifdef CONFIG_FSL_LAW |
Heiko Schocher | b61cbbd | 2019-10-14 11:29:39 +0200 | [diff] [blame] | 90 | mpc85xx_pci_dm_setup_laws(io, mem, pre); |
Bin Meng | 5a40f5c | 2021-02-25 17:22:40 +0800 | [diff] [blame] | 91 | #endif |
Heiko Schocher | b61cbbd | 2019-10-14 11:29:39 +0200 | [diff] [blame] | 92 | |
| 93 | pcix = priv->cfg_addr; |
| 94 | /* BAR 1: memory */ |
Bin Meng | 8461ee5 | 2021-02-25 17:22:42 +0800 | [diff] [blame] | 95 | out_be32(&pcix->potar1, mem->bus_start >> 12); |
| 96 | out_be32(&pcix->potear1, (u64)mem->bus_start >> 44); |
| 97 | out_be32(&pcix->powbar1, mem->phys_start >> 12); |
| 98 | out_be32(&pcix->powbear1, (u64)mem->phys_start >> 44); |
Heiko Schocher | b61cbbd | 2019-10-14 11:29:39 +0200 | [diff] [blame] | 99 | out_be32(&pcix->powar1, (POWAR_EN | POWAR_MEM_READ | |
| 100 | POWAR_MEM_WRITE | (__ilog2(mem->size) - 1))); |
| 101 | |
| 102 | /* BAR 1: IO */ |
Bin Meng | 8461ee5 | 2021-02-25 17:22:42 +0800 | [diff] [blame] | 103 | out_be32(&pcix->potar2, io->bus_start >> 12); |
| 104 | out_be32(&pcix->potear2, (u64)io->bus_start >> 44); |
| 105 | out_be32(&pcix->powbar2, io->phys_start >> 12); |
| 106 | out_be32(&pcix->powbear2, (u64)io->phys_start >> 44); |
Heiko Schocher | b61cbbd | 2019-10-14 11:29:39 +0200 | [diff] [blame] | 107 | out_be32(&pcix->powar2, (POWAR_EN | POWAR_IO_READ | |
| 108 | POWAR_IO_WRITE | (__ilog2(io->size) - 1))); |
| 109 | |
| 110 | out_be32(&pcix->pitar1, 0); |
| 111 | out_be32(&pcix->piwbar1, 0); |
| 112 | out_be32(&pcix->piwar1, (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL | |
| 113 | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G)); |
| 114 | |
| 115 | out_be32(&pcix->powar3, 0); |
| 116 | out_be32(&pcix->powar4, 0); |
| 117 | out_be32(&pcix->piwar2, 0); |
| 118 | out_be32(&pcix->piwar3, 0); |
| 119 | |
| 120 | return 0; |
| 121 | } |
| 122 | |
| 123 | static int mpc85xx_pci_dm_remove(struct udevice *dev) |
| 124 | { |
| 125 | return 0; |
| 126 | } |
| 127 | |
Simon Glass | d1998a9 | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 128 | static int mpc85xx_pci_of_to_plat(struct udevice *dev) |
Heiko Schocher | b61cbbd | 2019-10-14 11:29:39 +0200 | [diff] [blame] | 129 | { |
| 130 | struct mpc85xx_pci_priv *priv = dev_get_priv(dev); |
| 131 | fdt_addr_t addr; |
| 132 | |
| 133 | addr = devfdt_get_addr_index(dev, 0); |
| 134 | if (addr == FDT_ADDR_T_NONE) |
| 135 | return -EINVAL; |
Bin Meng | 03ff970 | 2021-02-25 17:22:41 +0800 | [diff] [blame] | 136 | priv->cfg_addr = (void __iomem *)map_physmem(addr, 0, MAP_NOCACHE); |
| 137 | priv->cfg_data = (void __iomem *)((ulong)priv->cfg_addr + 4); |
Heiko Schocher | b61cbbd | 2019-10-14 11:29:39 +0200 | [diff] [blame] | 138 | |
| 139 | return 0; |
| 140 | } |
| 141 | |
| 142 | static const struct dm_pci_ops mpc85xx_pci_ops = { |
| 143 | .read_config = mpc85xx_pci_dm_read_config, |
| 144 | .write_config = mpc85xx_pci_dm_write_config, |
| 145 | }; |
| 146 | |
| 147 | static const struct udevice_id mpc85xx_pci_ids[] = { |
| 148 | { .compatible = "fsl,mpc8540-pci" }, |
| 149 | { } |
| 150 | }; |
| 151 | |
| 152 | U_BOOT_DRIVER(mpc85xx_pci) = { |
| 153 | .name = "mpc85xx_pci", |
| 154 | .id = UCLASS_PCI, |
| 155 | .of_match = mpc85xx_pci_ids, |
| 156 | .ops = &mpc85xx_pci_ops, |
| 157 | .probe = mpc85xx_pci_dm_probe, |
| 158 | .remove = mpc85xx_pci_dm_remove, |
Simon Glass | d1998a9 | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 159 | .of_to_plat = mpc85xx_pci_of_to_plat, |
Simon Glass | 41575d8 | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 160 | .priv_auto = sizeof(struct mpc85xx_pci_priv), |
Heiko Schocher | b61cbbd | 2019-10-14 11:29:39 +0200 | [diff] [blame] | 161 | }; |