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Ian Campbellcba69ee2014-05-05 11:52:26 +01001/*
2 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
3 *
4 * (C) Copyright 2007-2011
5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6 * Tom Cubie <tangliang@allwinnertech.com>
7 *
8 * Some init for sunxi platform.
9 *
10 * SPDX-License-Identifier: GPL-2.0+
11 */
12
13#include <common.h>
Daniel Kochmańskia1514032015-05-29 16:55:42 +020014#include <mmc.h>
Hans de Goede66203772014-06-13 22:55:49 +020015#include <i2c.h>
Ian Campbellcba69ee2014-05-05 11:52:26 +010016#include <serial.h>
17#ifdef CONFIG_SPL_BUILD
18#include <spl.h>
19#endif
20#include <asm/gpio.h>
21#include <asm/io.h>
22#include <asm/arch/clock.h>
23#include <asm/arch/gpio.h>
Bernhard Nortmannaf654d12015-09-17 18:52:52 +020024#include <asm/arch/spl.h>
Ian Campbellcba69ee2014-05-05 11:52:26 +010025#include <asm/arch/sys_proto.h>
26#include <asm/arch/timer.h>
Chen-Yu Tsai92369842015-08-25 10:49:19 +080027#include <asm/arch/tzpc.h>
Daniel Kochmańskia1514032015-05-29 16:55:42 +020028#include <asm/arch/mmc.h>
Ian Campbellcba69ee2014-05-05 11:52:26 +010029
Ian Campbell799aff32014-07-06 20:03:20 +010030#include <linux/compiler.h>
31
Simon Glass942cb0b2015-02-07 10:47:30 -070032struct fel_stash {
33 uint32_t sp;
34 uint32_t lr;
Siarhei Siamashka840fe952015-02-16 10:23:59 +020035 uint32_t cpsr;
36 uint32_t sctlr;
37 uint32_t vbar;
38 uint32_t cr;
Simon Glass942cb0b2015-02-07 10:47:30 -070039};
40
41struct fel_stash fel_stash __attribute__((section(".data")));
42
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +020043#ifdef CONFIG_MACH_SUN50I
44#include <asm/armv8/mmu.h>
45
46static struct mm_region sunxi_mem_map[] = {
47 {
48 /* SRAM, MMIO regions */
York Suncd4b0c52016-06-24 16:46:22 -070049 .virt = 0x0UL,
50 .phys = 0x0UL,
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +020051 .size = 0x40000000UL,
52 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
53 PTE_BLOCK_NON_SHARE
54 }, {
55 /* RAM */
York Suncd4b0c52016-06-24 16:46:22 -070056 .virt = 0x40000000UL,
57 .phys = 0x40000000UL,
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +020058 .size = 0x80000000UL,
59 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
60 PTE_BLOCK_INNER_SHARE
61 }, {
62 /* List terminator */
63 0,
64 }
65};
66struct mm_region *mem_map = sunxi_mem_map;
67#endif
68
Simon Glassf6309742014-12-23 12:04:52 -070069static int gpio_init(void)
Ian Campbellcba69ee2014-05-05 11:52:26 +010070{
Chen-Yu Tsaiff2b47f2014-10-22 16:47:42 +080071#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
Ian Campbelled41e622014-10-24 21:20:47 +010072#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
Chen-Yu Tsaiff2b47f2014-10-22 16:47:42 +080073 /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
74 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
75 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
76#endif
Paul Kocialkowski487b3272015-03-22 18:12:22 +010077#if defined(CONFIG_MACH_SUN8I)
Chen-Yu Tsai6ad8c742015-06-23 19:57:23 +080078 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
79 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
Paul Kocialkowski487b3272015-03-22 18:12:22 +010080#else
Chen-Yu Tsai6ad8c742015-06-23 19:57:23 +080081 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
82 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
Paul Kocialkowski487b3272015-03-22 18:12:22 +010083#endif
Chen-Yu Tsaiff2b47f2014-10-22 16:47:42 +080084 sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
Ian Campbelled41e622014-10-24 21:20:47 +010085#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
Paul Kocialkowski487b3272015-03-22 18:12:22 +010086 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
87 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
Chen-Yu Tsaiea520942014-10-03 20:16:21 +080088 sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
Ian Campbelled41e622014-10-24 21:20:47 +010089#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
Paul Kocialkowski487b3272015-03-22 18:12:22 +010090 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
91 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
Chen-Yu Tsaiea520942014-10-03 20:16:21 +080092 sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
Ian Campbelled41e622014-10-24 21:20:47 +010093#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
Paul Kocialkowski487b3272015-03-22 18:12:22 +010094 sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
95 sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
Maxime Ripard77115392014-10-03 20:16:28 +080096 sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
Chen-Yu Tsaie5068892015-06-23 19:57:25 +080097#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
98 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
99 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
100 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
Jens Kuske1c27b7d2015-11-17 15:12:58 +0100101#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_H3)
102 sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
103 sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
104 sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200105#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I)
106 sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
107 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
108 sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
vishnupatekard5a33572015-11-29 01:07:20 +0800109#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
110 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
111 sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
112 sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
Hans de Goede1871a8c2015-01-13 19:25:06 +0100113#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
114 sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
115 sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
116 sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
Ian Campbelled41e622014-10-24 21:20:47 +0100117#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
Paul Kocialkowski487b3272015-03-22 18:12:22 +0100118 sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
119 sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
Chen-Yu Tsaiea520942014-10-03 20:16:21 +0800120 sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
Laurent Itti5cd83b112015-05-05 17:02:00 -0700121#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
122 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
123 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
124 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
Ian Campbelled41e622014-10-24 21:20:47 +0100125#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
Paul Kocialkowski487b3272015-03-22 18:12:22 +0100126 sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
127 sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
Chen-Yu Tsaic757a502014-10-22 16:47:47 +0800128 sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
Hans de Goedef84269c2014-06-09 11:36:58 +0200129#else
130#error Unsupported console port number. Please fix pin mux settings in board.c
131#endif
Ian Campbellcba69ee2014-05-05 11:52:26 +0100132
133 return 0;
134}
135
Simon Glass97d9df02016-09-24 18:20:12 -0600136#ifdef CONFIG_SPL_BUILD
Simon Glass2a2ee2a2016-09-24 18:20:13 -0600137static int spl_board_load_image(struct spl_image_info *spl_image,
138 struct spl_boot_device *bootdev)
Simon Glass942cb0b2015-02-07 10:47:30 -0700139{
140 debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
141 return_to_fel(fel_stash.sp, fel_stash.lr);
Nikita Kiryanov36afd452015-11-08 17:11:49 +0200142
143 return 0;
Simon Glass942cb0b2015-02-07 10:47:30 -0700144}
Simon Glass97d9df02016-09-24 18:20:12 -0600145SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_BOARD, spl_board_load_image);
146#endif
Simon Glass942cb0b2015-02-07 10:47:30 -0700147
Hans de Goedeb56f6e22015-01-21 16:24:05 +0100148void s_init(void)
Simon Glassf6309742014-12-23 12:04:52 -0700149{
Hans de Goede583fede2016-03-04 10:57:34 +0100150 /*
151 * Undocumented magic taken from boot0, without this DRAM
152 * access gets messed up (seems cache related).
153 * The boot0 sources describe this as: "config ema for cache sram"
154 */
155#if defined CONFIG_MACH_SUN6I
Simon Glassf6309742014-12-23 12:04:52 -0700156 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
Hans de Goede5f8afd72016-03-24 22:37:08 +0100157#elif defined CONFIG_MACH_SUN8I
158 __maybe_unused uint version;
Hans de Goede583fede2016-03-04 10:57:34 +0100159
160 /* Unlock sram version info reg, read it, relock */
161 setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
Hans de Goede5f8afd72016-03-24 22:37:08 +0100162 version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
Hans de Goede583fede2016-03-04 10:57:34 +0100163 clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
164
Hans de Goede5f8afd72016-03-24 22:37:08 +0100165 /*
166 * Ideally this would be a switch case, but we do not know exactly
167 * which versions there are and which version needs which settings,
168 * so reproduce the per SoC code from the BSP.
169 */
170#if defined CONFIG_MACH_SUN8I_A23
171 if (version == 0x1650)
Hans de Goede583fede2016-03-04 10:57:34 +0100172 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
173 else /* 0x1661 ? */
174 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
Hans de Goede5f8afd72016-03-24 22:37:08 +0100175#elif defined CONFIG_MACH_SUN8I_A33
176 if (version != 0x1667)
177 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
178#endif
179 /* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */
180 /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
Simon Glassf6309742014-12-23 12:04:52 -0700181#endif
Hans de Goede583fede2016-03-04 10:57:34 +0100182
Hans de Goede92bcc6c2015-04-06 20:16:36 +0200183#if defined CONFIG_MACH_SUN6I || \
184 defined CONFIG_MACH_SUN7I || \
Philipp Tomsichf28bad12016-10-28 18:21:30 +0800185 defined CONFIG_MACH_SUN8I || \
186 defined CONFIG_MACH_SUN9I
Simon Glassf6309742014-12-23 12:04:52 -0700187 /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
188 asm volatile(
189 "mrc p15, 0, r0, c1, c0, 1\n"
190 "orr r0, r0, #1 << 6\n"
191 "mcr p15, 0, r0, c1, c0, 1\n");
192#endif
Chen-Yu Tsai58236642016-01-06 15:13:06 +0800193#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
194 /* Enable non-secure access to some peripherals */
Chen-Yu Tsai92369842015-08-25 10:49:19 +0800195 tzpc_init();
196#endif
Simon Glassf6309742014-12-23 12:04:52 -0700197
198 clock_init();
199 timer_init();
200 gpio_init();
201 i2c_init_board();
Hans de Goedefc8991c2016-03-17 13:53:03 +0100202 eth_init_board();
Hans de Goedeb56f6e22015-01-21 16:24:05 +0100203}
Simon Glassf6309742014-12-23 12:04:52 -0700204
Hans de Goedeb56f6e22015-01-21 16:24:05 +0100205#ifdef CONFIG_SPL_BUILD
Daniel Kochmańskia1514032015-05-29 16:55:42 +0200206DECLARE_GLOBAL_DATA_PTR;
207
Hans de Goedeb56f6e22015-01-21 16:24:05 +0100208/* The sunxi internal brom will try to loader external bootloader
209 * from mmc0, nand flash, mmc2.
Hans de Goedeb56f6e22015-01-21 16:24:05 +0100210 */
211u32 spl_boot_device(void)
212{
Hans de Goedeef36d9a2016-07-09 15:31:47 +0200213 int boot_source;
214
Siarhei Siamashka840fe952015-02-16 10:23:59 +0200215 /*
Daniel Kochmańskia1514032015-05-29 16:55:42 +0200216 * When booting from the SD card or NAND memory, the "eGON.BT0"
217 * signature is expected to be found in memory at the address 0x0004
218 * (see the "mksunxiboot" tool, which generates this header).
Siarhei Siamashka840fe952015-02-16 10:23:59 +0200219 *
220 * When booting in the FEL mode over USB, this signature is patched in
221 * memory and replaced with something else by the 'fel' tool. This other
222 * signature is selected in such a way, that it can't be present in a
223 * valid bootable SD card image (because the BROM would refuse to
224 * execute the SPL in this case).
225 *
Daniel Kochmańskia1514032015-05-29 16:55:42 +0200226 * This checks for the signature and if it is not found returns to
227 * the FEL code in the BROM to wait and receive the main u-boot
228 * binary over USB. If it is found, it determines where SPL was
229 * read from.
Siarhei Siamashka840fe952015-02-16 10:23:59 +0200230 */
Bernhard Nortmannaf654d12015-09-17 18:52:52 +0200231 if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
Simon Glass942cb0b2015-02-07 10:47:30 -0700232 return BOOT_DEVICE_BOARD;
Daniel Kochmańskia1514032015-05-29 16:55:42 +0200233
Hans de Goedeef36d9a2016-07-09 15:31:47 +0200234 boot_source = readb(SPL_ADDR + 0x28);
235 switch (boot_source) {
236 case SUNXI_BOOTED_FROM_MMC0:
Daniel Kochmańskia1514032015-05-29 16:55:42 +0200237 return BOOT_DEVICE_MMC1;
Hans de Goedeef36d9a2016-07-09 15:31:47 +0200238 case SUNXI_BOOTED_FROM_NAND:
Daniel Kochmańskia1514032015-05-29 16:55:42 +0200239 return BOOT_DEVICE_NAND;
Hans de Goedeef36d9a2016-07-09 15:31:47 +0200240 case SUNXI_BOOTED_FROM_MMC2:
241 return BOOT_DEVICE_MMC2;
242 case SUNXI_BOOTED_FROM_SPI:
243 return BOOT_DEVICE_SPI;
Daniel Kochmańskia1514032015-05-29 16:55:42 +0200244 }
245
Hans de Goedeef36d9a2016-07-09 15:31:47 +0200246 panic("Unknown boot source %d\n", boot_source);
Daniel Kochmańskia1514032015-05-29 16:55:42 +0200247 return -1; /* Never reached */
Hans de Goedeb56f6e22015-01-21 16:24:05 +0100248}
249
Bernhard Nortmann28d68042016-04-03 13:58:00 +0200250/*
251 * Properly announce BOOT_DEVICE_BOARD as "FEL".
252 * Overrides weak function from common/spl/spl.c
253 */
254void spl_board_announce_boot_device(void)
255{
256 printf("FEL");
257}
258
Hans de Goedeb56f6e22015-01-21 16:24:05 +0100259/* No confirmation data available in SPL yet. Hardcode bootmode */
Marek Vasut2b1cdaf2016-05-14 23:42:07 +0200260u32 spl_boot_mode(const u32 boot_device)
Hans de Goedeb56f6e22015-01-21 16:24:05 +0100261{
262 return MMCSD_MODE_RAW;
263}
264
265void board_init_f(ulong dummy)
266{
Hans de Goede6d0bdfd2015-09-13 12:31:24 +0200267 spl_init();
Simon Glassf6309742014-12-23 12:04:52 -0700268 preloader_console_init();
269
270#ifdef CONFIG_SPL_I2C_SUPPORT
271 /* Needed early by sunxi_board_init if PMU is enabled */
272 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
273#endif
274 sunxi_board_init();
Simon Glassf6309742014-12-23 12:04:52 -0700275}
276#endif
277
Ian Campbellcba69ee2014-05-05 11:52:26 +0100278void reset_cpu(ulong addr)
279{
Hans de Goede44d8ae52015-04-06 20:33:34 +0200280#ifdef CONFIG_SUNXI_GEN_SUN4I
Hans de Goedec7e79de2014-06-09 11:36:56 +0200281 static const struct sunxi_wdog *wdog =
282 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
283
284 /* Set the watchdog for its shortest interval (.5s) and wait */
285 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
286 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
Hans de Goedeae5de5a2014-06-13 22:55:52 +0200287
288 while (1) {
289 /* sun5i sometimes gets stuck without this */
290 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
291 }
Hans de Goede44d8ae52015-04-06 20:33:34 +0200292#endif
293#ifdef CONFIG_SUNXI_GEN_SUN6I
Chen-Yu Tsai78c396a2014-10-04 20:37:28 +0800294 static const struct sunxi_wdog *wdog =
295 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
296
297 /* Set the watchdog for its shortest interval (.5s) and wait */
298 writel(WDT_CFG_RESET, &wdog->cfg);
299 writel(WDT_MODE_EN, &wdog->mode);
300 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
Hans de Goedefc175432015-06-14 16:53:15 +0200301 while (1) { }
Chen-Yu Tsai78c396a2014-10-04 20:37:28 +0800302#endif
Ian Campbellcba69ee2014-05-05 11:52:26 +0100303}
304
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200305#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
Ian Campbellcba69ee2014-05-05 11:52:26 +0100306void enable_caches(void)
307{
308 /* Enable D-cache. I-cache is already enabled in start.S */
309 dcache_enable();
310}
311#endif