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wdenk0f8c9762002-08-19 11:57:05 +00001 /*
2 * A collection of structures, addresses, and values associated with
3 * the Motorola 860T FADS board. Copied from the MBX stuff.
4 * Magnus Damm added defines for 8xxrom and extended bd_info.
5 * Helmut Buchsbaum added bitvalues for BCSRx
6 *
7 * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
8 */
9
10/*
11 * 1999-nov-26: The FADS is using the following physical memorymap:
12 *
13 * ff020000 -> ff02ffff : pcmcia
14 * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxrom
15 * ff000000 -> ff00ffff : IMAP internal in the cpu
16 * fe000000 -> ffnnnnnn : flash connected to CS0, setup by 8xxrom
17 * 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom
18 */
19
20/* ------------------------------------------------------------------------- */
21
22/*
23 * board/config.h - configuration options, board specific
24 */
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29/*
30 * High Level Configuration Options
31 * (easy to change)
32 */
wdenk0f8c9762002-08-19 11:57:05 +000033#define CONFIG_MPC850 1
34#define CONFIG_MPC850SAR 1
35#define CONFIG_FADS 1
36
37#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
38#undef CONFIG_8xx_CONS_SMC2
39#undef CONFIG_8xx_CONS_NONE
40#define CONFIG_BAUDRATE 9600
41
42#if 0
43#define MPC8XX_FACT 10 /* Multiply by 10 */
44#define MPC8XX_XIN 50000000 /* 50 MHz in */
45#else
46#define MPC8XX_FACT 12 /* Multiply by 12 */
47#define MPC8XX_XIN 4000000 /* 4 MHz in */
48#endif
49#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
50
51#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
52
53#if 1
54#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
55#else
56#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
57#endif
58
59#define CONFIG_BOOTCOMMAND "bootm 02880000" /* autoboot command */
60#define CONFIG_BOOTARGS " "
61
62#undef CONFIG_WATCHDOG /* watchdog disabled */
63
Jon Loeliger60a08762007-07-07 21:04:26 -050064
65/*
Jon Loeliger11799432007-07-10 09:02:57 -050066 * BOOTP options
67 */
68#define CONFIG_BOOTP_BOOTFILESIZE
69#define CONFIG_BOOTP_BOOTPATH
70#define CONFIG_BOOTP_GATEWAY
71#define CONFIG_BOOTP_HOSTNAME
72
73
74/*
Jon Loeliger60a08762007-07-07 21:04:26 -050075 * Command line configuration.
76 */
77#include <config_cmd_default.h>
78
wdenk0f8c9762002-08-19 11:57:05 +000079
80/*
81 * Miscellaneous configurable options
82 */
83#undef CFG_LONGHELP /* undef to save memory */
84#define CFG_PROMPT ":>" /* Monitor Command Prompt */
Jon Loeliger60a08762007-07-07 21:04:26 -050085#if defined(CONFIG_CMD_KGDB)
wdenk0f8c9762002-08-19 11:57:05 +000086#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
87#else
88#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
89#endif
90#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
91#define CFG_MAXARGS 16 /* max number of command args */
92#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
93
94#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
95#define CFG_MEMTEST_END 0x00800000 /* 0 ... 8 MB in DRAM */
96
97#define CFG_LOAD_ADDR 0x00100000 /* default load address */
98
99#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
100
101#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
102
103/*
104 * Low Level Configuration Settings
105 * (address mappings, register initial values, etc.)
106 * You should know what you are doing if you make changes here.
107 */
108/*-----------------------------------------------------------------------
109 * Internal Memory Mapped Register
110 */
111#define CFG_IMMR 0xFF000000
112#define CFG_IMMR_SIZE ((uint)(64 * 1024))
113
114/*-----------------------------------------------------------------------
115 * Definitions for initial stack pointer and data area (in DPRAM)
116 */
117#define CFG_INIT_RAM_ADDR CFG_IMMR
118#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
119#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
120#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
121#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
122
123/*-----------------------------------------------------------------------
124 * Start addresses for the final memory configuration
125 * (Set up by the startup code)
126 * Please note that CFG_SDRAM_BASE _must_ start at 0
127 * Also NOTE that it doesn't mean SDRAM - it means MEMORY.
128 */
129#define CFG_SDRAM_BASE 0x00000000
wdenk2535d602003-07-17 23:16:40 +0000130#define CFG_SDRAM_SIZE (4<<20) /* standard FADS has 4M */
wdenk0f8c9762002-08-19 11:57:05 +0000131#define CFG_FLASH_BASE 0x02800000
132#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
133#if 0
134#define CFG_MONITOR_LEN (256 << 10) /* Reserve 128 kB for Monitor */
135#else
136#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
137#endif
138#define CFG_MONITOR_BASE CFG_FLASH_BASE
139#define CFG_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */
140
141/*
142 * For booting Linux, the board info and command line data
143 * have to be in the first 8 MB of memory, since this is
144 * the maximum mapped by the Linux kernel during initialization.
145 */
146#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
147/*-----------------------------------------------------------------------
148 * FLASH organization
149 */
150#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
151#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
152
153#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
154#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
155
156#define CFG_ENV_IS_IN_FLASH 1
157#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
158#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
159
160/*-----------------------------------------------------------------------
161 * Cache Configuration
162 */
163#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger60a08762007-07-07 21:04:26 -0500164#if defined(CONFIG_CMD_KGDB)
wdenk0f8c9762002-08-19 11:57:05 +0000165#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
166#endif
167
168/*-----------------------------------------------------------------------
169 * SYPCR - System Protection Control 11-9
170 * SYPCR can only be written once after reset!
171 *-----------------------------------------------------------------------
172 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
173 */
174#if defined(CONFIG_WATCHDOG)
175#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
176 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
177#else
178#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
179#endif
180
181/*-----------------------------------------------------------------------
182 * SIUMCR - SIU Module Configuration 11-6
183 *-----------------------------------------------------------------------
184 * PCMCIA config., multi-function pin tri-state
185 */
186#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
187
188/*-----------------------------------------------------------------------
189 * TBSCR - Time Base Status and Control 11-26
190 *-----------------------------------------------------------------------
191 * Clear Reference Interrupt Status, Timebase freezing enabled
192 */
193#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
194
195/*-----------------------------------------------------------------------
196 * PISCR - Periodic Interrupt Status and Control 11-31
197 *-----------------------------------------------------------------------
198 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
199 */
200#define CFG_PISCR (PISCR_PS | PISCR_PITF)
201
202/*-----------------------------------------------------------------------
203 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
204 *-----------------------------------------------------------------------
205 * Reset PLL lock status sticky bit, timer expired status bit and timer *
206 * interrupt status bit - leave PLL multiplication factor unchanged !
207 */
208#define CFG_PLPRCR (((MPC8XX_FACT-1) << 20) | \
209 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
210
211/*-----------------------------------------------------------------------
212 * SCCR - System Clock and reset Control Register 15-27
213 *-----------------------------------------------------------------------
214 * Set clock output, timebase and RTC source and divider,
215 * power management and some other internal clocks
216 */
217#define SCCR_MASK SCCR_EBDF11
218#define CFG_SCCR (SCCR_TBS | \
219 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
220 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
221 SCCR_DFALCD00)
222
223 /*-----------------------------------------------------------------------
224 *
225 *-----------------------------------------------------------------------
226 *
227 */
228#define CFG_DER 0
229
230/* Because of the way the 860 starts up and assigns CS0 the
231* entire address space, we have to set the memory controller
232* differently. Normally, you write the option register
233* first, and then enable the chip select by writing the
234* base register. For CS0, you must write the base register
235* first, followed by the option register.
236*/
237
238/*
239 * Init Memory Controller:
240 *
241 * BR0/1 and OR0/1 (FLASH)
242 */
243/* the other CS:s are determined by looking at parameters in BCSRx */
244
245
246#define BCSR_ADDR ((uint) 0x02100000)
247#define BCSR_SIZE ((uint)(64 * 1024))
248
249#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */
250#define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */
251
252#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
253#define CFG_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */
254
255/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
256#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
257
258#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
259#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/
260#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
261
262/* BCSRx - Board Control and Status Registers */
263#define CFG_OR1_REMAP CFG_OR0_REMAP
264#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */
265#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V )
266
267
268/*
269 * Memory Periodic Timer Prescaler
270 */
271
272/* periodic timer for refresh */
273#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
274
275/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
276#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
277#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
278
279/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
280#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
281#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
282
283/*
284 * MAMR settings for SDRAM
285 */
286
287/* 8 column SDRAM */
288#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
289 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
290 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
291/* 9 column SDRAM */
292#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
293 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
294 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
295
296#define CFG_MAMR 0x13a01114
297/*
298 * Internal Definitions
299 *
300 * Boot Flags
301 */
302#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
303#define BOOTFLAG_WARM 0x02 /* Software reboot */
304
305
306/* values according to the manual */
307
308
309#define PCMCIA_MEM_ADDR ((uint)0xff020000)
310#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
311
312#define BCSR0 ((uint) (BCSR_ADDR + 00))
313#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
314#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
315#define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
316#define BCSR4 ((uint) (BCSR_ADDR + 0x10))
317
318/* FADS bitvalues by Helmut Buchsbaum
319 * see MPC8xxADS User's Manual for a proper description
320 * of the following structures
321 */
322
323#define BCSR0_ERB ((uint)0x80000000)
324#define BCSR0_IP ((uint)0x40000000)
325#define BCSR0_BDIS ((uint)0x10000000)
326#define BCSR0_BPS_MASK ((uint)0x0C000000)
327#define BCSR0_ISB_MASK ((uint)0x01800000)
328#define BCSR0_DBGC_MASK ((uint)0x00600000)
329#define BCSR0_DBPC_MASK ((uint)0x00180000)
330#define BCSR0_EBDF_MASK ((uint)0x00060000)
331
332#define BCSR1_FLASH_EN ((uint)0x80000000)
333#define BCSR1_DRAM_EN ((uint)0x40000000)
334#define BCSR1_ETHEN ((uint)0x20000000)
335#define BCSR1_IRDEN ((uint)0x10000000)
336#define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
337#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
338#define BCSR1_BCSR_EN ((uint)0x02000000)
339#define BCSR1_RS232EN_1 ((uint)0x01000000)
340#define BCSR1_PCCEN ((uint)0x00800000)
341#define BCSR1_PCCVCC0 ((uint)0x00400000)
342#define BCSR1_PCCVPP_MASK ((uint)0x00300000)
343#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
344#define BCSR1_RS232EN_2 ((uint)0x00040000)
345#define BCSR1_SDRAM_EN ((uint)0x00020000)
346#define BCSR1_PCCVCC1 ((uint)0x00010000)
347
348#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
wdenkb54d32b2004-06-10 21:34:36 +0000349#define BCSR2_FLASH_PD_SHIFT 28
wdenk0f8c9762002-08-19 11:57:05 +0000350#define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
wdenkb54d32b2004-06-10 21:34:36 +0000351#define BCSR2_DRAM_PD_SHIFT 23
wdenk0f8c9762002-08-19 11:57:05 +0000352#define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
353#define BCSR2_DBREVNR_MASK ((uint)0x00030000)
354
355#define BCSR3_DBID_MASK ((ushort)0x3800)
356#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
357#define BCSR3_BREVNR0 ((ushort)0x0080)
358#define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
359#define BCSR3_BREVN1 ((ushort)0x0008)
360#define BCSR3_BREVN2_MASK ((ushort)0x0003)
361
362#define BCSR4_ETHLOOP ((uint)0x80000000)
363#define BCSR4_TFPLDL ((uint)0x40000000)
364#define BCSR4_TPSQEL ((uint)0x20000000)
365#define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
366#ifdef CONFIG_MPC823
367#define BCSR4_USB_EN ((uint)0x08000000)
368#endif /* CONFIG_MPC823 */
369#ifdef CONFIG_MPC860SAR
370#define BCSR4_UTOPIA_EN ((uint)0x08000000)
371#endif /* CONFIG_MPC860SAR */
372#ifdef CONFIG_MPC860T
373#define BCSR4_FETH_EN ((uint)0x08000000)
374#endif /* CONFIG_MPC860T */
375#ifdef CONFIG_MPC823
376#define BCSR4_USB_SPEED ((uint)0x04000000)
377#endif /* CONFIG_MPC823 */
378#ifdef CONFIG_MPC860T
379#define BCSR4_FETHCFG0 ((uint)0x04000000)
380#endif /* CONFIG_MPC860T */
381#ifdef CONFIG_MPC823
382#define BCSR4_VCCO ((uint)0x02000000)
383#endif /* CONFIG_MPC823 */
384#ifdef CONFIG_MPC860T
385#define BCSR4_FETHFDE ((uint)0x02000000)
386#endif /* CONFIG_MPC860T */
387#ifdef CONFIG_MPC823
388#define BCSR4_VIDEO_ON ((uint)0x00800000)
389#endif /* CONFIG_MPC823 */
390#ifdef CONFIG_MPC823
391#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
392#endif /* CONFIG_MPC823 */
393#ifdef CONFIG_MPC860T
394#define BCSR4_FETHCFG1 ((uint)0x00400000)
395#endif /* CONFIG_MPC860T */
396#ifdef CONFIG_MPC823
397#define BCSR4_VIDEO_RST ((uint)0x00200000)
398#endif /* CONFIG_MPC823 */
399#ifdef CONFIG_MPC860T
400#define BCSR4_FETHRST ((uint)0x00200000)
401#endif /* CONFIG_MPC860T */
402#define BCSR4_MODEM_EN ((uint)0x00100000)
403#define BCSR4_DATA_VOICE ((uint)0x00080000)
404
405#define CONFIG_DRAM_50MHZ 1
406#define CONFIG_SDRAM_50MHZ
407
wdenk0f8c9762002-08-19 11:57:05 +0000408/* We don't use the 8259.
409*/
410#define NR_8259_INTS 0
411
412/* Machine type
413*/
414#define _MACH_8xx (_MACH_fads)
415
416#define CONFIG_DISK_SPINUP_TIME 1000000
417
418
419/* PCMCIA configuration */
420
421#define PCMCIA_MAX_SLOTS 2
422
423#ifdef CONFIG_MPC860
424#define PCMCIA_SLOT_A 1
425#endif
426
wdenk180d3f72004-01-04 16:28:35 +0000427#define CFG_DAUGHTERBOARD
428
wdenk0f8c9762002-08-19 11:57:05 +0000429#endif /* __CONFIG_H */