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Stefan Roeseb79316f2005-08-15 12:31:23 +02001/*
2 * (C) Copyright 2004 Sandburst Corporation
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/************************************************************************
24 * KAMINOREFDES.h - configuration for the Sandburst Kamino Reference
Wolfgang Denk3d078ce2005-08-15 16:03:56 +020025 * design.
Stefan Roeseb79316f2005-08-15 12:31:23 +020026 ***********************************************************************/
27
28/*
29 * $Id: KAREF.h,v 1.6 2005/06/03 15:05:25 tsawyer Exp $
30 *
31 */
32
33#ifndef __CONFIG_H
34#define __CONFIG_H
35
36/*-----------------------------------------------------------------------
37 * High Level Configuration Options
38 *----------------------------------------------------------------------*/
Wolfgang Denk3d078ce2005-08-15 16:03:56 +020039#define CONFIG_KAREF 1 /* Board is Kamino Ref Variant */
40#define CONFIG_440GX 1 /* Specifc GX support */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +020041#define CONFIG_440 1 /* ... PPC440 family */
Wolfgang Denk3d078ce2005-08-15 16:03:56 +020042#define CONFIG_4xx 1 /* ... PPC4xx family */
Stefan Roeseb79316f2005-08-15 12:31:23 +020043#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
Wolfgang Denk3d078ce2005-08-15 16:03:56 +020044#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
45#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */
Stefan Roeseb79316f2005-08-15 12:31:23 +020046#undef CFG_DRAM_TEST /* Disable-takes long time!*/
Wolfgang Denk3d078ce2005-08-15 16:03:56 +020047#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
Stefan Roeseb79316f2005-08-15 12:31:23 +020048
49#define CONFIG_VERY_BIG_RAM 1
50#define CONFIG_VERSION_VARIABLE
51
52#define CONFIG_IDENT_STRING " Sandburst Kamino Reference Design"
53
54/*-----------------------------------------------------------------------
55 * Base addresses -- Note these are effective addresses where the
56 * actual resources get mapped (not physical addresses)
57 *----------------------------------------------------------------------*/
Wolfgang Denk3d078ce2005-08-15 16:03:56 +020058#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
59#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */
60#define CFG_MONITOR_BASE 0xfff80000 /* start of monitor */
61#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
62#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
63#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
64#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
Stefan Roeseb79316f2005-08-15 12:31:23 +020065
66#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
67#define CFG_KAREF_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08200000)
68#define CFG_OFEM_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08400000)
69#define CFG_BME32_BASE (CFG_PERIPHERAL_BASE + 0x08500000)
70#define CFG_GPIO_BASE (CFG_PERIPHERAL_BASE + 0x00000700)
71
72/* Here for completeness */
Wolfgang Denk3d078ce2005-08-15 16:03:56 +020073#define CFG_OFEMAC_BASE (CFG_PERIPHERAL_BASE + 0x08600000)
Stefan Roeseb79316f2005-08-15 12:31:23 +020074
75/*-----------------------------------------------------------------------
76 * Initial RAM & stack pointer (placed in internal SRAM)
77 *----------------------------------------------------------------------*/
78#define CFG_TEMP_STACK_OCM 1
79#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
Wolfgang Denk3d078ce2005-08-15 16:03:56 +020080#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
81#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
82#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
Stefan Roeseb79316f2005-08-15 12:31:23 +020083
84#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
85#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
86#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
87
Wolfgang Denk3d078ce2005-08-15 16:03:56 +020088#define CFG_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */
89#define CFG_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */
Stefan Roeseb79316f2005-08-15 12:31:23 +020090
91/*-----------------------------------------------------------------------
92 * Serial Port
93 *----------------------------------------------------------------------*/
94#undef CONFIG_SERIAL_SOFTWARE_FIFO
95#define CONFIG_SERIAL_MULTI 1
96#define CONFIG_BAUDRATE 9600
97
98#define CFG_BAUDRATE_TABLE \
99 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
100
101/*-----------------------------------------------------------------------
102 * NVRAM/RTC
103 *
104 * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
105 * The DS1743 code assumes this condition (i.e. -- it assumes the base
106 * address for the RTC registers is:
107 *
108 * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
109 *
110 *----------------------------------------------------------------------*/
111#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200112#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200113
114/*-----------------------------------------------------------------------
115 * FLASH related
116 *----------------------------------------------------------------------*/
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200117#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
118#define CFG_MAX_FLASH_SECT 8 /* sectors per device */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200119
120#undef CFG_FLASH_CHECKSUM
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200121#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */
122#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200123
124/*-----------------------------------------------------------------------
125 * DDR SDRAM
126 *----------------------------------------------------------------------*/
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200127#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/
128#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200129
130/*-----------------------------------------------------------------------
131 * I2C
132 *----------------------------------------------------------------------*/
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200133#define CONFIG_HARD_I2C 1 /* I2C hardware support */
134#undef CONFIG_SOFT_I2C /* I2C !bit-banged */
135#define CFG_I2C_SPEED 400000 /* I2C speed 400kHz */
136#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
137#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
138#define CONFIG_I2C_BUS1 1 /* Include i2c bus 1 supp */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200139
140
141/*-----------------------------------------------------------------------
142 * Environment
143 *----------------------------------------------------------------------*/
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200144#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
145#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
146#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
147#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200148
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200149#define CFG_ENV_SIZE 0x1000 /* Size of Env vars */
150#define CFG_ENV_ADDR (CFG_NVRAM_BASE_ADDR)
Stefan Roeseb79316f2005-08-15 12:31:23 +0200151
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200152#define CONFIG_BOOTDELAY 5 /* 5 second autoboot */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200153
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200154#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */
155#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200156
157/*-----------------------------------------------------------------------
158 * Networking
159 *----------------------------------------------------------------------*/
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200160#define CONFIG_MII 1 /* MII PHY management */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200161#define CONFIG_NET_MULTI 1
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200162#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
163#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
164#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */
165#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200166#define CONFIG_HAS_ETH0
167#define CONFIG_HAS_ETH1
168#define CONFIG_HAS_ETH2
169#define CONFIG_HAS_ETH3
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200170#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200171#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */
172#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */
173#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200174#define CONFIG_PHY_RESET_DELAY 1000
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200175#define CONFIG_NETMASK 255.255.0.0
176#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */
177#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */
178#define CFG_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200179
180
Jon Loeliger348f2582007-07-08 13:46:18 -0500181/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500182 * BOOTP options
183 */
184#define CONFIG_BOOTP_BOOTFILESIZE
185#define CONFIG_BOOTP_BOOTPATH
186#define CONFIG_BOOTP_GATEWAY
187#define CONFIG_BOOTP_HOSTNAME
188
189
190/*
Jon Loeliger348f2582007-07-08 13:46:18 -0500191 * Command line configuration.
192 */
193#include <config_cmd_default.h>
194
195#define CONFIG_CMD_PCI
196#define CONFIG_CMD_IRQ
197#define CONFIG_CMD_I2C
198#define CONFIG_CMD_DHCP
199#define CONFIG_CMD_DATE
200#define CONFIG_CMD_BEDBUG
201#define CONFIG_CMD_PING
202#define CONFIG_CMD_DIAG
203#define CONFIG_CMD_MII
204#define CONFIG_CMD_NET
205#define CONFIG_CMD_ELF
206#define CONFIG_CMD_IDE
207#define CONFIG_CMD_FAT
208
Stefan Roeseb79316f2005-08-15 12:31:23 +0200209
210/* Include NetConsole support */
211#define CONFIG_NETCONSOLE
212
213/* Include auto complete with tabs */
214#define CONFIG_AUTO_COMPLETE 1
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200215#define CFG_ALT_MEMTEST 1 /* use real memory test */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200216
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200217#define CFG_LONGHELP /* undef to save memory */
218#define CFG_PROMPT "KaRefDes=> " /* Monitor Command Prompt */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200219
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200220#define CFG_HUSH_PARSER 1 /* HUSH for ext'd cli */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200221#define CFG_PROMPT_HUSH_PS2 "> "
222
223
224/*-----------------------------------------------------------------------
225 * Console Buffer
226 *----------------------------------------------------------------------*/
Jon Loeliger348f2582007-07-08 13:46:18 -0500227#if defined(CONFIG_CMD_KGDB)
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200228#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200229#else
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200230#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200231#endif
232#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200233 /* Print Buffer Size */
234#define CFG_MAXARGS 16 /* max number of cmd args */
235#define CFG_BARGSIZE CFG_CBSIZE /* Boot Arg Buffer Size */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200236
237/*-----------------------------------------------------------------------
238 * Memory Test
239 *----------------------------------------------------------------------*/
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200240#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
241#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200242
243/*-----------------------------------------------------------------------
244 * Compact Flash (in true IDE mode)
245 *----------------------------------------------------------------------*/
246#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
247#undef CONFIG_IDE_LED /* no led for ide supported */
248
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200249#define CONFIG_IDE_RESET /* reset for ide supported */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200250#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
251#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
252
253#define CFG_ATA_BASE_ADDR 0xF0000000
254#define CFG_ATA_IDE0_OFFSET 0x0000
255#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
256#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/
257#define CFG_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */
258
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200259#define CFG_ATA_STRIDE 2 /* Directly connected CF, needs a stride
260 to get to the correct offset */
261#define CONFIG_DOS_PARTITION 1 /* Include dos partition */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200262
263/*-----------------------------------------------------------------------
264 * PCI
265 *----------------------------------------------------------------------*/
266/* General PCI */
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200267#define CONFIG_PCI /* include pci support */
268#define CONFIG_PCI_PNP /* do pci plug-and-play */
269#define CONFIG_PCI_SCAN_SHOW /* show pci devices */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200270#define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE)
271
272/* Board-specific PCI */
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200273#define CFG_PCI_TARGET_INIT /* let board init pci target*/
Stefan Roeseb79316f2005-08-15 12:31:23 +0200274
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200275#define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */
276#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200277
278/*
279 * For booting Linux, the board info and command line data
280 * have to be in the first 8 MB of memory, since this is
281 * the maximum mapped by the Linux kernel during initialization.
282 */
283#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
284/*-----------------------------------------------------------------------
285 * Cache Configuration
286 */
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200287#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200288#define CFG_CACHELINE_SIZE 32
Jon Loeliger348f2582007-07-08 13:46:18 -0500289#if defined(CONFIG_CMD_KGDB)
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200290#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200291#endif
292
293/*
294 * Internal Definitions
295 *
296 * Boot Flags
297 */
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200298#define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */
299#define BOOTFLAG_WARM 0x02 /* Software reboot */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200300
Jon Loeliger348f2582007-07-08 13:46:18 -0500301#if defined(CONFIG_CMD_KGDB)
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200302#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */
303#define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200304#endif
305
306/*-----------------------------------------------------------------------
307 * Miscellaneous configurable options
308 *----------------------------------------------------------------------*/
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200309#undef CONFIG_WATCHDOG /* watchdog disabled */
310#define CFG_LOAD_ADDR 0x8000000 /* default load address */
311#define CFG_EXTBDINFO 1 /* use extended board_info */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200312
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200313#define CFG_HZ 100 /* decr freq: 1 ms ticks */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200314
315
316#endif /* __CONFIG_H */