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Wolfgang Denkad5bb452007-03-06 18:08:43 +01001/*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25
26/*
27 * CPU test
28 * Logic instructions: andi., andis.
29 *
30 * The test contains a pre-built table of instructions, operands and
31 * expected results. For each table entry, the test will cyclically use
32 * different sets of operand registers and result registers.
33 */
34
Wolfgang Denkad5bb452007-03-06 18:08:43 +010035#include <post.h>
36#include "cpu_asm.h"
37
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020038#if CONFIG_POST & CONFIG_SYS_POST_CPU
Wolfgang Denkad5bb452007-03-06 18:08:43 +010039
40extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
41extern ulong cpu_post_makecr (long v);
42
43static struct cpu_post_andi_s
44{
45 ulong cmd;
46 ulong op1;
47 ushort op2;
48 ulong res;
49} cpu_post_andi_table[] =
50{
51 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +020052 OP_ANDI_,
Wolfgang Denkad5bb452007-03-06 18:08:43 +010053 0x80008000,
54 0xffff,
55 0x00008000
56 },
57 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +020058 OP_ANDIS_,
Wolfgang Denkad5bb452007-03-06 18:08:43 +010059 0x80008000,
60 0xffff,
61 0x80000000
62 },
63};
64static unsigned int cpu_post_andi_size =
65 sizeof (cpu_post_andi_table) / sizeof (struct cpu_post_andi_s);
66
67int cpu_post_test_andi (void)
68{
69 int ret = 0;
70 unsigned int i, reg;
71 int flag = disable_interrupts();
72
73 for (i = 0; i < cpu_post_andi_size && ret == 0; i++)
74 {
75 struct cpu_post_andi_s *test = cpu_post_andi_table + i;
76
77 for (reg = 0; reg < 32 && ret == 0; reg++)
78 {
79 unsigned int reg0 = (reg + 0) % 32;
80 unsigned int reg1 = (reg + 1) % 32;
81 unsigned int stk = reg < 16 ? 31 : 15;
Wolfgang Denk53677ef2008-05-20 16:00:29 +020082 unsigned long codecr[] =
Wolfgang Denkad5bb452007-03-06 18:08:43 +010083 {
84 ASM_STW(stk, 1, -4),
85 ASM_ADDI(stk, 1, -16),
86 ASM_STW(3, stk, 8),
87 ASM_STW(reg0, stk, 4),
88 ASM_STW(reg1, stk, 0),
89 ASM_LWZ(reg0, stk, 8),
90 ASM_11IX(test->cmd, reg1, reg0, test->op2),
91 ASM_STW(reg1, stk, 8),
92 ASM_LWZ(reg1, stk, 0),
93 ASM_LWZ(reg0, stk, 4),
94 ASM_LWZ(3, stk, 8),
95 ASM_ADDI(1, stk, 16),
96 ASM_LWZ(stk, 1, -4),
97 ASM_BLR,
98 };
99 ulong res;
100 ulong cr;
101
102 cpu_post_exec_21 (codecr, & cr, & res, test->op1);
103
104 ret = res == test->res &&
105 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
106
107 if (ret != 0)
108 {
109 post_log ("Error at andi test %d !\n", i);
110 }
111 }
112 }
113
114 if (flag)
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200115 enable_interrupts();
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100116
117 return ret;
118}
119
120#endif