blob: 760d021549383351b1c7dec0ddc157ff3ae0923f [file] [log] [blame]
Paul Burtoncd71b1d2018-12-16 19:25:22 -03001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Startup Code for MIPS32 XBURST CPU-core
4 *
5 * Copyright (c) 2010 Xiangfu Liu <xiangfu@sharism.cc>
6 */
7
8#include <config.h>
9#include <asm/regdef.h>
10#include <asm/mipsregs.h>
11#include <asm/addrspace.h>
12#include <asm/cacheops.h>
13#include <asm/cache.h>
14#include <mach/jz4780.h>
15
16 .set noreorder
17
18 .globl _start
19 .text
20_start:
21#ifdef CONFIG_SPL_BUILD
22
23 /* magic value ("MSPL") */
24 .word 0x4d53504c
25
26 /* Invalidate BTB */
27 mfc0 t0, CP0_CONFIG, 7
28 nop
29 ori t0, 2
30 mtc0 t0, CP0_CONFIG, 7
31 nop
32
33 /*
34 * CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1
35 */
36 li t0, 0x0040FC04
37 mtc0 t0, CP0_STATUS
38
39 /* CAUSE register */
40 /* IV=1, use the specical interrupt vector (0x200) */
41 li t1, 0x00800000
42 mtc0 t1, CP0_CAUSE
43
44#ifdef CONFIG_SOC_JZ4780
45 /* enable bridge radical mode */
46 la t0, CPM_BASE
47 lw t1, 0x24(t0)
48 ori t1, t1, 0x22
49 sw t1, 0x24(t0)
50#endif
51
52 /* Set up stack */
53 li sp, CONFIG_SPL_STACK
54
55 b board_init_f
56 nop
57
58#ifdef CONFIG_SOC_JZ4780
59
60 .globl enable_caches
61 .ent enable_caches
62enable_caches:
63 mtc0 zero, CP0_TAGLO
64 mtc0 zero, CP0_TAGHI
65
66 li t0, KSEG0
67 addu t1, t0, CONFIG_SYS_DCACHE_SIZE
681:
69 cache INDEX_STORE_TAG_D, 0(t0)
70 bne t0, t1, 1b
71 addiu t0, t0, CONFIG_SYS_CACHELINE_SIZE
72
73 li t0, KSEG0
74 addu t1, t0, CONFIG_SYS_ICACHE_SIZE
752:
76 cache INDEX_STORE_TAG_I, 0(t0)
77 bne t0, t1, 2b
78 addiu t0, t0, CONFIG_SYS_CACHELINE_SIZE
79
80 /* Invalidate BTB */
81 mfc0 t0, CP0_CONFIG, 7
82 nop
83 ori t0, 2
84 mtc0 t0, CP0_CONFIG, 7
85 nop
86
87 /* Enable caches */
88 li t0, CONF_CM_CACHABLE_NONCOHERENT
89 mtc0 t0, CP0_CONFIG
90 nop
91
92 jr ra
93 nop
94
95 .end enable_caches
96
97#endif /* CONFIG_SOC_JZ4780 */
98#endif /* !CONFIG_SPL_BUILD */