blob: 0c2c1c565bdd115ad1332cfd43598bf710c19330 [file] [log] [blame]
Shengzhou Liu8d67c362014-03-05 15:04:48 +08001/*
2 * Copyright 2009-2013 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <command.h>
9#include <i2c.h>
10#include <netdev.h>
11#include <linux/compiler.h>
12#include <asm/mmu.h>
13#include <asm/processor.h>
14#include <asm/immap_85xx.h>
15#include <asm/fsl_law.h>
16#include <asm/fsl_serdes.h>
17#include <asm/fsl_portals.h>
18#include <asm/fsl_liodn.h>
19#include <fm_eth.h>
20#include "t208xrdb.h"
21#include "cpld.h"
Ying Zhange5abb922015-03-10 14:21:36 +080022#include "../common/vid.h"
Shengzhou Liu8d67c362014-03-05 15:04:48 +080023
24DECLARE_GLOBAL_DATA_PTR;
25
26int checkboard(void)
27{
28 struct cpu_type *cpu = gd->arch.cpu;
29 static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
30
31 printf("Board: %sRDB, ", cpu->name);
32 printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
33 CPLD_READ(hw_ver), CPLD_READ(sw_ver));
34
35#ifdef CONFIG_SDCARD
36 puts("SD/MMC\n");
37#elif CONFIG_SPIFLASH
38 puts("SPI\n");
39#else
40 u8 reg;
41
42 reg = CPLD_READ(flash_csr);
43
44 if (reg & CPLD_BOOT_SEL) {
45 puts("NAND\n");
46 } else {
47 reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
Shengzhou Liuef531c72014-04-18 16:43:41 +080048 printf("NOR vBank%d\n", reg);
Shengzhou Liu8d67c362014-03-05 15:04:48 +080049 }
50#endif
51
52 puts("SERDES Reference Clocks:\n");
53 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
54 printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[0], freq[0]);
55
56 return 0;
57}
58
59int board_early_init_r(void)
60{
61 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
York Sun9d045682014-06-24 21:16:20 -070062 int flash_esel = find_tlb_idx((void *)flashbase, 1);
Shengzhou Liu8d67c362014-03-05 15:04:48 +080063 /*
64 * Remap Boot flash + PROMJET region to caching-inhibited
65 * so that flash can be erased properly.
66 */
67
68 /* Flush d-cache and invalidate i-cache of any FLASH data */
69 flush_dcache();
70 invalidate_icache();
York Sun9d045682014-06-24 21:16:20 -070071 if (flash_esel == -1) {
72 /* very unlikely unless something is messed up */
73 puts("Error: Could not find TLB for FLASH BASE\n");
74 flash_esel = 2; /* give our best effort to continue */
75 } else {
76 /* invalidate existing TLB entry for flash + promjet */
77 disable_tlb(flash_esel);
78 }
Shengzhou Liu8d67c362014-03-05 15:04:48 +080079
80 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
81 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
82 0, flash_esel, BOOKE_PAGESZ_256M, 1);
83
84 set_liodns();
85#ifdef CONFIG_SYS_DPAA_QBMAN
86 setup_portals();
87#endif
88
Ying Zhange5abb922015-03-10 14:21:36 +080089 /*
90 * Adjust core voltage according to voltage ID
91 * This function changes I2C mux to channel 2.
92 */
93 if (adjust_vdd(0))
94 printf("Warning: Adjusting core voltage failed.\n");
Shengzhou Liu8d67c362014-03-05 15:04:48 +080095 return 0;
96}
97
98unsigned long get_board_sys_clk(void)
99{
100 return CONFIG_SYS_CLK_FREQ;
101}
102
103unsigned long get_board_ddr_clk(void)
104{
105 return CONFIG_DDR_CLK_FREQ;
106}
107
108int misc_init_r(void)
109{
Shengzhou Liufd3a78a2015-04-22 10:59:50 +0800110 u8 reg;
111
112 /* Reset CS4315 PHY */
113 reg = CPLD_READ(reset_ctl);
114 reg |= CPLD_RSTCON_EDC_RST;
115 CPLD_WRITE(reset_ctl, reg);
116
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800117 return 0;
118}
119
Simon Glasse895a4b2014-10-23 18:58:47 -0600120int ft_board_setup(void *blob, bd_t *bd)
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800121{
122 phys_addr_t base;
123 phys_size_t size;
124
125 ft_cpu_setup(blob, bd);
126
127 base = getenv_bootm_low();
128 size = getenv_bootm_size();
129
130 fdt_fixup_memory(blob, (u64)base, (u64)size);
131
132#ifdef CONFIG_PCI
133 pci_of_setup(blob, bd);
134#endif
135
136 fdt_fixup_liodn(blob);
137 fdt_fixup_dr_usb(blob, bd);
138
139#ifdef CONFIG_SYS_DPAA_FMAN
140 fdt_fixup_fman_ethernet(blob);
141 fdt_fixup_board_enet(blob);
142#endif
Simon Glasse895a4b2014-10-23 18:58:47 -0600143
144 return 0;
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800145}