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wdenkfe8c2802002-11-03 00:38:21 +00001/*
2 * (C) Copyright 2000
3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
4 *
5 * (C) Copyright 2000
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * (C) Copyright 2001
10 * Advent Networks, Inc. <http://www.adventnetworks.com>
11 * Jay Monkman <jtm@smoothsmoothie.com>
12 *
13 * Configuation settings for the WindRiver PPMC8260 board.
14 *
15 * See file CREDITS for list of people who contributed to this
16 * project.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA
32 */
33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
Wolfgang Denk2ae18242010-10-06 09:05:45 +020037#define CONFIG_SYS_TEXT_BASE 0xfe000000
38
wdenkfe8c2802002-11-03 00:38:21 +000039/*****************************************************************************
40 *
41 * These settings must match the way _your_ board is set up
42 *
43 *****************************************************************************/
44
45/* What is the oscillator's (UX2) frequency in Hz? */
46#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
47
48/*-----------------------------------------------------------------------
49 * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
50 *-----------------------------------------------------------------------
51 * What should MODCK_H be? It is dependent on the oscillator
52 * frequency, MODCK[1-3], and desired CPM and core frequencies.
53 * Here are some example values (all frequencies are in MHz):
54 *
55 * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
56 * ------- ---------- --- --- ---- ----- ----- -----
57 * 0x2 0x2 33 133 133 Close Open Close
58 * 0x2 0x3 33 133 166 Close Open Open
59 * 0x2 0x4 33 133 200 Open Close Close
60 * 0x2 0x5 33 133 233 Open Close Open
61 * 0x2 0x6 33 133 266 Open Open Close
62 *
63 * 0x5 0x5 66 133 133 Open Close Open
64 * 0x5 0x6 66 133 166 Open Open Close
65 * 0x5 0x7 66 133 200 Open Open Open
66 * 0x6 0x0 66 133 233 Close Close Close
67 * 0x6 0x1 66 133 266 Close Close Open
68 * 0x6 0x2 66 133 300 Close Open Close
69 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#define CONFIG_SYS_PPMC_MODCK_H 0x05
wdenkfe8c2802002-11-03 00:38:21 +000071
72/* Define this if you want to boot from 0x00000100. If you don't define
73 * this, you will need to program the bootloader to 0xfff00000, and
74 * get the hardware reset config words at 0xfe000000. The simplest
75 * way to do that is to program the bootloader at both addresses.
76 * It is suggested that you just let U-Boot live at 0x00000000.
77 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_PPMC_BOOT_LOW 1
wdenkfe8c2802002-11-03 00:38:21 +000079
80/* What should the base address of the main FLASH be and how big is
Wolfgang Denk14d0a022010-10-07 21:51:12 +020081 * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ppmc8260/config.mk
wdenkfe8c2802002-11-03 00:38:21 +000082 * The main FLASH is whichever is connected to *CS0. U-Boot expects
83 * this to be the SIMM.
84 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CONFIG_SYS_FLASH0_BASE 0xFE000000
86#define CONFIG_SYS_FLASH0_SIZE 16
wdenkfe8c2802002-11-03 00:38:21 +000087
88/* What should be the base address of the first SDRAM DIMM and how big is
89 * it (in Mbytes)?
90*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_SDRAM0_BASE 0x00000000
92#define CONFIG_SYS_SDRAM0_SIZE 128
wdenkfe8c2802002-11-03 00:38:21 +000093
94/* What should be the base address of the second SDRAM DIMM and how big is
95 * it (in Mbytes)?
96*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_SDRAM1_BASE 0x08000000
98#define CONFIG_SYS_SDRAM1_SIZE 128
wdenkfe8c2802002-11-03 00:38:21 +000099
100/* What should be the base address of the on board SDRAM and how big is
101 * it (in Mbytes)?
102*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_SDRAM2_BASE 0x38000000
104#define CONFIG_SYS_SDRAM2_SIZE 16
wdenkfe8c2802002-11-03 00:38:21 +0000105
106/* What should be the base address of the MAILBOX and how big is it
107 * (in Bytes)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108 * The eeprom lives at CONFIG_SYS_MAILBOX_BASE + 0x80000000
wdenkfe8c2802002-11-03 00:38:21 +0000109 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_MAILBOX_BASE 0x32000000
111#define CONFIG_SYS_MAILBOX_SIZE 8192
wdenkfe8c2802002-11-03 00:38:21 +0000112
113/* What is the base address of the I/O select lines and how big is it
114 * (In Mbytes)?
115 */
116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_IOSELECT_BASE 0xE0000000
118#define CONFIG_SYS_IOSELECT_SIZE 32
wdenkfe8c2802002-11-03 00:38:21 +0000119
120
121/* What should be the base address of the LEDs and switch S0?
122 * If you don't want them enabled, don't define this.
123 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_LED_BASE 0xF1000000
wdenkfe8c2802002-11-03 00:38:21 +0000125
126/*
127 * PPMC8260 with 256 16 MB DIMM:
128 *
129 * 0x0000 0000 Exception Vector code, 8k
130 * :
131 * 0x0000 1FFF
132 * 0x0000 2000 Free for Application Use
133 * :
134 * :
135 *
136 * :
137 * :
138 * 0x0FF5 FF30 Monitor Stack (Growing downward)
139 * Monitor Stack Buffer (0x80)
140 * 0x0FF5 FFB0 Board Info Data
141 * 0x0FF6 0000 Malloc Arena
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200142 * : CONFIG_ENV_SECT_SIZE, 256k
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143 * : CONFIG_SYS_MALLOC_LEN, 128k
wdenkfe8c2802002-11-03 00:38:21 +0000144 * 0x0FFC 0000 RAM Copy of Monitor Code
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145 * : CONFIG_SYS_MONITOR_LEN, 256k
146 * 0x0FFF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
wdenkfe8c2802002-11-03 00:38:21 +0000147 */
148
149
150/*
151 * select serial console configuration
152 *
153 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
154 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
155 * for SCC).
156 *
157 * if CONFIG_CONS_NONE is defined, then the serial console routines must
158 * defined elsewhere.
159 * The console can be on SMC1 or SMC2
160 */
161#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
162#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
163#undef CONFIG_CONS_NONE /* define if console on neither */
164#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
165
166/*
167 * select ethernet configuration
168 *
169 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
170 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
171 * for FCC)
172 *
173 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -0500174 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenkfe8c2802002-11-03 00:38:21 +0000175 */
176
177#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
178#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
179#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
180#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
181#define CONFIG_MII /* MII PHY management */
182#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
183/*
184 * Port pins used for bit-banged MII communictions (if applicable).
185 */
186#define MDIO_PORT 2 /* Port C */
Luigi 'Comio' Mantellinibe225442009-10-10 12:42:22 +0200187#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
188 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
189#define MDC_DECLARE MDIO_DECLARE
190
wdenkfe8c2802002-11-03 00:38:21 +0000191#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
192#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
193#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
194
195#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
196 else iop->pdat &= ~0x00400000
197
198#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
199 else iop->pdat &= ~0x00200000
200
201#define MIIDELAY udelay(1)
202
203
204/* Define this to reserve an entire FLASH sector (256 KB) for
205 * environment variables. Otherwise, the environment will be
206 * put in the same sector as U-Boot, and changing variables
207 * will erase U-Boot temporarily
208 */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200209#define CONFIG_ENV_IN_OWN_SECT 1
wdenkfe8c2802002-11-03 00:38:21 +0000210
211/* Define to allow the user to overwrite serial and ethaddr */
212#define CONFIG_ENV_OVERWRITE
213
214/* What should the console's baud rate be? */
215#define CONFIG_BAUDRATE 9600
216
217/* Ethernet MAC address */
218
219#define CONFIG_ETHADDR 00:a0:1e:90:2b:00
220
221/* Define this to set the last octet of the ethernet address
222 * from the DS0-DS7 switch and light the leds with the result
223 * The DS0-DS7 switch and the leds are backwards with respect
224 * to each other. DS7 is on the board edge side of both the
225 * led strip and the DS0-DS7 switch.
226 */
227#define CONFIG_MISC_INIT_R
228
229/* Set to a positive value to delay for running BOOTCOMMAND */
230#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
231
232#if 0
233/* Be selective on what keys can delay or stop the autoboot process
234 * To stop use: " "
235 */
236# define CONFIG_AUTOBOOT_KEYED
Wolfgang Denkc37207d2008-07-16 16:38:59 +0200237# define CONFIG_AUTOBOOT_PROMPT \
238 "Autobooting in %d seconds, press \" \" to stop\n", bootdelay
wdenkfe8c2802002-11-03 00:38:21 +0000239# define CONFIG_AUTOBOOT_STOP_STR " "
240# undef CONFIG_AUTOBOOT_DELAY_STR
241# define DEBUG_BOOTKEYS 0
242#endif
243
244/* Define a command string that is automatically executed when no character
245 * is read on the console interface withing "Boot Delay" after reset.
246 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200247#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
wdenkb79a11c2004-03-25 15:14:43 +0000248#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
wdenkfe8c2802002-11-03 00:38:21 +0000249
wdenk42dfe7a2004-03-14 22:25:36 +0000250#ifdef CONFIG_BOOT_ROOT_INITRD
wdenkfe8c2802002-11-03 00:38:21 +0000251#define CONFIG_BOOTCOMMAND \
252 "version;" \
253 "echo;" \
254 "bootp;" \
255 "setenv bootargs root=/dev/ram0 rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100256 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenkfe8c2802002-11-03 00:38:21 +0000257 "bootm"
258#endif /* CONFIG_BOOT_ROOT_INITRD */
259
wdenk42dfe7a2004-03-14 22:25:36 +0000260#ifdef CONFIG_BOOT_ROOT_NFS
wdenkfe8c2802002-11-03 00:38:21 +0000261#define CONFIG_BOOTCOMMAND \
262 "version;" \
263 "echo;" \
264 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100265 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
266 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenkfe8c2802002-11-03 00:38:21 +0000267 "bootm"
268#endif /* CONFIG_BOOT_ROOT_NFS */
269
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500270
271/*
272 * BOOTP options
wdenkfe8c2802002-11-03 00:38:21 +0000273 */
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500274#define CONFIG_BOOTP_SUBNETMASK
275#define CONFIG_BOOTP_GATEWAY
276#define CONFIG_BOOTP_HOSTNAME
277#define CONFIG_BOOTP_BOOTPATH
278#define CONFIG_BOOTP_BOOTFILESIZE
279#define CONFIG_BOOTP_DNS
280
wdenkfe8c2802002-11-03 00:38:21 +0000281
282/* undef this to save memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_LONGHELP
wdenkfe8c2802002-11-03 00:38:21 +0000284
285/* Monitor Command Prompt */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_PROMPT "=> "
wdenkfe8c2802002-11-03 00:38:21 +0000287
Jon Loeliger26a34562007-07-04 22:33:17 -0500288
289/*
290 * Command line configuration.
291 */
292#include <config_cmd_default.h>
293
294#define CONFIG_CMD_ELF
295#define CONFIG_CMD_ASKENV
296#define CONFIG_CMD_REGINFO
297#define CONFIG_CMD_MEMTEST
298#define CONFIG_CMD_MII
299#define CONFIG_CMD_IMMAP
300
301#undef CONFIG_CMD_KGDB
wdenkfe8c2802002-11-03 00:38:21 +0000302
303
304/* Where do the internal registers live? */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_IMMR 0xf0000000
wdenkfe8c2802002-11-03 00:38:21 +0000306
307/*****************************************************************************
308 *
309 * You should not have to modify any of the following settings
310 *
311 *****************************************************************************/
312
313#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
314#define CONFIG_PPMC8260 1 /* on an Wind River PPMC8260 Board */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500315#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenkfe8c2802002-11-03 00:38:21 +0000316
wdenkfe8c2802002-11-03 00:38:21 +0000317/*
318 * Miscellaneous configurable options
319 */
Jon Loeliger26a34562007-07-04 22:33:17 -0500320#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkfe8c2802002-11-03 00:38:21 +0000322#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkfe8c2802002-11-03 00:38:21 +0000324#endif
325
326/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
wdenkfe8c2802002-11-03 00:38:21 +0000328
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
wdenkfe8c2802002-11-03 00:38:21 +0000330
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkfe8c2802002-11-03 00:38:21 +0000332
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#define CONFIG_SYS_LOAD_ADDR 0x140000 /* default load address */
334#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkfe8c2802002-11-03 00:38:21 +0000335
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */
wdenkfe8c2802002-11-03 00:38:21 +0000337 /* the exception vector table */
338 /* to the end of the DRAM */
339 /* less monitor and malloc area */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
341#define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \
342 + CONFIG_SYS_MALLOC_LEN \
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200343 + CONFIG_ENV_SECT_SIZE \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344 + CONFIG_SYS_STACK_USAGE )
wdenkfe8c2802002-11-03 00:38:21 +0000345
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_MEMTEST_END ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
347 - CONFIG_SYS_MEM_END_USAGE )
wdenkfe8c2802002-11-03 00:38:21 +0000348
349/* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenkfe8c2802002-11-03 00:38:21 +0000351
352/*
353 * Low Level Configuration Settings
354 * (address mappings, register initial values, etc.)
355 * You should know what you are doing if you make changes here.
356 */
357
358#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
359/*
360 * Attention: This is board specific
361 * - RX clk is CLK11
362 * - TX clk is CLK12
363 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 |\
wdenkfe8c2802002-11-03 00:38:21 +0000365 CMXSCR_TS1CS_CLK12)
366
367#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
368/*
369 * Attention: this is board-specific
370 * - Rx-CLK is CLK13
371 * - Tx-CLK is CLK14
372 * - Select bus for bd/buffers (see 28-13)
373 * - Enable Full Duplex in FSMR
374 */
Mike Frysingerd4590da2011-10-17 05:38:58 +0000375#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
376#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377#define CONFIG_SYS_CPMFCR_RAMTYPE 0
378#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
wdenkfe8c2802002-11-03 00:38:21 +0000379#endif /* CONFIG_ETHER_INDEX */
380
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
382#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
383#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE
384#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_SDRAM0_SIZE + CONFIG_SYS_SDRAM1_SIZE)
wdenkfe8c2802002-11-03 00:38:21 +0000385
386/*-----------------------------------------------------------------------
387 * Hard Reset Configuration Words
388 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389#if defined(CONFIG_SYS_PPMC_BOOT_LOW)
390# define CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
wdenkfe8c2802002-11-03 00:38:21 +0000391#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392# define CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS (0)
393#endif /* defined(CONFIG_SYS_PPMC_BOOT_LOW) */
wdenkfe8c2802002-11-03 00:38:21 +0000394
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395/* get the HRCW ISB field from CONFIG_SYS_IMMR */
396#define CONFIG_SYS_PPMC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
397 ((CONFIG_SYS_IMMR & 0x01000000) >> 7) | \
398 ((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
wdenkfe8c2802002-11-03 00:38:21 +0000399
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400#define CONFIG_SYS_HRCW_MASTER ( HRCW_EBM | \
wdenkfe8c2802002-11-03 00:38:21 +0000401 HRCW_BPS11 | \
402 HRCW_L2CPC10 | \
403 HRCW_DPPC00 | \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200404 CONFIG_SYS_PPMC_HRCW_IMMR | \
wdenkfe8c2802002-11-03 00:38:21 +0000405 HRCW_MMR00 | \
406 HRCW_LBPC00 | \
407 HRCW_APPC10 | \
408 HRCW_CS10PC00 | \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409 (CONFIG_SYS_PPMC_MODCK_H & HRCW_MODCK_H1111) | \
410 CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS )
wdenkfe8c2802002-11-03 00:38:21 +0000411
412/* no slaves */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413#define CONFIG_SYS_HRCW_SLAVE1 0
414#define CONFIG_SYS_HRCW_SLAVE2 0
415#define CONFIG_SYS_HRCW_SLAVE3 0
416#define CONFIG_SYS_HRCW_SLAVE4 0
417#define CONFIG_SYS_HRCW_SLAVE5 0
418#define CONFIG_SYS_HRCW_SLAVE6 0
419#define CONFIG_SYS_HRCW_SLAVE7 0
wdenkfe8c2802002-11-03 00:38:21 +0000420
421/*-----------------------------------------------------------------------
422 * Definitions for initial stack pointer and data area (in DPRAM)
423 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200424#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200425#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200426#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200427#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkfe8c2802002-11-03 00:38:21 +0000428
429/*-----------------------------------------------------------------------
430 * Start addresses for the final memory configuration
431 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200432 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
433 * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
wdenkfe8c2802002-11-03 00:38:21 +0000434 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE
wdenkfe8c2802002-11-03 00:38:21 +0000436
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200437#ifndef CONFIG_SYS_MONITOR_BASE
438#define CONFIG_SYS_MONITOR_BASE 0x0ff80000
wdenkfe8c2802002-11-03 00:38:21 +0000439#endif
440
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200441#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
442# define CONFIG_SYS_RAMBOOT
wdenkfe8c2802002-11-03 00:38:21 +0000443#endif
444
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200445#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 374 kB for Monitor */
446#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkfe8c2802002-11-03 00:38:21 +0000447
448/*
449 * For booting Linux, the board info and command line data
450 * have to be in the first 8 MB of memory, since this is
451 * the maximum mapped by the Linux kernel during initialization.
452 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200453#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkfe8c2802002-11-03 00:38:21 +0000454
455/*-----------------------------------------------------------------------
456 * FLASH and environment organization
457 */
458
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200459#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200460#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200461#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
462#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
463#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */
464#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
465#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
wdenkfe8c2802002-11-03 00:38:21 +0000466
467
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200468#ifndef CONFIG_SYS_RAMBOOT
wdenkfe8c2802002-11-03 00:38:21 +0000469
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200470# define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200471# ifdef CONFIG_ENV_IN_OWN_SECT
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200472# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200473# define CONFIG_ENV_SECT_SIZE 0x40000
wdenkfe8c2802002-11-03 00:38:21 +0000474# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200475# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200476# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
477# define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */
478# endif /* CONFIG_ENV_IN_OWN_SECT */
wdenkfe8c2802002-11-03 00:38:21 +0000479
480#else
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200481# define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200482# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200483#define CONFIG_ENV_SIZE 0x1000
484# define CONFIG_ENV_SECT_SIZE 0x40000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200485#endif /* CONFIG_SYS_RAMBOOT */
wdenkfe8c2802002-11-03 00:38:21 +0000486
487/*-----------------------------------------------------------------------
488 * Cache Configuration
489 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200490#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
wdenkfe8c2802002-11-03 00:38:21 +0000491
Jon Loeliger26a34562007-07-04 22:33:17 -0500492#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200493# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenkfe8c2802002-11-03 00:38:21 +0000494#endif
495
496/*-----------------------------------------------------------------------
497 * HIDx - Hardware Implementation-dependent Registers 2-11
498 *-----------------------------------------------------------------------
499 * HID0 also contains cache control - initially enable both caches and
500 * invalidate contents, then the final state leaves only the instruction
501 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
502 * but Soft reset does not.
503 *
504 * HID1 has only read-only information - nothing to set.
505 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200506#define CONFIG_SYS_HID0_INIT (HID0_ICE |\
wdenkfe8c2802002-11-03 00:38:21 +0000507 HID0_DCE |\
508 HID0_ICFI |\
509 HID0_DCI |\
510 HID0_IFEM |\
511 HID0_ABE)
512
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200513#define CONFIG_SYS_HID0_FINAL (HID0_ICE |\
wdenkfe8c2802002-11-03 00:38:21 +0000514 HID0_IFEM |\
515 HID0_ABE |\
516 HID0_EMCP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200517#define CONFIG_SYS_HID2 0
wdenkfe8c2802002-11-03 00:38:21 +0000518
519/*-----------------------------------------------------------------------
520 * RMR - Reset Mode Register
521 *-----------------------------------------------------------------------
522 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200523#define CONFIG_SYS_RMR 0
wdenkfe8c2802002-11-03 00:38:21 +0000524
525/*-----------------------------------------------------------------------
526 * BCR - Bus Configuration 4-25
527 *-----------------------------------------------------------------------
528 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200529#define CONFIG_SYS_BCR (BCR_EBM |\
wdenkfe8c2802002-11-03 00:38:21 +0000530 0x30000000)
531
532/*-----------------------------------------------------------------------
533 * SIUMCR - SIU Module Configuration 4-31
534 * Ref Section 4.3.2.6 page 4-31
535 *-----------------------------------------------------------------------
536 */
537
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200538#define CONFIG_SYS_SIUMCR (SIUMCR_ESE |\
wdenkfe8c2802002-11-03 00:38:21 +0000539 SIUMCR_DPPC00 |\
540 SIUMCR_L2CPC10 |\
541 SIUMCR_LBPC00 |\
542 SIUMCR_APPC10 |\
543 SIUMCR_CS10PC00 |\
544 SIUMCR_BCTLC00 |\
545 SIUMCR_MMR00)
546
547
548/*-----------------------------------------------------------------------
549 * SYPCR - System Protection Control 11-9
550 * SYPCR can only be written once after reset!
551 *-----------------------------------------------------------------------
552 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
553 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200554#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
wdenkfe8c2802002-11-03 00:38:21 +0000555 SYPCR_BMT |\
556 SYPCR_PBME |\
557 SYPCR_LBME |\
558 SYPCR_SWRI |\
559 SYPCR_SWP)
560
561/*-----------------------------------------------------------------------
562 * TMCNTSC - Time Counter Status and Control 4-40
563 *-----------------------------------------------------------------------
564 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
565 * and enable Time Counter
566 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200567#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\
wdenkfe8c2802002-11-03 00:38:21 +0000568 TMCNTSC_ALR |\
569 TMCNTSC_TCF |\
570 TMCNTSC_TCE)
571
572/*-----------------------------------------------------------------------
573 * PISCR - Periodic Interrupt Status and Control 4-42
574 *-----------------------------------------------------------------------
575 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
576 * Periodic timer
577 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200578#define CONFIG_SYS_PISCR (PISCR_PS |\
wdenkfe8c2802002-11-03 00:38:21 +0000579 PISCR_PTF |\
580 PISCR_PTE)
581
582/*-----------------------------------------------------------------------
583 * SCCR - System Clock Control 9-8
584 *-----------------------------------------------------------------------
585 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200586#define CONFIG_SYS_SCCR 0
wdenkfe8c2802002-11-03 00:38:21 +0000587
588/*-----------------------------------------------------------------------
589 * RCCR - RISC Controller Configuration 13-7
590 *-----------------------------------------------------------------------
591 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200592#define CONFIG_SYS_RCCR 0
wdenkfe8c2802002-11-03 00:38:21 +0000593
594/*
595 * Initialize Memory Controller:
596 *
597 * Bank Bus Machine PortSz Device
598 * ---- --- ------- ------ ------
599 * 0 60x GPCM 32 bit FLASH (SIMM - 32MB) *
600 * 1 unused
601 * 2 60x SDRAM 64 bit SDRAM (DIMM - 128MB)
602 * 3 60x SDRAM 64 bit SDRAM (DIMM - 128MB)
603 * 4 Local SDRAM 32 bit SDRAM (on board - 16MB)
604 * 5 60x GPCM 8 bit Mailbox/EEPROM (8KB)
605 * 6 60x GPCM 8 bit FLASH (on board - 2MB) *
606 * 7 60x GPCM 8 bit LEDs, switches
607 *
608 * (*) This configuration requires the PPMC8260 be configured
609 * so that *CS0 goes to the FLASH SIMM, and *CS6 goes to
610 * the on board FLASH. In other words, JP24 should have
611 * pins 1 and 2 jumpered and pins 3 and 4 jumpered.
612 *
613 */
614
615/*-----------------------------------------------------------------------
616 * BR0,BR1 - Base Register
617 * Ref: Section 10.3.1 on page 10-14
618 * OR0,OR1 - Option Register
619 * Ref: Section 10.3.2 on page 10-18
620 *-----------------------------------------------------------------------
621 */
622
623/* Bank 0,1 - FLASH SIMM
624 *
625 * This expects the FLASH SIMM to be connected to *CS0
626 * It consists of 4 AM29F080B parts.
627 *
628 * Note: For the 4 MB SIMM, *CS1 is unused.
629 */
630
631/* BR0 is configured as follows:
632 *
633 * - Base address of 0xFE000000
634 * - 32 bit port size
635 * - Data errors checking is disabled
636 * - Read and write access
637 * - GPCM 60x bus
638 * - Access are handled by the memory controller according to MSEL
639 * - Not used for atomic operations
640 * - No data pipelining is done
641 * - Valid
642 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200643#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
wdenkfe8c2802002-11-03 00:38:21 +0000644 BRx_PS_32 |\
645 BRx_MS_GPCM_P |\
646 BRx_V)
647
648/* OR0 is configured as follows:
649 *
650 * - 32 MB
651 * - *BCTL0 is asserted upon access to the current memory bank
652 * - *CW / *WE are negated a quarter of a clock earlier
653 * - *CS is output at the same time as the address lines
654 * - Uses a clock cycle length of 5
655 * - *PSDVAL is generated internally by the memory controller
656 * unless *GTA is asserted earlier externally.
657 * - Relaxed timing is generated by the GPCM for accesses
658 * initiated to this memory region.
659 * - One idle clock is inserted between a read access from the
660 * current bank and the next access.
661 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200662#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\
wdenkfe8c2802002-11-03 00:38:21 +0000663 ORxG_CSNT |\
664 ORxG_ACS_DIV1 |\
665 ORxG_SCY_5_CLK |\
666 ORxG_TRLX |\
667 ORxG_EHTR)
668
669/*-----------------------------------------------------------------------
670 * BR2,BR3 - Base Register
671 * Ref: Section 10.3.1 on page 10-14
672 * OR2,OR3 - Option Register
673 * Ref: Section 10.3.2 on page 10-16
674 *-----------------------------------------------------------------------
675 */
676
677/*
678 * Bank 2,3 - 128 MB SDRAM DIMM
679 */
680
681/* With a 128 MB DIMM, the BR2 is configured as follows:
682 *
683 * - Base address of 0x00000000/0x08000000
684 * - 64 bit port size (60x bus only)
685 * - Data errors checking is disabled
686 * - Read and write access
687 * - SDRAM 60x bus
688 * - Access are handled by the memory controller according to MSEL
689 * - Not used for atomic operations
690 * - No data pipelining is done
691 * - Valid
692 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200693#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
wdenkfe8c2802002-11-03 00:38:21 +0000694 BRx_PS_64 |\
695 BRx_MS_SDRAM_P |\
696 BRx_V)
697
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200698#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\
wdenkfe8c2802002-11-03 00:38:21 +0000699 BRx_PS_64 |\
700 BRx_MS_SDRAM_P |\
701 BRx_V)
702
703/* With a 128 MB DIMM, the OR2 is configured as follows:
704 *
705 * - 128 MB
706 * - 4 internal banks per device
707 * - Row start address bit is A8 with PSDMR[PBI] = 0
708 * - 13 row address lines
709 * - Back-to-back page mode
710 * - Internal bank interleaving within save device enabled
711 */
712
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200713#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
wdenkfe8c2802002-11-03 00:38:21 +0000714 ORxS_BPD_4 |\
715 ORxS_ROWST_PBI0_A7 |\
716 ORxS_NUMR_13)
717
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200718#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE) |\
wdenkfe8c2802002-11-03 00:38:21 +0000719 ORxS_BPD_4 |\
720 ORxS_ROWST_PBI0_A7 |\
721 ORxS_NUMR_13)
722
723
724/*-----------------------------------------------------------------------
725 * PSDMR - 60x Bus SDRAM Mode Register
726 * Ref: Section 10.3.3 on page 10-21
727 *-----------------------------------------------------------------------
728 */
729
730/* With a 128 MB DIMM, the PSDMR is configured as follows:
731 *
732 * - Page Based Interleaving,
733 * - Refresh Enable,
734 * - Normal Operation
735 * - Address Multiplexing where A5 is output on A14 pin
736 * (A6 on A15, and so on),
737 * - use address pins A13-A15 as bank select,
738 * - A9 is output on SDA10 during an ACTIVATE command,
739 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
740 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
741 * is 3 clocks,
742 * - earliest timing for READ/WRITE command after ACTIVATE command is
743 * 2 clocks,
744 * - earliest timing for PRECHARGE after last data was read is 1 clock,
745 * - earliest timing for PRECHARGE after last data was written is 1 clock,
746 * - External Address Multiplexing enabled
747 * - CAS Latency is 2.
748 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200749#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
wdenkfe8c2802002-11-03 00:38:21 +0000750 PSDMR_SDAM_A14_IS_A5 |\
751 PSDMR_BSMA_A13_A15 |\
752 PSDMR_SDA10_PBI0_A9 |\
753 PSDMR_RFRC_7_CLK |\
754 PSDMR_PRETOACT_3W |\
755 PSDMR_ACTTORW_2W |\
756 PSDMR_LDOTOPRE_1C |\
757 PSDMR_WRC_1C |\
758 PSDMR_EAMUX |\
759 PSDMR_CL_2)
760
761
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200762#define CONFIG_SYS_PSRT 0x0e
763#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32
wdenkfe8c2802002-11-03 00:38:21 +0000764
765
766/*-----------------------------------------------------------------------
767 * BR4 - Base Register
768 * Ref: Section 10.3.1 on page 10-14
769 * OR4 - Option Register
770 * Ref: Section 10.3.2 on page 10-16
771 *-----------------------------------------------------------------------
772 */
773
774/*
775 * Bank 4 - On board SDRAM
776 *
777 */
778/* With 16 MB of onboard SDRAM BR4 is configured as follows
779 *
780 * - Base address 0x38000000
781 * - 32 bit port size
782 * - Data error checking disabled
783 * - Read/Write access
784 * - SDRAM local bus
785 * - Not used for atomic operations
786 * - No data pipelining is done
787 * - Valid
788 *
789 */
790
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200791#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_SDRAM2_BASE & BRx_BA_MSK) |\
wdenkfe8c2802002-11-03 00:38:21 +0000792 BRx_PS_32 |\
793 BRx_DECC_NONE |\
794 BRx_MS_SDRAM_L |\
795 BRx_V)
796
797/*
798 * With 16MB SDRAM, OR4 is configured as follows
799 * - 4 internal banks per device
800 * - Row start address bit is A10 with LSDMR[PBI] = 0
801 * - 12 row address lines
802 * - Back-to-back page mode
803 * - Internal bank interleaving within save device enabled
804 */
805
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200806#define CONFIG_SYS_OR4_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM2_SIZE) |\
wdenkfe8c2802002-11-03 00:38:21 +0000807 ORxS_BPD_4 |\
808 ORxS_ROWST_PBI0_A10 |\
809 ORxS_NUMR_12)
810
811
812/*-----------------------------------------------------------------------
813 * LSDMR - Local Bus SDRAM Mode Register
814 * Ref: Section 10.3.4 on page 10-24
815 *-----------------------------------------------------------------------
816 */
817
818/* With a 16 MB onboard SDRAM, the LSDMR is configured as follows:
819 *
820 * - Page Based Interleaving,
821 * - Refresh Enable,
822 * - Normal Operation
823 * - Address Multiplexing where A5 is output on A13 pin
824 * (A6 on A15, and so on),
825 * - use address pins A15-A17 as bank select,
826 * - A11 is output on SDA10 during an ACTIVATE command,
827 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
828 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
829 * is 2 clocks,
830 * - earliest timing for READ/WRITE command after ACTIVATE command is
831 * 2 clocks,
832 * - SDRAM burst length is 8
833 * - earliest timing for PRECHARGE after last data was read is 1 clock,
834 * - earliest timing for PRECHARGE after last data was written is 1 clock,
835 * - External Address Multiplexing disabled
836 * - CAS Latency is 2.
837 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200838#define CONFIG_SYS_LSDMR (PSDMR_RFEN |\
wdenkfe8c2802002-11-03 00:38:21 +0000839 PSDMR_SDAM_A13_IS_A5 |\
840 PSDMR_BSMA_A15_A17 |\
841 PSDMR_SDA10_PBI0_A11 |\
842 PSDMR_RFRC_7_CLK |\
843 PSDMR_PRETOACT_2W |\
844 PSDMR_ACTTORW_2W |\
845 PSDMR_BL |\
846 PSDMR_LDOTOPRE_1C |\
847 PSDMR_WRC_1C |\
848 PSDMR_CL_2)
849
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200850#define CONFIG_SYS_LSRT 0x0e
wdenkfe8c2802002-11-03 00:38:21 +0000851
852/*-----------------------------------------------------------------------
853 * BR5 - Base Register
854 * Ref: Section 10.3.1 on page 10-14
855 * OR5 - Option Register
856 * Ref: Section 10.3.2 on page 10-16
857 *-----------------------------------------------------------------------
858 */
859
860/*
861 * Bank 5 EEProm and Mailbox
862 *
863 * The EEPROM and mailbox live on the same chip select.
864 * the eeprom is selected if the MSb of the address is set and the mailbox is
865 * selected if the MSb of the address is clear.
866 *
867 */
868
869/* BR5 is configured as follows:
870 *
871 * - Base address of 0x32000000/0xF2000000
872 * - 8 bit
873 * - Data error checking disabled
874 * - Read/Write access
875 * - GPCM 60x Bus
876 * - SDRAM local bus
877 * - No data pipelining is done
878 * - Valid
879 */
880
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200881#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_MAILBOX_BASE & BRx_BA_MSK) |\
wdenkfe8c2802002-11-03 00:38:21 +0000882 BRx_PS_8 |\
883 BRx_DECC_NONE |\
884 BRx_MS_GPCM_P |\
885 BRx_V)
886/* OR5 is configured as follows
887 * - buffer control enabled
888 * - chip select negated normally
889 * - CS output 1/2 clock after address
890 * - 15 wait states
891 * - *PSDVAL is generated internally by the memory controller
892 * unless *GTA is asserted earlier externally.
893 * - Relaxed timing is generated by the GPCM for accesses
894 * initiated to this memory region.
895 * - One idle clock is inserted between a read access from the
896 * current bank and the next access.
897 */
898
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200899#define CONFIG_SYS_OR5_PRELIM ((P2SZ_TO_AM(CONFIG_SYS_MAILBOX_SIZE) & ~0x80000000) |\
wdenkfe8c2802002-11-03 00:38:21 +0000900 ORxG_ACS_DIV2 |\
901 ORxG_SCY_15_CLK |\
902 ORxG_TRLX |\
903 ORxG_EHTR)
904
905/*-----------------------------------------------------------------------
906 * BR6 - Base Register
907 * Ref: Section 10.3.1 on page 10-14
908 * OR6 - Option Register
909 * Ref: Section 10.3.2 on page 10-18
910 *-----------------------------------------------------------------------
911 */
912
913/* Bank 6 - I/O select
914 *
915 */
916
917/* BR6 is configured as follows:
918 *
919 * - Base address of 0xE0000000
920 * - 16 bit port size
921 * - Data errors checking is disabled
922 * - Read and write access
923 * - GPCM 60x bus
924 * - Access are handled by the memory controller according to MSEL
925 * - Not used for atomic operations
926 * - No data pipelining is done
927 * - Valid
928 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200929#define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_IOSELECT_BASE & BRx_BA_MSK) |\
wdenkfe8c2802002-11-03 00:38:21 +0000930 BRx_PS_16 |\
931 BRx_MS_GPCM_P |\
932 BRx_V)
933
934/* OR6 is configured as follows
935 * - buffer control enabled
936 * - chip select negated normally
937 * - CS output 1/2 clock after address
938 * - 15 wait states
939 * - *PSDVAL is generated internally by the memory controller
940 * unless *GTA is asserted earlier externally.
941 * - Relaxed timing is generated by the GPCM for accesses
942 * initiated to this memory region.
943 * - One idle clock is inserted between a read access from the
944 * current bank and the next access.
945 */
946
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200947#define CONFIG_SYS_OR6_PRELIM (MEG_TO_AM(CONFIG_SYS_IOSELECT_SIZE) |\
wdenkfe8c2802002-11-03 00:38:21 +0000948 ORxG_ACS_DIV2 |\
949 ORxG_SCY_15_CLK |\
950 ORxG_TRLX |\
951 ORxG_EHTR)
952
953
954/*-----------------------------------------------------------------------
955 * BR7 - Base Register
956 * Ref: Section 10.3.1 on page 10-14
957 * OR7 - Option Register
958 * Ref: Section 10.3.2 on page 10-18
959 *-----------------------------------------------------------------------
960 */
961
962/* Bank 7 - LEDs and switches
963 *
964 * LEDs are at 0x00001 (write only)
965 * switches are at 0x00001 (read only)
966 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200967#ifdef CONFIG_SYS_LED_BASE
wdenkfe8c2802002-11-03 00:38:21 +0000968
969/* BR7 is configured as follows:
970 *
971 * - Base address of 0xA0000000
972 * - 8 bit port size
973 * - Data errors checking is disabled
974 * - Read and write access
975 * - GPCM 60x bus
976 * - Access are handled by the memory controller according to MSEL
977 * - Not used for atomic operations
978 * - No data pipelining is done
979 * - Valid
980 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200981#define CONFIG_SYS_BR7_PRELIM ((CONFIG_SYS_LED_BASE & BRx_BA_MSK) |\
wdenkfe8c2802002-11-03 00:38:21 +0000982 BRx_PS_8 |\
983 BRx_DECC_NONE |\
984 BRx_MS_GPCM_P |\
985 BRx_V)
986
987/* OR7 is configured as follows:
988 *
989 * - 1 byte
990 * - *BCTL0 is asserted upon access to the current memory bank
991 * - *CW / *WE are negated a quarter of a clock earlier
992 * - *CS is output at the same time as the address lines
993 * - Uses a clock cycle length of 15
994 * - *PSDVAL is generated internally by the memory controller
995 * unless *GTA is asserted earlier externally.
996 * - Relaxed timing is generated by the GPCM for accesses
997 * initiated to this memory region.
998 * - One idle clock is inserted between a read access from the
999 * current bank and the next access.
1000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001001#define CONFIG_SYS_OR7_PRELIM (ORxG_AM_MSK |\
wdenkfe8c2802002-11-03 00:38:21 +00001002 ORxG_CSNT |\
1003 ORxG_ACS_DIV1 |\
1004 ORxG_SCY_15_CLK |\
1005 ORxG_TRLX |\
1006 ORxG_EHTR)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001007#endif /* CONFIG_SYS_LED_BASE */
wdenkfe8c2802002-11-03 00:38:21 +00001008#endif /* __CONFIG_H */