| Thomas Chou | 7e812f2 | 2010-04-17 23:34:40 +0800 | [diff] [blame] | 1 | #ifndef __ASM_NIOS2_DMA_MAPPING_H |
| 2 | #define __ASM_NIOS2_DMA_MAPPING_H |
| 3 | |
| Thomas Chou | 7cacb64 | 2015-10-18 20:03:53 +0800 | [diff] [blame] | 4 | #include <memalign.h> |
| 5 | #include <asm/io.h> |
| Thomas Chou | 7e812f2 | 2010-04-17 23:34:40 +0800 | [diff] [blame] | 6 | |
| Thomas Chou | 7cacb64 | 2015-10-18 20:03:53 +0800 | [diff] [blame] | 7 | /* |
| 8 | * dma_alloc_coherent() return cache-line aligned allocation which is mapped |
| 9 | * to uncached io region. |
| 10 | */ |
| Thomas Chou | 7e812f2 | 2010-04-17 23:34:40 +0800 | [diff] [blame] | 11 | static inline void *dma_alloc_coherent(size_t len, unsigned long *handle) |
| 12 | { |
| Thomas Chou | 7cacb64 | 2015-10-18 20:03:53 +0800 | [diff] [blame] | 13 | unsigned long addr = (unsigned long)malloc_cache_aligned(len); |
| Thomas Chou | 7e812f2 | 2010-04-17 23:34:40 +0800 | [diff] [blame] | 14 | |
| Thomas Chou | 7cacb64 | 2015-10-18 20:03:53 +0800 | [diff] [blame] | 15 | if (!addr) |
| 16 | return NULL; |
| 17 | |
| 18 | invalidate_dcache_range(addr, addr + len); |
| 19 | if (handle) |
| 20 | *handle = addr; |
| 21 | |
| Thomas Chou | 7be35dd | 2015-11-14 11:34:09 +0800 | [diff] [blame] | 22 | return map_physmem(addr, len, MAP_NOCACHE); |
| Thomas Chou | 7cacb64 | 2015-10-18 20:03:53 +0800 | [diff] [blame] | 23 | } |
| Thomas Chou | 7e812f2 | 2010-04-17 23:34:40 +0800 | [diff] [blame] | 24 | #endif /* __ASM_NIOS2_DMA_MAPPING_H */ |