blob: d2bf3049f10a1a810803214fb48da5be61099903 [file] [log] [blame]
Kumar Gala143b5182008-01-17 01:44:34 -06001/*
2 * Copyright 2008 Freescale Semiconductor, Inc.
3 *
4 * (C) Copyright 2000
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Kumar Gala143b5182008-01-17 01:44:34 -06008 */
9
10#include <common.h>
11#include <asm/mmu.h>
12
13struct fsl_e_tlb_entry tlb_table[] = {
14 /* TLB 0 - for temp stack in cache */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020015 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
Kumar Gala143b5182008-01-17 01:44:34 -060016 MAS3_SX|MAS3_SW|MAS3_SR, 0,
17 0, 0, BOOKE_PAGESZ_4K, 0),
Paul Gortmakerded58f42009-09-23 17:30:57 -040018 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
19 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
Kumar Gala143b5182008-01-17 01:44:34 -060020 MAS3_SX|MAS3_SW|MAS3_SR, 0,
21 0, 0, BOOKE_PAGESZ_4K, 0),
Paul Gortmakerded58f42009-09-23 17:30:57 -040022 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
23 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
Kumar Gala143b5182008-01-17 01:44:34 -060024 MAS3_SX|MAS3_SW|MAS3_SR, 0,
25 0, 0, BOOKE_PAGESZ_4K, 0),
Paul Gortmakerded58f42009-09-23 17:30:57 -040026 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
27 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
Kumar Gala143b5182008-01-17 01:44:34 -060028 MAS3_SX|MAS3_SW|MAS3_SR, 0,
29 0, 0, BOOKE_PAGESZ_4K, 0),
30
31 /*
Paul Gortmaker9b3ba242009-09-18 19:08:41 -040032 * TLB 0: 64M Non-cacheable, guarded
Paul Gortmaker3fd673c2011-12-30 23:53:07 -050033 * 0xfc000000 56M unused
Paul Gortmaker9b3ba242009-09-18 19:08:41 -040034 * 0xff800000 8M boot FLASH
Paul Gortmaker3fd673c2011-12-30 23:53:07 -050035 * .... or ....
36 * 0xfc000000 64M user flash
37 *
Kumar Gala143b5182008-01-17 01:44:34 -060038 * Out of reset this entry is only 4K.
39 */
Paul Gortmaker3fd673c2011-12-30 23:53:07 -050040 SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000,
Kumar Gala143b5182008-01-17 01:44:34 -060041 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
Paul Gortmaker9b3ba242009-09-18 19:08:41 -040042 0, 0, BOOKE_PAGESZ_64M, 1),
Kumar Gala143b5182008-01-17 01:44:34 -060043
44 /*
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -040045 * TLB 1: 1G Non-cacheable, guarded
46 * 0x80000000 512M PCI1 MEM
47 * 0xa0000000 512M PCIe MEM
Kumar Gala143b5182008-01-17 01:44:34 -060048 */
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -040049 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
Kumar Gala143b5182008-01-17 01:44:34 -060050 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -040051 0, 1, BOOKE_PAGESZ_1G, 1),
Kumar Gala143b5182008-01-17 01:44:34 -060052
53 /*
Becky Bruce38dba0c2010-12-17 17:17:56 -060054 * TLB 2: 64M Non-cacheable, guarded
Kumar Gala143b5182008-01-17 01:44:34 -060055 * 0xe0000000 1M CCSRBAR
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -040056 * 0xe2000000 8M PCI1 IO
57 * 0xe2800000 8M PCIe IO
Kumar Gala143b5182008-01-17 01:44:34 -060058 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
Kumar Gala143b5182008-01-17 01:44:34 -060060 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
Becky Bruce38dba0c2010-12-17 17:17:56 -060061 0, 2, BOOKE_PAGESZ_64M, 1),
Kumar Gala143b5182008-01-17 01:44:34 -060062
Paul Gortmaker7e44f2b2011-12-30 23:53:10 -050063#ifdef CONFIG_SYS_LBC_SDRAM_BASE
Kumar Gala143b5182008-01-17 01:44:34 -060064 /*
Becky Bruce38dba0c2010-12-17 17:17:56 -060065 * TLB 3: 64M Cacheable, non-guarded
Paul Gortmaker11d5a622009-09-20 20:36:04 -040066 * 0xf0000000 64M LBC SDRAM First half
Kumar Gala143b5182008-01-17 01:44:34 -060067 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068 SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
York Sun316f0d02017-12-05 10:57:54 -080069 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
Becky Bruce38dba0c2010-12-17 17:17:56 -060070 0, 3, BOOKE_PAGESZ_64M, 1),
Kumar Gala143b5182008-01-17 01:44:34 -060071
72 /*
Becky Bruce38dba0c2010-12-17 17:17:56 -060073 * TLB 4: 64M Cacheable, non-guarded
Paul Gortmaker11d5a622009-09-20 20:36:04 -040074 * 0xf4000000 64M LBC SDRAM Second half
75 */
76 SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
77 CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
York Sun316f0d02017-12-05 10:57:54 -080078 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
Becky Bruce38dba0c2010-12-17 17:17:56 -060079 0, 4, BOOKE_PAGESZ_64M, 1),
Paul Gortmaker7e44f2b2011-12-30 23:53:10 -050080#endif
Paul Gortmaker11d5a622009-09-20 20:36:04 -040081
82 /*
Becky Bruce38dba0c2010-12-17 17:17:56 -060083 * TLB 5: 16M Cacheable, non-guarded
Kumar Gala143b5182008-01-17 01:44:34 -060084 * 0xf8000000 1M 7-segment LED display
85 * 0xf8100000 1M User switches
86 * 0xf8300000 1M Board revision
87 * 0xf8b00000 1M EEPROM
88 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089 SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE,
Kumar Gala143b5182008-01-17 01:44:34 -060090 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
Becky Bruce38dba0c2010-12-17 17:17:56 -060091 0, 5, BOOKE_PAGESZ_16M, 1),
Paul Gortmaker9b3ba242009-09-18 19:08:41 -040092
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -050093#ifndef CONFIG_SYS_ALT_BOOT
Paul Gortmaker9b3ba242009-09-18 19:08:41 -040094 /*
Paul Gortmaker3fd673c2011-12-30 23:53:07 -050095 * TLB 6: 64M Non-cacheable, guarded
96 * 0xec000000 64M 64MB user FLASH
Paul Gortmaker9b3ba242009-09-18 19:08:41 -040097 */
98 SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
99 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
Paul Gortmaker3fd673c2011-12-30 23:53:07 -0500100 0, 6, BOOKE_PAGESZ_64M, 1),
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500101#else
102 /*
103 * TLB 6: 4M Non-cacheable, guarded
104 * 0xef800000 4M 1st 1/2 8MB soldered FLASH
105 */
106 SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
107 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
108 0, 6, BOOKE_PAGESZ_4M, 1),
109
110 /*
111 * TLB 7: 4M Non-cacheable, guarded
112 * 0xefc00000 4M 2nd half 8MB soldered FLASH
113 */
114 SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000,
115 CONFIG_SYS_ALT_FLASH + 0x400000,
116 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
117 0, 7, BOOKE_PAGESZ_4M, 1),
118#endif
Paul Gortmaker9b3ba242009-09-18 19:08:41 -0400119
Kumar Gala143b5182008-01-17 01:44:34 -0600120};
121
122int num_tlb_entries = ARRAY_SIZE(tlb_table);