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wdenkfe8c2802002-11-03 00:38:21 +00001/*
2 * (C) Copyright 2000
3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
4 *
5 * (C) Copyright 2000
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * (C) Copyright 2001
10 * Advent Networks, Inc. <http://www.adventnetworks.com>
11 * Jay Monkman <jtm@smoothsmoothie.com>
12 *
13 * Configuration settings for the WindRiver SBC8260 board.
14 * See http://www.windriver.com/products/html/sbc8260.html
15 *
16 * See file CREDITS for list of people who contributed to this
17 * project.
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * MA 02111-1307 USA
33 */
34
35#ifndef __CONFIG_H
36#define __CONFIG_H
37
wdenkfe8c2802002-11-03 00:38:21 +000038#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
39
wdenk78137c32003-09-15 18:00:00 +000040#undef CONFIG_LOGBUFFER /* External logbuffer support */
41
wdenkfe8c2802002-11-03 00:38:21 +000042/*****************************************************************************
43 *
44 * These settings must match the way _your_ board is set up
45 *
46 *****************************************************************************/
47
48/* What is the oscillator's (UX2) frequency in Hz? */
49#define CONFIG_8260_CLKIN 66666600
50
51/*-----------------------------------------------------------------------
52 * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
53 *-----------------------------------------------------------------------
54 * What should MODCK_H be? It is dependent on the oscillator
55 * frequency, MODCK[1-3], and desired CPM and core frequencies.
56 * Here are some example values (all frequencies are in MHz):
57 *
58 * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
59 * ------- ---------- --- --- ---- ----- ----- -----
60 * 0x1 0x5 33 100 133 Open Close Open
61 * 0x1 0x6 33 100 166 Open Open Close
62 * 0x1 0x7 33 100 200 Open Open Open
63 *
64 * 0x2 0x2 33 133 133 Close Open Close
65 * 0x2 0x3 33 133 166 Close Open Open
66 * 0x2 0x4 33 133 200 Open Close Close
67 * 0x2 0x5 33 133 233 Open Close Open
68 * 0x2 0x6 33 133 266 Open Open Close
69 *
70 * 0x5 0x5 66 133 133 Open Close Open
71 * 0x5 0x6 66 133 166 Open Open Close
72 * 0x5 0x7 66 133 200 Open Open Open
73 * 0x6 0x0 66 133 233 Close Close Close
74 * 0x6 0x1 66 133 266 Close Close Open
75 * 0x6 0x2 66 133 300 Close Open Close
76 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_SBC_MODCK_H 0x05
wdenkfe8c2802002-11-03 00:38:21 +000078
79/* Define this if you want to boot from 0x00000100. If you don't define
80 * this, you will need to program the bootloader to 0xfff00000, and
81 * get the hardware reset config words at 0xfe000000. The simplest
82 * way to do that is to program the bootloader at both addresses.
83 * It is suggested that you just let U-Boot live at 0x00000000.
84 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CONFIG_SYS_SBC_BOOT_LOW 1
wdenkfe8c2802002-11-03 00:38:21 +000086
87/* What should the base address of the main FLASH be and how big is
88 * it (in MBytes)? This must contain TEXT_BASE from board/sacsng/config.mk
89 * The main FLASH is whichever is connected to *CS0.
90 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_FLASH0_BASE 0x40000000
92#define CONFIG_SYS_FLASH0_SIZE 2
wdenkfe8c2802002-11-03 00:38:21 +000093
94/* What should the base address of the secondary FLASH be and how big
95 * is it (in Mbytes)? The secondary FLASH is whichever is connected
96 * to *CS6.
97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_FLASH1_BASE 0x60000000
99#define CONFIG_SYS_FLASH1_SIZE 2
wdenkfe8c2802002-11-03 00:38:21 +0000100
101/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
102 */
103#define CONFIG_VERY_BIG_RAM 1
104
105/* What should be the base address of SDRAM DIMM and how big is
106 * it (in Mbytes)? This will normally auto-configure via the SPD.
107*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_SDRAM0_BASE 0x00000000
109#define CONFIG_SYS_SDRAM0_SIZE 64
wdenkfe8c2802002-11-03 00:38:21 +0000110
111/*
112 * Memory map example with 64 MB DIMM:
113 *
114 * 0x0000 0000 Exception Vector code, 8k
115 * :
116 * 0x0000 1FFF
117 * 0x0000 2000 Free for Application Use
118 * :
119 * :
120 *
121 * :
122 * :
123 * 0x03F5 FF30 Monitor Stack (Growing downward)
124 * Monitor Stack Buffer (0x80)
125 * 0x03F5 FFB0 Board Info Data
126 * 0x03F6 0000 Malloc Arena
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200127 * : CONFIG_ENV_SECT_SIZE, 16k
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128 * : CONFIG_SYS_MALLOC_LEN, 128k
wdenkfe8c2802002-11-03 00:38:21 +0000129 * 0x03FC 0000 RAM Copy of Monitor Code
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130 * : CONFIG_SYS_MONITOR_LEN, 256k
131 * 0x03FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
wdenkfe8c2802002-11-03 00:38:21 +0000132 */
133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
135 CONFIG_SYS_POST_CPU)
wdenkfe8c2802002-11-03 00:38:21 +0000136
137
138/*
139 * select serial console configuration
140 *
141 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
142 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
143 * for SCC).
144 *
145 * if CONFIG_CONS_NONE is defined, then the serial console routines must
146 * defined elsewhere.
147 */
148#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
149#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
150#undef CONFIG_CONS_NONE /* define if console on neither */
151#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
152
153/*
154 * select ethernet configuration
155 *
156 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
157 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
158 * for FCC)
159 *
160 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -0500161 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenkfe8c2802002-11-03 00:38:21 +0000162 */
163
164#undef CONFIG_ETHER_ON_SCC
165#define CONFIG_ETHER_ON_FCC
166#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
167
168#ifdef CONFIG_ETHER_ON_SCC
169#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
170#endif /* CONFIG_ETHER_ON_SCC */
171
172#ifdef CONFIG_ETHER_ON_FCC
173#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
wdenk78137c32003-09-15 18:00:00 +0000174#undef CONFIG_ETHER_LOOPBACK_TEST /* Ethernet external loopback test */
wdenkfe8c2802002-11-03 00:38:21 +0000175#define CONFIG_MII /* MII PHY management */
176#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
177/*
178 * Port pins used for bit-banged MII communictions (if applicable).
179 */
180
181#define MDIO_PORT 2 /* Port A=0, B=1, C=2, D=3 */
Luigi 'Comio' Mantellinibe225442009-10-10 12:42:22 +0200182#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
183 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
184#define MDC_DECLARE MDIO_DECLARE
185
wdenkfe8c2802002-11-03 00:38:21 +0000186#define MDIO_ACTIVE (iop->pdir |= 0x40000000)
187#define MDIO_TRISTATE (iop->pdir &= ~0x40000000)
188#define MDIO_READ ((iop->pdat & 0x40000000) != 0)
189
190#define MDIO(bit) if(bit) iop->pdat |= 0x40000000; \
191 else iop->pdat &= ~0x40000000
192
193#define MDC(bit) if(bit) iop->pdat |= 0x80000000; \
194 else iop->pdat &= ~0x80000000
195
196#define MIIDELAY udelay(50)
197#endif /* CONFIG_ETHER_ON_FCC */
198
199#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
200
201/*
202 * - RX clk is CLK11
203 * - TX clk is CLK12
204 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
wdenkfe8c2802002-11-03 00:38:21 +0000206
207#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
208
209/*
210 * - Rx-CLK is CLK13
211 * - Tx-CLK is CLK14
212 * - Select bus for bd/buffers (see 28-13)
213 * - Enable Full Duplex in FSMR
214 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
216# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
217# define CONFIG_SYS_CPMFCR_RAMTYPE 0
218# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
wdenkfe8c2802002-11-03 00:38:21 +0000219
220#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
221
222#define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progress enabled */
223
224/*
225 * Configure for RAM tests.
226 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#undef CONFIG_SYS_DRAM_TEST /* calls other tests in board.c */
wdenkfe8c2802002-11-03 00:38:21 +0000228
229
230/*
231 * Status LED for power up status feedback.
232 */
233#define CONFIG_STATUS_LED 1 /* Status LED enabled */
234
235#define STATUS_LED_PAR im_ioport.iop_ppara
236#define STATUS_LED_DIR im_ioport.iop_pdira
237#define STATUS_LED_ODR im_ioport.iop_podra
238#define STATUS_LED_DAT im_ioport.iop_pdata
239
240#define STATUS_LED_BIT 0x00000800 /* LED 0 is on PA.20 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define STATUS_LED_PERIOD (CONFIG_SYS_HZ)
wdenkfe8c2802002-11-03 00:38:21 +0000242#define STATUS_LED_STATE STATUS_LED_OFF
243#define STATUS_LED_BIT1 0x00001000 /* LED 1 is on PA.19 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ)
wdenkfe8c2802002-11-03 00:38:21 +0000245#define STATUS_LED_STATE1 STATUS_LED_OFF
246#define STATUS_LED_BIT2 0x00002000 /* LED 2 is on PA.18 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ/2)
wdenkfe8c2802002-11-03 00:38:21 +0000248#define STATUS_LED_STATE2 STATUS_LED_ON
249
250#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
251
252#define STATUS_LED_YELLOW 0
253#define STATUS_LED_GREEN 1
254#define STATUS_LED_RED 2
255#define STATUS_LED_BOOT 1
256
257
258/*
wdenk1d0350e2002-11-11 21:14:20 +0000259 * Select SPI support configuration
wdenkfe8c2802002-11-03 00:38:21 +0000260 */
wdenk1d0350e2002-11-11 21:14:20 +0000261#define CONFIG_SOFT_SPI /* Enable SPI driver */
262#define MAX_SPI_BYTES 4 /* Maximum number of bytes we can handle */
wdenk8bde7f72003-06-27 21:31:46 +0000263#undef DEBUG_SPI /* Disable SPI debugging */
264
wdenkfe8c2802002-11-03 00:38:21 +0000265/*
266 * Software (bit-bang) SPI driver configuration
267 */
268#ifdef CONFIG_SOFT_SPI
269
270/*
271 * Software (bit-bang) SPI driver configuration
272 */
273#define I2C_SCLK 0x00002000 /* PD 18: Shift clock */
274#define I2C_MOSI 0x00004000 /* PD 17: Master Out, Slave In */
275#define I2C_MISO 0x00008000 /* PD 16: Master In, Slave Out */
276
277#undef SPI_INIT /* no port initialization needed */
278#define SPI_READ ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0)
Wolfgang Denkced209c2008-07-03 22:39:21 +0200279#define SPI_SDA(bit) do { \
280 if(bit) immr->im_ioport.iop_pdatd |= I2C_MOSI; \
281 else immr->im_ioport.iop_pdatd &= ~I2C_MOSI; \
282 } while (0)
283#define SPI_SCL(bit) do { \
284 if(bit) immr->im_ioport.iop_pdatd |= I2C_SCLK; \
285 else immr->im_ioport.iop_pdatd &= ~I2C_SCLK; \
286 } while (0)
wdenk1d0350e2002-11-11 21:14:20 +0000287#define SPI_DELAY /* No delay is needed */
wdenkfe8c2802002-11-03 00:38:21 +0000288#endif /* CONFIG_SOFT_SPI */
289
290
291/*
292 * select I2C support configuration
293 *
294 * Supported configurations are {none, software, hardware} drivers.
295 * If the software driver is chosen, there are some additional
296 * configuration items that the driver uses to drive the port pins.
297 */
298#undef CONFIG_HARD_I2C /* I2C with hardware support */
299#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
301#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenkfe8c2802002-11-03 00:38:21 +0000302
303/*
304 * Software (bit-bang) I2C driver configuration
305 */
306#ifdef CONFIG_SOFT_I2C
307#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
308#define I2C_ACTIVE (iop->pdir |= 0x00010000)
309#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
310#define I2C_READ ((iop->pdat & 0x00010000) != 0)
311#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
312 else iop->pdat &= ~0x00010000
313#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
314 else iop->pdat &= ~0x00020000
315#define I2C_DELAY udelay(20) /* 1/4 I2C clock duration */
316#endif /* CONFIG_SOFT_I2C */
317
318/* Define this to reserve an entire FLASH sector for
319 * environment variables. Otherwise, the environment will be
320 * put in the same sector as U-Boot, and changing variables
321 * will erase U-Boot temporarily
322 */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200323#define CONFIG_ENV_IN_OWN_SECT 1
wdenkfe8c2802002-11-03 00:38:21 +0000324
325/* Define this to contain any number of null terminated strings that
326 * will be part of the default enviroment compiled into the boot image.
327 */
328#define CONFIG_EXTRA_ENV_SETTINGS \
wdenk78137c32003-09-15 18:00:00 +0000329"quiet=0\0" \
330"serverip=192.168.123.205\0" \
wdenkfe8c2802002-11-03 00:38:21 +0000331"ipaddr=192.168.123.203\0" \
332"checkhostname=VR8500\0" \
333"reprog="\
wdenk78137c32003-09-15 18:00:00 +0000334 "bootp; " \
wdenkfe8c2802002-11-03 00:38:21 +0000335 "tftpboot 0x140000 /bdi2000/u-boot.bin; " \
336 "protect off 60000000 6003FFFF; " \
337 "erase 60000000 6003FFFF; " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100338 "cp.b 140000 60000000 ${filesize}; " \
wdenkfe8c2802002-11-03 00:38:21 +0000339 "protect on 60000000 6003FFFF\0" \
340"copyenv="\
341 "protect off 60040000 6004FFFF; " \
342 "erase 60040000 6004FFFF; " \
343 "cp.b 40040000 60040000 10000; " \
344 "protect on 60040000 6004FFFF\0" \
345"copyprog="\
346 "protect off 60000000 6003FFFF; " \
347 "erase 60000000 6003FFFF; " \
348 "cp.b 40000000 60000000 40000; " \
349 "protect on 60000000 6003FFFF\0" \
350"zapenv="\
351 "protect off 40040000 4004FFFF; " \
352 "erase 40040000 4004FFFF; " \
353 "protect on 40040000 4004FFFF\0" \
354"zapotherenv="\
355 "protect off 60040000 6004FFFF; " \
356 "erase 60040000 6004FFFF; " \
357 "protect on 60040000 6004FFFF\0" \
358"root-on-initrd="\
359 "setenv bootcmd "\
360 "version\\;" \
361 "echo\\;" \
362 "bootp\\;" \
363 "setenv bootargs root=/dev/ram0 rw quiet " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100364 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
wdenkfe8c2802002-11-03 00:38:21 +0000365 "run boot-hook\\;" \
366 "bootm\0" \
367"root-on-initrd-debug="\
368 "setenv bootcmd "\
369 "version\\;" \
370 "echo\\;" \
371 "bootp\\;" \
372 "setenv bootargs root=/dev/ram0 rw debug " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100373 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
wdenkfe8c2802002-11-03 00:38:21 +0000374 "run debug-hook\\;" \
375 "run boot-hook\\;" \
376 "bootm\0" \
377"root-on-nfs="\
378 "setenv bootcmd "\
379 "version\\;" \
380 "echo\\;" \
381 "bootp\\;" \
382 "setenv bootargs root=/dev/nfs rw quiet " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100383 "nfsroot=\\${serverip}:\\${rootpath} " \
384 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
wdenkfe8c2802002-11-03 00:38:21 +0000385 "run boot-hook\\;" \
386 "bootm\0" \
387"root-on-nfs-debug="\
388 "setenv bootcmd "\
389 "version\\;" \
390 "echo\\;" \
391 "bootp\\;" \
392 "setenv bootargs root=/dev/nfs rw debug " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100393 "nfsroot=\\${serverip}:\\${rootpath} " \
394 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
wdenkfe8c2802002-11-03 00:38:21 +0000395 "run debug-hook\\;" \
396 "run boot-hook\\;" \
397 "bootm\0" \
398"debug-checkout="\
399 "setenv checkhostname;" \
400 "setenv ethaddr 00:09:70:00:00:01;" \
401 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100402 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} debug " \
403 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenkfe8c2802002-11-03 00:38:21 +0000404 "run debug-hook;" \
405 "run boot-hook;" \
406 "bootm\0" \
407"debug-hook="\
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100408 "echo ipaddr ${ipaddr};" \
409 "echo serverip ${serverip};" \
410 "echo gatewayip ${gatewayip};" \
411 "echo netmask ${netmask};" \
412 "echo hostname ${hostname}\0" \
wdenkfe8c2802002-11-03 00:38:21 +0000413"ana=run adc ; run dac\0" \
414"adc=run adc-12 ; run adc-34\0" \
Peter Tyser0f89c542009-04-18 22:34:03 -0500415"adc-12=echo ### ADC-12 ; i2c md e 81 e\0" \
416"adc-34=echo ### ADC-34 ; i2c md f 81 e\0" \
417"dac=echo ### DAC ; i2c md 11 81 5\0" \
wdenk78137c32003-09-15 18:00:00 +0000418"boot-hook=echo\0"
wdenkfe8c2802002-11-03 00:38:21 +0000419
420/* What should the console's baud rate be? */
421#define CONFIG_BAUDRATE 9600
422
423/* Ethernet MAC address */
424#define CONFIG_ETHADDR 00:09:70:00:00:00
425
426/* The default Ethernet MAC address can be overwritten just once */
427#ifdef CONFIG_ETHADDR
428#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
429#endif
430
431/*
432 * Define this to do some miscellaneous board-specific initialization.
433 */
434#define CONFIG_MISC_INIT_R
435
436/* Set to a positive value to delay for running BOOTCOMMAND */
437#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
438
439/* Be selective on what keys can delay or stop the autoboot process
440 * To stop use: " "
441 */
442#define CONFIG_AUTOBOOT_KEYED
Stefan Roesef2302d42008-08-06 14:05:38 +0200443#define CONFIG_AUTOBOOT_PROMPT "Autobooting...\n"
wdenkfe8c2802002-11-03 00:38:21 +0000444#define CONFIG_AUTOBOOT_STOP_STR " "
445#undef CONFIG_AUTOBOOT_DELAY_STR
446#define CONFIG_ZERO_BOOTDELAY_CHECK
447#define DEBUG_BOOTKEYS 0
448
449/* Define a command string that is automatically executed when no character
450 * is read on the console interface withing "Boot Delay" after reset.
451 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200452#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
wdenkb79a11c2004-03-25 15:14:43 +0000453#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
wdenkfe8c2802002-11-03 00:38:21 +0000454
wdenk42dfe7a2004-03-14 22:25:36 +0000455#ifdef CONFIG_BOOT_ROOT_INITRD
wdenkfe8c2802002-11-03 00:38:21 +0000456#define CONFIG_BOOTCOMMAND \
457 "version;" \
458 "echo;" \
459 "bootp;" \
460 "setenv bootargs root=/dev/ram0 rw quiet " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100461 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenkfe8c2802002-11-03 00:38:21 +0000462 "run boot-hook;" \
463 "bootm"
464#endif /* CONFIG_BOOT_ROOT_INITRD */
465
wdenk42dfe7a2004-03-14 22:25:36 +0000466#ifdef CONFIG_BOOT_ROOT_NFS
wdenkfe8c2802002-11-03 00:38:21 +0000467#define CONFIG_BOOTCOMMAND \
468 "version;" \
469 "echo;" \
470 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100471 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} quiet " \
472 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenkfe8c2802002-11-03 00:38:21 +0000473 "run boot-hook;" \
474 "bootm"
475#endif /* CONFIG_BOOT_ROOT_NFS */
476
477#define CONFIG_BOOTP_RANDOM_DELAY /* Randomize the BOOTP retry delay */
478
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500479/*
480 * BOOTP options
wdenkfe8c2802002-11-03 00:38:21 +0000481 */
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500482#define CONFIG_BOOTP_SUBNETMASK
483#define CONFIG_BOOTP_GATEWAY
484#define CONFIG_BOOTP_HOSTNAME
485#define CONFIG_BOOTP_BOOTPATH
486#define CONFIG_BOOTP_BOOTFILESIZE
487#define CONFIG_BOOTP_DNS
488#define CONFIG_BOOTP_DNS2
489#define CONFIG_BOOTP_SEND_HOSTNAME
490
wdenkfe8c2802002-11-03 00:38:21 +0000491
492/* undef this to save memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200493#define CONFIG_SYS_LONGHELP
wdenkfe8c2802002-11-03 00:38:21 +0000494
495/* Monitor Command Prompt */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200496#define CONFIG_SYS_PROMPT "=> "
wdenkfe8c2802002-11-03 00:38:21 +0000497
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200498#undef CONFIG_SYS_HUSH_PARSER
499#ifdef CONFIG_SYS_HUSH_PARSER
500#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenkfe8c2802002-11-03 00:38:21 +0000501#endif
502
wdenk1d0350e2002-11-11 21:14:20 +0000503/* When CONFIG_TIMESTAMP is selected, the timestamp (date and time)
504 * of an image is printed by image commands like bootm or iminfo.
505 */
506#define CONFIG_TIMESTAMP
507
wdenk42d1f032003-10-15 23:53:47 +0000508/* If this variable is defined, an environment variable named "ver"
wdenk78137c32003-09-15 18:00:00 +0000509 * is created by U-Boot showing the U-Boot version.
510 */
511#define CONFIG_VERSION_VARIABLE
512
Jon Loeliger46da1e92007-07-04 22:33:30 -0500513
514/*
515 * Command line configuration.
516 */
517#include <config_cmd_default.h>
518
519#define CONFIG_CMD_ELF
520#define CONFIG_CMD_ASKENV
521#define CONFIG_CMD_I2C
522#define CONFIG_CMD_SPI
523#define CONFIG_CMD_SDRAM
524#define CONFIG_CMD_REGINFO
525#define CONFIG_CMD_IMMAP
526#define CONFIG_CMD_IRQ
527#define CONFIG_CMD_PING
528
529#undef CONFIG_CMD_KGDB
530
wdenkfe8c2802002-11-03 00:38:21 +0000531#ifdef CONFIG_ETHER_ON_FCC
Jon Loeliger46da1e92007-07-04 22:33:30 -0500532#define CONFIG_CMD_MII
533#endif
534
wdenkfe8c2802002-11-03 00:38:21 +0000535
536/* Where do the internal registers live? */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200537#define CONFIG_SYS_IMMR 0xF0000000
wdenkfe8c2802002-11-03 00:38:21 +0000538
wdenk78137c32003-09-15 18:00:00 +0000539#undef CONFIG_WATCHDOG /* disable the watchdog */
540
wdenkfe8c2802002-11-03 00:38:21 +0000541/*****************************************************************************
542 *
543 * You should not have to modify any of the following settings
544 *
545 *****************************************************************************/
546
547#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
548#define CONFIG_SBC8260 1 /* on an EST SBC8260 Board */
549#define CONFIG_SACSng 1 /* munged for the SACSng */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500550#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenkfe8c2802002-11-03 00:38:21 +0000551
wdenkfe8c2802002-11-03 00:38:21 +0000552/*
553 * Miscellaneous configurable options
554 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200555#define CONFIG_SYS_BOOTM_HEADER_QUIET 1 /* Suppress the image header dump */
wdenk42d1f032003-10-15 23:53:47 +0000556 /* in the bootm command. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200557#define CONFIG_SYS_BOOTM_PROGESS_QUIET 1 /* Suppress the progress displays, */
wdenk42d1f032003-10-15 23:53:47 +0000558 /* "## <message>" from the bootm cmd */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200559#define CONFIG_SYS_BOOTP_CHECK_HOSTNAME 1 /* If checkhostname environment is */
wdenk42d1f032003-10-15 23:53:47 +0000560 /* defined, then the hostname param */
561 /* validated against checkhostname. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200562#define CONFIG_SYS_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up */
563#define CONFIG_SYS_BOOTP_SHORT_RANDOM_DELAY 1 /* Use a short random delay value */
wdenk42d1f032003-10-15 23:53:47 +0000564 /* (limited to maximum of 1024 msec) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200565#define CONFIG_SYS_CHK_FOR_ABORT_AT_LEAST_ONCE 1
wdenk42d1f032003-10-15 23:53:47 +0000566 /* Check for abort key presses */
567 /* at least once in dependent of the */
568 /* CONFIG_BOOTDELAY value. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200569#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Don't print console @ startup */
570#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 /* Echo the inverted Ethernet link */
wdenk42d1f032003-10-15 23:53:47 +0000571 /* state to the fault LED. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200572#define CONFIG_SYS_FAULT_MII_ADDR 0x02 /* MII addr of the PHY to check for */
wdenk42d1f032003-10-15 23:53:47 +0000573 /* the Ethernet link state. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200574#define CONFIG_SYS_STATUS_FLASH_UNTIL_TFTP_OK 1 /* Keeping the status LED flashing */
wdenk42d1f032003-10-15 23:53:47 +0000575 /* until the TFTP is successful. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200576#define CONFIG_SYS_STATUS_OFF_AFTER_NETBOOT 1 /* After a successful netboot, */
wdenk42d1f032003-10-15 23:53:47 +0000577 /* turn off the STATUS LEDs. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200578#define CONFIG_SYS_TFTP_BLINK_STATUS_ON_DATA_IN 1 /* Blink status LED based on */
wdenk42d1f032003-10-15 23:53:47 +0000579 /* incoming data. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200580#define CONFIG_SYS_TFTP_BLOCKS_PER_HASH 100 /* For every XX blocks, output a '#' */
wdenk42d1f032003-10-15 23:53:47 +0000581 /* to signify that tftp is moving. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200582#define CONFIG_SYS_TFTP_HASHES_PER_FLASH 200 /* For every '#' hashes, */
wdenk42d1f032003-10-15 23:53:47 +0000583 /* flash the status LED. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200584#define CONFIG_SYS_TFTP_HASHES_PER_LINE 65 /* Only output XX '#'s per line */
wdenk42d1f032003-10-15 23:53:47 +0000585 /* during the tftp file transfer. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200586#define CONFIG_SYS_TFTP_PROGESS_QUIET 1 /* Suppress the progress displays */
wdenk42d1f032003-10-15 23:53:47 +0000587 /* '#'s from the tftp command. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200588#define CONFIG_SYS_TFTP_STATUS_QUIET 1 /* Suppress the status displays */
wdenk42d1f032003-10-15 23:53:47 +0000589 /* issued during the tftp command. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200590#define CONFIG_SYS_TFTP_TIMEOUT_COUNT 5 /* How many timeouts TFTP will allow */
wdenk78137c32003-09-15 18:00:00 +0000591 /* before it gives up. */
592
Jon Loeliger46da1e92007-07-04 22:33:30 -0500593#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200594# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkfe8c2802002-11-03 00:38:21 +0000595#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200596# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkfe8c2802002-11-03 00:38:21 +0000597#endif
598
599/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200600#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
wdenkfe8c2802002-11-03 00:38:21 +0000601
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200602#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
wdenkfe8c2802002-11-03 00:38:21 +0000603
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200604#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkfe8c2802002-11-03 00:38:21 +0000605
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200606#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
607#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkfe8c2802002-11-03 00:38:21 +0000608
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200609#define CONFIG_SYS_ALT_MEMTEST /* Select full-featured memory test */
610#define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */
wdenkfe8c2802002-11-03 00:38:21 +0000611 /* the exception vector table */
612 /* to the end of the DRAM */
613 /* less monitor and malloc area */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200614#define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
615#define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \
616 + CONFIG_SYS_MALLOC_LEN \
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200617 + CONFIG_ENV_SECT_SIZE \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200618 + CONFIG_SYS_STACK_USAGE )
wdenkfe8c2802002-11-03 00:38:21 +0000619
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200620#define CONFIG_SYS_MEMTEST_END ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
621 - CONFIG_SYS_MEM_END_USAGE )
wdenkfe8c2802002-11-03 00:38:21 +0000622
623/* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200624#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenkfe8c2802002-11-03 00:38:21 +0000625
626/*
627 * Low Level Configuration Settings
628 * (address mappings, register initial values, etc.)
629 * You should know what you are doing if you make changes here.
630 */
631
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200632#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
633#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
634#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE
635#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM0_SIZE
wdenkfe8c2802002-11-03 00:38:21 +0000636
637/*-----------------------------------------------------------------------
638 * Hard Reset Configuration Words
639 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200640#if defined(CONFIG_SYS_SBC_BOOT_LOW)
641# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
wdenkfe8c2802002-11-03 00:38:21 +0000642#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200643# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0)
644#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
wdenkfe8c2802002-11-03 00:38:21 +0000645
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200646/* get the HRCW ISB field from CONFIG_SYS_IMMR */
647#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
648 ((CONFIG_SYS_IMMR & 0x01000000) >> 7) | \
649 ((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
wdenkfe8c2802002-11-03 00:38:21 +0000650
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200651#define CONFIG_SYS_HRCW_MASTER ( HRCW_BPS10 | \
wdenkfe8c2802002-11-03 00:38:21 +0000652 HRCW_DPPC11 | \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200653 CONFIG_SYS_SBC_HRCW_IMMR | \
wdenkfe8c2802002-11-03 00:38:21 +0000654 HRCW_MMR00 | \
655 HRCW_LBPC11 | \
656 HRCW_APPC10 | \
657 HRCW_CS10PC00 | \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200658 (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) | \
659 CONFIG_SYS_SBC_HRCW_BOOT_FLAGS )
wdenkfe8c2802002-11-03 00:38:21 +0000660
661/* no slaves */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200662#define CONFIG_SYS_HRCW_SLAVE1 0
663#define CONFIG_SYS_HRCW_SLAVE2 0
664#define CONFIG_SYS_HRCW_SLAVE3 0
665#define CONFIG_SYS_HRCW_SLAVE4 0
666#define CONFIG_SYS_HRCW_SLAVE5 0
667#define CONFIG_SYS_HRCW_SLAVE6 0
668#define CONFIG_SYS_HRCW_SLAVE7 0
wdenkfe8c2802002-11-03 00:38:21 +0000669
670/*-----------------------------------------------------------------------
671 * Definitions for initial stack pointer and data area (in DPRAM)
672 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200673#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
674#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
675#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
676#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
677#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkfe8c2802002-11-03 00:38:21 +0000678
679/*-----------------------------------------------------------------------
680 * Start addresses for the final memory configuration
681 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200682 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
683 * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
wdenkfe8c2802002-11-03 00:38:21 +0000684 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200685#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE
wdenkfe8c2802002-11-03 00:38:21 +0000686
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200687#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
688# define CONFIG_SYS_RAMBOOT
wdenkfe8c2802002-11-03 00:38:21 +0000689#endif
690
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200691#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
692#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkfe8c2802002-11-03 00:38:21 +0000693
694/*
695 * For booting Linux, the board info and command line data
696 * have to be in the first 8 MB of memory, since this is
697 * the maximum mapped by the Linux kernel during initialization.
698 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200699#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkfe8c2802002-11-03 00:38:21 +0000700
701/*-----------------------------------------------------------------------
702 * FLASH and environment organization
703 */
704
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200705#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
706#undef CONFIG_SYS_FLASH_PROTECTION /* use hardware protection */
707#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
708#define CONFIG_SYS_MAX_FLASH_SECT (64+4) /* max number of sectors on one chip */
wdenkfe8c2802002-11-03 00:38:21 +0000709
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200710#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
711#define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
wdenkfe8c2802002-11-03 00:38:21 +0000712
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200713#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200714# define CONFIG_ENV_IS_IN_FLASH 1
wdenkfe8c2802002-11-03 00:38:21 +0000715
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200716# ifdef CONFIG_ENV_IN_OWN_SECT
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200717# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200718# define CONFIG_ENV_SECT_SIZE 0x10000
wdenkfe8c2802002-11-03 00:38:21 +0000719# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200720# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200721# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
722# define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
723# endif /* CONFIG_ENV_IN_OWN_SECT */
wdenkfe8c2802002-11-03 00:38:21 +0000724
725#else
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200726# define CONFIG_ENV_IS_IN_NVRAM 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200727# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200728# define CONFIG_ENV_SIZE 0x200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200729#endif /* CONFIG_SYS_RAMBOOT */
wdenkfe8c2802002-11-03 00:38:21 +0000730
731/*-----------------------------------------------------------------------
732 * Cache Configuration
733 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200734#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
wdenkfe8c2802002-11-03 00:38:21 +0000735
Jon Loeliger46da1e92007-07-04 22:33:30 -0500736#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200737# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenkfe8c2802002-11-03 00:38:21 +0000738#endif
739
740/*-----------------------------------------------------------------------
741 * HIDx - Hardware Implementation-dependent Registers 2-11
742 *-----------------------------------------------------------------------
743 * HID0 also contains cache control - initially enable both caches and
744 * invalidate contents, then the final state leaves only the instruction
745 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
746 * but Soft reset does not.
747 *
748 * HID1 has only read-only information - nothing to set.
749 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200750#define CONFIG_SYS_HID0_INIT (HID0_ICE |\
wdenkfe8c2802002-11-03 00:38:21 +0000751 HID0_DCE |\
752 HID0_ICFI |\
753 HID0_DCI |\
754 HID0_IFEM |\
755 HID0_ABE)
756
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200757#define CONFIG_SYS_HID0_FINAL (HID0_ICE |\
wdenkfe8c2802002-11-03 00:38:21 +0000758 HID0_IFEM |\
759 HID0_ABE |\
760 HID0_EMCP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200761#define CONFIG_SYS_HID2 0
wdenkfe8c2802002-11-03 00:38:21 +0000762
763/*-----------------------------------------------------------------------
764 * RMR - Reset Mode Register
765 *-----------------------------------------------------------------------
766 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200767#define CONFIG_SYS_RMR 0
wdenkfe8c2802002-11-03 00:38:21 +0000768
769/*-----------------------------------------------------------------------
770 * BCR - Bus Configuration 4-25
771 *-----------------------------------------------------------------------
772 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200773#define CONFIG_SYS_BCR (BCR_ETM)
wdenkfe8c2802002-11-03 00:38:21 +0000774
775/*-----------------------------------------------------------------------
776 * SIUMCR - SIU Module Configuration 4-31
777 *-----------------------------------------------------------------------
778 */
779
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200780#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 |\
wdenkfe8c2802002-11-03 00:38:21 +0000781 SIUMCR_L2CPC00 |\
782 SIUMCR_APPC10 |\
783 SIUMCR_MMR00)
784
785
786/*-----------------------------------------------------------------------
787 * SYPCR - System Protection Control 11-9
788 * SYPCR can only be written once after reset!
789 *-----------------------------------------------------------------------
790 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
791 */
wdenk78137c32003-09-15 18:00:00 +0000792#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200793#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
wdenk78137c32003-09-15 18:00:00 +0000794 SYPCR_BMT |\
795 SYPCR_PBME |\
796 SYPCR_LBME |\
797 SYPCR_SWRI |\
798 SYPCR_SWP |\
wdenk42d1f032003-10-15 23:53:47 +0000799 SYPCR_SWE)
wdenk78137c32003-09-15 18:00:00 +0000800#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200801#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
wdenkfe8c2802002-11-03 00:38:21 +0000802 SYPCR_BMT |\
803 SYPCR_PBME |\
804 SYPCR_LBME |\
805 SYPCR_SWRI |\
806 SYPCR_SWP)
wdenk78137c32003-09-15 18:00:00 +0000807#endif /* CONFIG_WATCHDOG */
wdenkfe8c2802002-11-03 00:38:21 +0000808
809/*-----------------------------------------------------------------------
810 * TMCNTSC - Time Counter Status and Control 4-40
811 *-----------------------------------------------------------------------
812 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
813 * and enable Time Counter
814 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200815#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\
wdenkfe8c2802002-11-03 00:38:21 +0000816 TMCNTSC_ALR |\
817 TMCNTSC_TCF |\
818 TMCNTSC_TCE)
819
820/*-----------------------------------------------------------------------
821 * PISCR - Periodic Interrupt Status and Control 4-42
822 *-----------------------------------------------------------------------
823 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
824 * Periodic timer
825 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200826#define CONFIG_SYS_PISCR (PISCR_PS |\
wdenkfe8c2802002-11-03 00:38:21 +0000827 PISCR_PTF |\
828 PISCR_PTE)
829
830/*-----------------------------------------------------------------------
831 * SCCR - System Clock Control 9-8
832 *-----------------------------------------------------------------------
833 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200834#define CONFIG_SYS_SCCR 0
wdenkfe8c2802002-11-03 00:38:21 +0000835
836/*-----------------------------------------------------------------------
837 * RCCR - RISC Controller Configuration 13-7
838 *-----------------------------------------------------------------------
839 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200840#define CONFIG_SYS_RCCR 0
wdenkfe8c2802002-11-03 00:38:21 +0000841
842/*
843 * Initialize Memory Controller:
844 *
845 * Bank Bus Machine PortSz Device
846 * ---- --- ------- ------ ------
847 * 0 60x GPCM 16 bit FLASH (primary flash - 2MB)
848 * 1 60x GPCM -- bit (Unused)
849 * 2 60x SDRAM 64 bit SDRAM (DIMM)
850 * 3 60x SDRAM 64 bit SDRAM (DIMM)
851 * 4 60x GPCM -- bit (Unused)
852 * 5 60x GPCM -- bit (Unused)
853 * 6 60x GPCM 16 bit FLASH (secondary flash - 2MB)
854 */
855
856/*-----------------------------------------------------------------------
857 * BR0,BR1 - Base Register
858 * Ref: Section 10.3.1 on page 10-14
859 * OR0,OR1 - Option Register
860 * Ref: Section 10.3.2 on page 10-18
861 *-----------------------------------------------------------------------
862 */
863
864/* Bank 0 - Primary FLASH
865 */
866
867/* BR0 is configured as follows:
868 *
869 * - Base address of 0x40000000
870 * - 16 bit port size
871 * - Data errors checking is disabled
872 * - Read and write access
873 * - GPCM 60x bus
874 * - Access are handled by the memory controller according to MSEL
875 * - Not used for atomic operations
876 * - No data pipelining is done
877 * - Valid
878 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200879#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
wdenkfe8c2802002-11-03 00:38:21 +0000880 BRx_PS_16 |\
881 BRx_MS_GPCM_P |\
882 BRx_V)
883
884/* OR0 is configured as follows:
885 *
886 * - 4 MB
887 * - *BCTL0 is asserted upon access to the current memory bank
888 * - *CW / *WE are negated a quarter of a clock earlier
889 * - *CS is output at the same time as the address lines
890 * - Uses a clock cycle length of 5
891 * - *PSDVAL is generated internally by the memory controller
892 * unless *GTA is asserted earlier externally.
893 * - Relaxed timing is generated by the GPCM for accesses
894 * initiated to this memory region.
895 * - One idle clock is inserted between a read access from the
896 * current bank and the next access.
897 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200898#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\
wdenkfe8c2802002-11-03 00:38:21 +0000899 ORxG_CSNT |\
900 ORxG_ACS_DIV1 |\
901 ORxG_SCY_5_CLK |\
902 ORxG_TRLX |\
903 ORxG_EHTR)
904
905/*-----------------------------------------------------------------------
906 * BR2,BR3 - Base Register
907 * Ref: Section 10.3.1 on page 10-14
908 * OR2,OR3 - Option Register
909 * Ref: Section 10.3.2 on page 10-16
910 *-----------------------------------------------------------------------
911 */
912
913/* Bank 2,3 - SDRAM DIMM
914 */
915
916/* The BR2 is configured as follows:
917 *
918 * - Base address of 0x00000000
919 * - 64 bit port size (60x bus only)
920 * - Data errors checking is disabled
921 * - Read and write access
922 * - SDRAM 60x bus
923 * - Access are handled by the memory controller according to MSEL
924 * - Not used for atomic operations
925 * - No data pipelining is done
926 * - Valid
927 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200928#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
wdenkfe8c2802002-11-03 00:38:21 +0000929 BRx_PS_64 |\
930 BRx_MS_SDRAM_P |\
931 BRx_V)
932
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200933#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
wdenkfe8c2802002-11-03 00:38:21 +0000934 BRx_PS_64 |\
935 BRx_MS_SDRAM_P |\
936 BRx_V)
937
938/* With a 64 MB DIMM, the OR2 is configured as follows:
939 *
940 * - 64 MB
941 * - 4 internal banks per device
942 * - Row start address bit is A8 with PSDMR[PBI] = 0
943 * - 12 row address lines
944 * - Back-to-back page mode
945 * - Internal bank interleaving within save device enabled
946 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200947#if (CONFIG_SYS_SDRAM0_SIZE == 64)
948#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
wdenkfe8c2802002-11-03 00:38:21 +0000949 ORxS_BPD_4 |\
950 ORxS_ROWST_PBI0_A8 |\
951 ORxS_NUMR_12)
952#else
953#error "INVALID SDRAM CONFIGURATION"
954#endif
955
956/*-----------------------------------------------------------------------
957 * PSDMR - 60x Bus SDRAM Mode Register
958 * Ref: Section 10.3.3 on page 10-21
959 *-----------------------------------------------------------------------
960 */
961
962/* Address that the DIMM SPD memory lives at.
963 */
964#define SDRAM_SPD_ADDR 0x50
965
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200966#if (CONFIG_SYS_SDRAM0_SIZE == 64)
wdenkfe8c2802002-11-03 00:38:21 +0000967/* With a 64 MB DIMM, the PSDMR is configured as follows:
968 *
969 * - Bank Based Interleaving,
970 * - Refresh Enable,
971 * - Address Multiplexing where A5 is output on A14 pin
972 * (A6 on A15, and so on),
973 * - use address pins A14-A16 as bank select,
974 * - A9 is output on SDA10 during an ACTIVATE command,
975 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
976 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
977 * is 3 clocks,
978 * - earliest timing for READ/WRITE command after ACTIVATE command is
979 * 2 clocks,
980 * - earliest timing for PRECHARGE after last data was read is 1 clock,
981 * - earliest timing for PRECHARGE after last data was written is 1 clock,
982 * - CAS Latency is 2.
983 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200984#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
wdenkfe8c2802002-11-03 00:38:21 +0000985 PSDMR_SDAM_A14_IS_A5 |\
986 PSDMR_BSMA_A14_A16 |\
987 PSDMR_SDA10_PBI0_A9 |\
988 PSDMR_RFRC_7_CLK |\
989 PSDMR_PRETOACT_3W |\
990 PSDMR_ACTTORW_2W |\
991 PSDMR_LDOTOPRE_1C |\
992 PSDMR_WRC_1C |\
993 PSDMR_CL_2)
994#else
995#error "INVALID SDRAM CONFIGURATION"
996#endif
997
998/*
999 * Shoot for approximately 1MHz on the prescaler.
1000 */
1001#if (CONFIG_8260_CLKIN >= (60 * 1000 * 1000))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001002#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV64
wdenkfe8c2802002-11-03 00:38:21 +00001003#elif (CONFIG_8260_CLKIN >= (30 * 1000 * 1000))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001004#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32
wdenkfe8c2802002-11-03 00:38:21 +00001005#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001006#warning "Unconfigured bus clock freq: check CONFIG_SYS_MPTPR and CONFIG_SYS_PSRT are OK"
1007#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32
wdenkfe8c2802002-11-03 00:38:21 +00001008#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001009#define CONFIG_SYS_PSRT 14
wdenkfe8c2802002-11-03 00:38:21 +00001010
1011
1012/*-----------------------------------------------------------------------
1013 * BR6 - Base Register
1014 * Ref: Section 10.3.1 on page 10-14
1015 * OR6 - Option Register
1016 * Ref: Section 10.3.2 on page 10-18
1017 *-----------------------------------------------------------------------
1018 */
1019
1020/* Bank 6 - Secondary FLASH
1021 *
1022 * The secondary FLASH is connected to *CS6
1023 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001024#if (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE))
wdenkfe8c2802002-11-03 00:38:21 +00001025
1026/* BR6 is configured as follows:
1027 *
1028 * - Base address of 0x60000000
1029 * - 16 bit port size
1030 * - Data errors checking is disabled
1031 * - Read and write access
1032 * - GPCM 60x bus
1033 * - Access are handled by the memory controller according to MSEL
1034 * - Not used for atomic operations
1035 * - No data pipelining is done
1036 * - Valid
1037 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001038# define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_FLASH1_BASE & BRx_BA_MSK) |\
wdenkfe8c2802002-11-03 00:38:21 +00001039 BRx_PS_16 |\
1040 BRx_MS_GPCM_P |\
1041 BRx_V)
1042
1043/* OR6 is configured as follows:
1044 *
1045 * - 2 MB
1046 * - *BCTL0 is asserted upon access to the current memory bank
1047 * - *CW / *WE are negated a quarter of a clock earlier
1048 * - *CS is output at the same time as the address lines
1049 * - Uses a clock cycle length of 5
1050 * - *PSDVAL is generated internally by the memory controller
1051 * unless *GTA is asserted earlier externally.
1052 * - Relaxed timing is generated by the GPCM for accesses
1053 * initiated to this memory region.
1054 * - One idle clock is inserted between a read access from the
1055 * current bank and the next access.
1056 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001057# define CONFIG_SYS_OR6_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH1_SIZE) |\
wdenkfe8c2802002-11-03 00:38:21 +00001058 ORxG_CSNT |\
1059 ORxG_ACS_DIV1 |\
1060 ORxG_SCY_5_CLK |\
1061 ORxG_TRLX |\
1062 ORxG_EHTR)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001063#endif /* (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE)) */
wdenkfe8c2802002-11-03 00:38:21 +00001064
1065/*
1066 * Internal Definitions
1067 *
1068 * Boot Flags
1069 */
1070#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
1071#define BOOTFLAG_WARM 0x02 /* Software reboot */
1072
1073#endif /* __CONFIG_H */