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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / f395cf9cacb1c54f95bce09473e37b8ac2b5517d / . / board / Synology / ds109 / ds109.c
blob: 9e7f6ac6c7923471821f98cc20d8525b79bc8141 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Walter Schweizera0a868b2016-10-06 23:29:56 +0200[diff] [blame]2/*
3 * Copyright (C) 2009-2012
4 * Wojciech Dubowik <wojciech.dubowik@neratec.com>
5 * Luka Perkov <luka@openwrt.org>
Walter Schweizera0a868b2016-10-06 23:29:56 +0200[diff] [blame]6 */
7
8#include <common.h>
Simon Glass691d7192020-05-10 11:40:02 -0600[diff] [blame]9#include <init.h>
Walter Schweizera0a868b2016-10-06 23:29:56 +0200[diff] [blame]10#include <miiphy.h>
Simon Glass5e6267a2019-12-28 10:44:48 -0700[diff] [blame]11#include <net.h>
Simon Glass401d1c42020-10-30 21:38:53 -0600[diff] [blame]12#include <asm/global_data.h>
Pali Rohárf395cf92022-08-17 21:37:49 +0200[diff] [blame^]13#include <asm/io.h>
Simon Glass5d982852017-05-17 08:23:00 -0600[diff] [blame]14#include <asm/setup.h>
Walter Schweizera0a868b2016-10-06 23:29:56 +0200[diff] [blame]15#include <asm/arch/cpu.h>
16#include <asm/arch/soc.h>
17#include <asm/arch/mpp.h>
Simon Glassc05ed002020-05-10 11:40:11 -0600[diff] [blame]18#include <linux/delay.h>
Walter Schweizera0a868b2016-10-06 23:29:56 +0200[diff] [blame]19#include "ds109.h"
20
21DECLARE_GLOBAL_DATA_PTR;
22
23int board_early_init_f(void)
24{
25 /*
26 * default gpio configuration
27 * There are maximum 64 gpios controlled through 2 sets of registers
28 * the below configuration configures mainly initial LED status
29 */
30 mvebu_config_gpio(DS109_OE_VAL_LOW,
31 DS109_OE_VAL_HIGH,
32 DS109_OE_LOW, DS109_OE_HIGH);
33
34 /* Multi-Purpose Pins Functionality configuration */
35 static const u32 kwmpp_config[] = {
36 MPP0_SPI_SCn, /* SPI Flash */
37 MPP1_SPI_MOSI,
38 MPP2_SPI_SCK,
39 MPP3_SPI_MISO,
40 MPP4_GPIO,
41 MPP5_GPO,
42 MPP6_SYSRST_OUTn, /* Reset signal */
43 MPP7_GPO,
44 MPP8_TW_SDA, /* I2C */
45 MPP9_TW_SCK, /* I2C */
46 MPP10_UART0_TXD,
47 MPP11_UART0_RXD,
48 MPP12_GPO,
49 MPP13_UART1_TXD,
50 MPP14_UART1_RXD,
51 MPP15_GPIO,
52 MPP16_GPIO,
53 MPP17_GPIO,
54 MPP18_GPO,
55 MPP19_GPO,
56 MPP20_SATA1_ACTn,
57 MPP21_SATA0_ACTn,
58 MPP22_GPIO, /* HDD2 FAIL LED */
59 MPP23_GPIO, /* HDD1 FAIL LED */
60 MPP24_GPIO,
61 MPP25_GPIO,
62 MPP26_GPIO,
63 MPP27_GPIO,
64 MPP28_GPIO,
65 MPP29_GPIO,
66 MPP30_GPIO,
67 MPP31_GPIO, /* HDD2 */
68 MPP32_GPIO, /* FAN A */
69 MPP33_GPIO, /* FAN B */
70 MPP34_GPIO, /* FAN C */
71 MPP35_GPIO, /* FAN SENSE */
72 MPP36_GPIO,
73 MPP37_GPIO,
74 MPP38_GPIO,
75 MPP39_GPIO,
76 MPP40_GPIO,
77 MPP41_GPIO,
78 MPP42_GPIO,
79 MPP43_GPIO,
80 MPP44_GPIO,
81 MPP45_GPIO,
82 MPP46_GPIO,
83 MPP47_GPIO,
84 MPP48_GPIO,
85 MPP49_GPIO,
86 0
87 };
88 kirkwood_mpp_conf(kwmpp_config, NULL);
89 return 0;
90}
91
92int board_init(void)
93{
94 /* address of boot parameters */
95 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
96
97 return 0;
98}
99
100/* Synology reset uses UART */
101#include <ns16550.h>
102#define SOFTWARE_SHUTDOWN 0x31
103#define SOFTWARE_REBOOT 0x43
104#define CONFIG_SYS_NS16550_COM2 KW_UART1_BASE
105void reset_misc(void)
106{
107 int b_d;
108 printf("Synology reset...");
109 udelay(50000);
110
Simon Glassd30c7202020-12-22 19:30:18 -0700[diff] [blame]111 b_d = ns16550_calc_divisor((struct ns16550 *)CONFIG_SYS_NS16550_COM2,
112 CONFIG_SYS_NS16550_CLK, 9600);
Simon Glass2d6bf752020-12-22 19:30:19 -0700[diff] [blame]113 ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM2, b_d);
114 ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM2,
115 SOFTWARE_REBOOT);
Walter Schweizera0a868b2016-10-06 23:29:56 +0200[diff] [blame]116}
117
Walter Schweizera0a868b2016-10-06 23:29:56 +0200[diff] [blame]118#ifdef CONFIG_RESET_PHY_R
119/* Configure and enable MV88E1116 PHY */
120void reset_phy(void)
121{
122 u16 reg;
123 u16 devadr;
124 char *name = "egiga0";
125
126 if (miiphy_set_current_dev(name))
127 return;
128
129 /* command to read PHY dev address */
130 if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
131 printf("Error: 88E1116 could not read PHY dev address\n");
132 return;
133 }
134
135 /*
136 * Enable RGMII delay on Tx and Rx for CPU port
137 * Ref: sec 4.7.2 of chip datasheet
138 */
139 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
140 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
141 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
142 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
143 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
144
145 /* reset the phy */
146 miiphy_reset(name, devadr);
147
148 printf("88E1116 Initialized on %s\n", name);
149}
150#endif /* CONFIG_RESET_PHY_R */