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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenk3d3befa2004-03-14 15:06:13 +00002/*
3 * (C) Copyright 2003, 2004
4 * ARM Ltd.
5 * Philippe Robin, <philippe.robin@arm.com>
wdenk3d3befa2004-03-14 15:06:13 +00006 */
7
8/*
wdenk42dfe7a2004-03-14 22:25:36 +00009 * ARM PrimeCell UART's (PL010 & PL011)
wdenk3d3befa2004-03-14 15:06:13 +000010 * ------------------------------------
wdenk42dfe7a2004-03-14 22:25:36 +000011 *
wdenk3d3befa2004-03-14 15:06:13 +000012 * Definitions common to both PL010 & PL011
wdenk42dfe7a2004-03-14 22:25:36 +000013 *
wdenk3d3befa2004-03-14 15:06:13 +000014 */
Rabin Vincent72d5e442010-05-05 09:23:07 +053015
16#ifndef __ASSEMBLY__
17/*
18 * We can use a combined structure for PL010 and PL011, because they overlap
19 * only in common registers.
20 */
21struct pl01x_regs {
22 u32 dr; /* 0x00 Data register */
23 u32 ecr; /* 0x04 Error clear register (Write) */
24 u32 pl010_lcrh; /* 0x08 Line control register, high byte */
25 u32 pl010_lcrm; /* 0x0C Line control register, middle byte */
26 u32 pl010_lcrl; /* 0x10 Line control register, low byte */
27 u32 pl010_cr; /* 0x14 Control register */
28 u32 fr; /* 0x18 Flag register (Read only) */
John Rigby910f1ae2011-04-19 10:42:39 +000029#ifdef CONFIG_PL011_SERIAL_RLCR
30 u32 pl011_rlcr; /* 0x1c Receive line control register */
31#else
Rabin Vincent72d5e442010-05-05 09:23:07 +053032 u32 reserved;
John Rigby910f1ae2011-04-19 10:42:39 +000033#endif
Rabin Vincent72d5e442010-05-05 09:23:07 +053034 u32 ilpr; /* 0x20 IrDA low-power counter register */
35 u32 pl011_ibrd; /* 0x24 Integer baud rate register */
36 u32 pl011_fbrd; /* 0x28 Fractional baud rate register */
37 u32 pl011_lcrh; /* 0x2C Line control register */
38 u32 pl011_cr; /* 0x30 Control register */
39};
Alexander Graf60019852018-01-25 12:05:55 +010040
Tom Rini0478dac2022-12-04 10:14:13 -050041#if CONFIG_IS_ENABLED(DM_SERIAL)
Alexander Graf60019852018-01-25 12:05:55 +010042
Simon Glassd1998a92020-12-03 16:55:21 -070043int pl01x_serial_of_to_plat(struct udevice *dev);
Alexander Graf60019852018-01-25 12:05:55 +010044int pl01x_serial_probe(struct udevice *dev);
Alexander Grafc9bf43d2018-03-07 22:08:25 +010045
46/* Needed for external pl01x_serial_ops drivers */
47int pl01x_serial_putc(struct udevice *dev, const char ch);
48int pl01x_serial_pending(struct udevice *dev, bool input);
49int pl01x_serial_getc(struct udevice *dev);
50int pl01x_serial_setbrg(struct udevice *dev, int baudrate);
Alexander Graf60019852018-01-25 12:05:55 +010051
52struct pl01x_priv {
53 struct pl01x_regs *regs;
54 enum pl01x_type type;
55};
56
57#endif /* CONFIG_DM_SERIAL */
58#endif /* !__ASSEMBLY__ */
wdenk3d3befa2004-03-14 15:06:13 +000059
60#define UART_PL01x_RSR_OE 0x08
61#define UART_PL01x_RSR_BE 0x04
62#define UART_PL01x_RSR_PE 0x02
63#define UART_PL01x_RSR_FE 0x01
64
65#define UART_PL01x_FR_TXFE 0x80
66#define UART_PL01x_FR_RXFF 0x40
67#define UART_PL01x_FR_TXFF 0x20
68#define UART_PL01x_FR_RXFE 0x10
69#define UART_PL01x_FR_BUSY 0x08
70#define UART_PL01x_FR_TMSK (UART_PL01x_FR_TXFF + UART_PL01x_FR_BUSY)
71
wdenk42dfe7a2004-03-14 22:25:36 +000072/*
wdenk3d3befa2004-03-14 15:06:13 +000073 * PL010 definitions
wdenk42dfe7a2004-03-14 22:25:36 +000074 *
wdenk3d3befa2004-03-14 15:06:13 +000075 */
wdenk3d3befa2004-03-14 15:06:13 +000076#define UART_PL010_CR_LPE (1 << 7)
77#define UART_PL010_CR_RTIE (1 << 6)
78#define UART_PL010_CR_TIE (1 << 5)
79#define UART_PL010_CR_RIE (1 << 4)
80#define UART_PL010_CR_MSIE (1 << 3)
81#define UART_PL010_CR_IIRLP (1 << 2)
82#define UART_PL010_CR_SIREN (1 << 1)
83#define UART_PL010_CR_UARTEN (1 << 0)
wdenk42dfe7a2004-03-14 22:25:36 +000084
wdenk3d3befa2004-03-14 15:06:13 +000085#define UART_PL010_LCRH_WLEN_8 (3 << 5)
86#define UART_PL010_LCRH_WLEN_7 (2 << 5)
87#define UART_PL010_LCRH_WLEN_6 (1 << 5)
88#define UART_PL010_LCRH_WLEN_5 (0 << 5)
89#define UART_PL010_LCRH_FEN (1 << 4)
90#define UART_PL010_LCRH_STP2 (1 << 3)
91#define UART_PL010_LCRH_EPS (1 << 2)
92#define UART_PL010_LCRH_PEN (1 << 1)
93#define UART_PL010_LCRH_BRK (1 << 0)
94
95
96#define UART_PL010_BAUD_460800 1
97#define UART_PL010_BAUD_230400 3
98#define UART_PL010_BAUD_115200 7
99#define UART_PL010_BAUD_57600 15
100#define UART_PL010_BAUD_38400 23
101#define UART_PL010_BAUD_19200 47
102#define UART_PL010_BAUD_14400 63
103#define UART_PL010_BAUD_9600 95
104#define UART_PL010_BAUD_4800 191
105#define UART_PL010_BAUD_2400 383
106#define UART_PL010_BAUD_1200 767
wdenk42dfe7a2004-03-14 22:25:36 +0000107/*
wdenk3d3befa2004-03-14 15:06:13 +0000108 * PL011 definitions
wdenk42dfe7a2004-03-14 22:25:36 +0000109 *
wdenk3d3befa2004-03-14 15:06:13 +0000110 */
wdenk3d3befa2004-03-14 15:06:13 +0000111#define UART_PL011_LCRH_SPS (1 << 7)
112#define UART_PL011_LCRH_WLEN_8 (3 << 5)
113#define UART_PL011_LCRH_WLEN_7 (2 << 5)
114#define UART_PL011_LCRH_WLEN_6 (1 << 5)
115#define UART_PL011_LCRH_WLEN_5 (0 << 5)
116#define UART_PL011_LCRH_FEN (1 << 4)
117#define UART_PL011_LCRH_STP2 (1 << 3)
118#define UART_PL011_LCRH_EPS (1 << 2)
119#define UART_PL011_LCRH_PEN (1 << 1)
120#define UART_PL011_LCRH_BRK (1 << 0)
121
122#define UART_PL011_CR_CTSEN (1 << 15)
123#define UART_PL011_CR_RTSEN (1 << 14)
124#define UART_PL011_CR_OUT2 (1 << 13)
125#define UART_PL011_CR_OUT1 (1 << 12)
126#define UART_PL011_CR_RTS (1 << 11)
127#define UART_PL011_CR_DTR (1 << 10)
128#define UART_PL011_CR_RXE (1 << 9)
129#define UART_PL011_CR_TXE (1 << 8)
130#define UART_PL011_CR_LPE (1 << 7)
131#define UART_PL011_CR_IIRLP (1 << 2)
132#define UART_PL011_CR_SIREN (1 << 1)
133#define UART_PL011_CR_UARTEN (1 << 0)
134
135#define UART_PL011_IMSC_OEIM (1 << 10)
136#define UART_PL011_IMSC_BEIM (1 << 9)
137#define UART_PL011_IMSC_PEIM (1 << 8)
138#define UART_PL011_IMSC_FEIM (1 << 7)
139#define UART_PL011_IMSC_RTIM (1 << 6)
140#define UART_PL011_IMSC_TXIM (1 << 5)
141#define UART_PL011_IMSC_RXIM (1 << 4)
142#define UART_PL011_IMSC_DSRMIM (1 << 3)
143#define UART_PL011_IMSC_DCDMIM (1 << 2)
144#define UART_PL011_IMSC_CTSMIM (1 << 1)
145#define UART_PL011_IMSC_RIMIM (1 << 0)