| Andrew Bradford | f3b84a3 | 2015-08-07 08:36:35 -0400 | [diff] [blame^] | 1 | Intel Bay Trail FSP UPD Binding |
| 2 | =============================== |
| 3 | |
| 4 | The device tree node which describes the overriding of the Intel Bay Trail FSP |
| 5 | UPD data for configuring the SoC. |
| 6 | |
| 7 | All properties can be found within the `upd-region` struct in |
| 8 | arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h, under the same names, and in |
| 9 | Intel's FSP Binary Configuration Tool for Bay Trail. This list of properties is |
| 10 | matched up to Intel's E3800 FSPv4 release. |
| 11 | |
| 12 | # Boolean properties: |
| 13 | |
| 14 | - fsp,enable-sdio |
| 15 | - fsp,enable-sdcard |
| 16 | - fsp,enable-hsuart0 |
| 17 | - fsp,enable-hsuart1 |
| 18 | - fsp,enable-spi |
| 19 | - fsp,enable-sata |
| 20 | - fsp,enable-azalia |
| 21 | - fsp,enable-xhci |
| 22 | - fsp,enable-lpe |
| 23 | - fsp,lpss-sio-enable-pci-mode |
| 24 | - fsp,enable-dma0 |
| 25 | - fsp,enable-dma1 |
| 26 | - fsp,enable-i2-c0 |
| 27 | - fsp,enable-i2-c1 |
| 28 | - fsp,enable-i2-c2 |
| 29 | - fsp,enable-i2-c3 |
| 30 | - fsp,enable-i2-c4 |
| 31 | - fsp,enable-i2-c5 |
| 32 | - fsp,enable-i2-c6 |
| 33 | - fsp,enable-pwm0 |
| 34 | - fsp,enable-pwm1 |
| 35 | - fsp,enable-hsi |
| 36 | - fsp,mrc-debug-msg |
| 37 | - fsp,isp-enable |
| 38 | - fsp,scc-enable-pci-mode |
| 39 | - fsp,igd-render-standby |
| 40 | - fsp,txe-uma-enable |
| 41 | - fsp,emmc45-ddr50-enabled |
| 42 | - fsp,emmc45-hs200-enabled |
| 43 | - fsp,enable-igd |
| 44 | - fsp,enable-memory-down |
| 45 | |
| 46 | If you set "fsp,enable-memory-down" you are strongly encouraged to provide an |
| 47 | "fsp,memory-down-params{};" to specify how your memory is configured. If you do |
| 48 | not set "fsp,enable-memory-down", then the DIMM SPD information will be |
| 49 | discovered by the FSP and used to setup main memory. |
| 50 | |
| 51 | |
| 52 | # Integer properties: |
| 53 | |
| 54 | - fsp,mrc-init-tseg-size |
| 55 | - fsp,mrc-init-mmio-size |
| 56 | - fsp,mrc-init-spd-addr1 |
| 57 | - fsp,mrc-init-spd-addr2 |
| 58 | - fsp,emmc-boot-mode |
| 59 | - fsp,sata-mode |
| 60 | - fsp,igd-dvmt50-pre-alloc |
| 61 | - fsp,aperture-size |
| 62 | - fsp,gtt-size |
| 63 | - fsp,serial-debug-port-address |
| 64 | - fsp,serial-debug-port-type |
| 65 | - fsp,os-selection |
| 66 | - fsp,emmc45-retune-timer-value |
| 67 | |
| 68 | - fsp,memory-down-params { |
| 69 | |
| 70 | # Boolean properties: |
| 71 | |
| 72 | - fsp,dimm-0-enable |
| 73 | - fsp,dimm-1-enable |
| 74 | |
| 75 | # Integer properties: |
| 76 | |
| 77 | - fsp,dram-speed |
| 78 | - fsp,dram-type |
| 79 | - fsp,dimm-width |
| 80 | - fsp,dimm-density |
| 81 | - fsp,dimm-bus-width |
| 82 | - fsp,dimm-sides |
| 83 | - fsp,dimm-tcl |
| 84 | - fsp,dimm-trpt-rcd |
| 85 | - fsp,dimm-twr |
| 86 | - fsp,dimm-twtr |
| 87 | - fsp,dimm-trrd |
| 88 | - fsp,dimm-trtp |
| 89 | - fsp,dimm-tfaw |
| 90 | }; |
| 91 | |
| 92 | |
| 93 | Example (from MinnowMax Dual Core): |
| 94 | ----------------------------------- |
| 95 | |
| 96 | / { |
| 97 | ... |
| 98 | |
| 99 | fsp { |
| 100 | compatible = "intel,baytrail-fsp"; |
| 101 | fsp,mrc-init-tseg-size = <0>; |
| 102 | fsp,mrc-init-mmio-size = <0x800>; |
| 103 | fsp,mrc-init-spd-addr1 = <0xa0>; |
| 104 | fsp,mrc-init-spd-addr2 = <0xa2>; |
| 105 | fsp,emmc-boot-mode = <2>; |
| 106 | fsp,enable-sdio; |
| 107 | fsp,enable-sdcard; |
| 108 | fsp,enable-hsuart1; |
| 109 | fsp,enable-spi; |
| 110 | fsp,enable-sata; |
| 111 | fsp,sata-mode = <1>; |
| 112 | fsp,enable-xhci; |
| 113 | fsp,enable-lpe; |
| 114 | fsp,lpss-sio-enable-pci-mode; |
| 115 | fsp,enable-dma0; |
| 116 | fsp,enable-dma1; |
| 117 | fsp,enable-i2c0; |
| 118 | fsp,enable-i2c1; |
| 119 | fsp,enable-i2c2; |
| 120 | fsp,enable-i2c3; |
| 121 | fsp,enable-i2c4; |
| 122 | fsp,enable-i2c5; |
| 123 | fsp,enable-i2c6; |
| 124 | fsp,enable-pwm0; |
| 125 | fsp,enable-pwm1; |
| 126 | fsp,igd-dvmt50-pre-alloc = <2>; |
| 127 | fsp,aperture-size = <2>; |
| 128 | fsp,gtt-size = <2>; |
| 129 | fsp,serial-debug-port-address = <0x3f8>; |
| 130 | fsp,serial-debug-port-type = <1>; |
| 131 | fsp,mrc-debug-msg; |
| 132 | fsp,scc-enable-pci-mode; |
| 133 | fsp,os-selection = <4>; |
| 134 | fsp,emmc45-ddr50-enabled; |
| 135 | fsp,emmc45-retune-timer-value = <8>; |
| 136 | fsp,enable-igd; |
| 137 | fsp,enable-memory-down; |
| 138 | fsp,memory-down-params { |
| 139 | compatible = "intel,baytrail-fsp-mdp"; |
| 140 | fsp,dram-speed = <1>; |
| 141 | fsp,dram-type = <1>; |
| 142 | fsp,dimm-0-enable; |
| 143 | fsp,dimm-width = <1>; |
| 144 | fsp,dimm-density = <2>; |
| 145 | fsp,dimm-bus-width = <3>; |
| 146 | fsp,dimm-sides = <0>; |
| 147 | fsp,dimm-tcl = <0xb>; |
| 148 | fsp,dimm-trpt-rcd = <0xb>; |
| 149 | fsp,dimm-twr = <0xc>; |
| 150 | fsp,dimm-twtr = <6>; |
| 151 | fsp,dimm-trrd = <6>; |
| 152 | fsp,dimm-trtp = <6>; |
| 153 | fsp,dimm-tfaw = <0x14>; |
| 154 | }; |
| 155 | }; |
| 156 | |
| 157 | ... |
| 158 | }; |