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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk1cb8e982003-03-06 21:55:29 +00002/*
3 * (C) Copyright 2002
4 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
wdenk1cb8e982003-03-06 21:55:29 +00005 */
6
wdenk1cb8e982003-03-06 21:55:29 +00007#include <common.h>
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +01008#include <errno.h>
9#include <dm.h>
Rajeshwari Shindea9d2ae72012-12-26 20:03:12 +000010#include <fdtdec.h>
Piotr Wilczekc86d9ed2012-11-20 02:19:05 +000011#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
Rajeshwari Shindeab7e52b2012-07-23 21:23:53 +000012#include <asm/arch/clk.h>
13#include <asm/arch/cpu.h>
Rajeshwari Shindea9d2ae72012-12-26 20:03:12 +000014#include <asm/arch/pinmux.h>
Rajeshwari Shindeab7e52b2012-07-23 21:23:53 +000015#else
kevin.morfitt@fearnside-systems.co.ukac678042009-11-17 18:30:34 +090016#include <asm/arch/s3c24x0_cpu.h>
Rajeshwari Shindeab7e52b2012-07-23 21:23:53 +000017#endif
kevin.morfitt@fearnside-systems.co.ukeb0ae7f2009-10-10 13:33:11 +090018#include <asm/io.h>
wdenk1cb8e982003-03-06 21:55:29 +000019#include <i2c.h>
Rajeshwari Shindeab7e52b2012-07-23 21:23:53 +000020#include "s3c24x0_i2c.h"
wdenk1cb8e982003-03-06 21:55:29 +000021
Jaehoon Chunga2987122017-01-09 14:47:51 +090022#ifndef CONFIG_SYS_I2C_S3C24X0_SLAVE
23#define SYS_I2C_S3C24X0_SLAVE_ADDR 0
24#else
25#define SYS_I2C_S3C24X0_SLAVE_ADDR CONFIG_SYS_I2C_S3C24X0_SLAVE
26#endif
27
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +010028DECLARE_GLOBAL_DATA_PTR;
29
Naveen Krishna Che4e24022013-10-15 16:01:43 +053030/*
31 * Wait til the byte transfer is completed.
32 *
33 * @param i2c- pointer to the appropriate i2c register bank.
34 * @return I2C_OK, if transmission was ACKED
35 * I2C_NACK, if transmission was NACKED
36 * I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS
37 */
38
Rajeshwari Shindeab7e52b2012-07-23 21:23:53 +000039static int WaitForXfer(struct s3c24x0_i2c *i2c)
wdenk1cb8e982003-03-06 21:55:29 +000040{
Naveen Krishna Che4e24022013-10-15 16:01:43 +053041 ulong start_time = get_timer(0);
wdenk1cb8e982003-03-06 21:55:29 +000042
Naveen Krishna Che4e24022013-10-15 16:01:43 +053043 do {
44 if (readl(&i2c->iiccon) & I2CCON_IRPND)
45 return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
46 I2C_NACK : I2C_OK;
47 } while (get_timer(start_time) < I2C_TIMEOUT_MS);
wdenk1cb8e982003-03-06 21:55:29 +000048
Naveen Krishna Che4e24022013-10-15 16:01:43 +053049 return I2C_NOK_TOUT;
wdenk1cb8e982003-03-06 21:55:29 +000050}
51
Simon Glass26ea7682015-07-02 18:15:46 -060052static void read_write_byte(struct s3c24x0_i2c *i2c)
wdenk1cb8e982003-03-06 21:55:29 +000053{
Simon Glass26ea7682015-07-02 18:15:46 -060054 clrbits_le32(&i2c->iiccon, I2CCON_IRPND);
wdenk1cb8e982003-03-06 21:55:29 +000055}
56
Rajeshwari Shindeab7e52b2012-07-23 21:23:53 +000057static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
58{
59 ulong freq, pres = 16, div;
Piotr Wilczekc86d9ed2012-11-20 02:19:05 +000060#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
Rajeshwari Shindeab7e52b2012-07-23 21:23:53 +000061 freq = get_i2c_clk();
62#else
63 freq = get_PCLK();
64#endif
65 /* calculate prescaler and divisor values */
66 if ((freq / pres / (16 + 1)) > speed)
67 /* set prescaler to 512 */
68 pres = 512;
69
70 div = 0;
71 while ((freq / pres / (div + 1)) > speed)
72 div++;
73
74 /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
75 writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
76
77 /* init to SLAVE REVEIVE and set slaveaddr */
78 writel(0, &i2c->iicstat);
79 writel(slaveadd, &i2c->iicadd);
80 /* program Master Transmit (and implicit STOP) */
81 writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
82}
83
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +010084static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
Piotr Wilczek2d8f1e22013-11-20 10:43:49 +010085{
Simon Glass9a1bff62016-11-23 06:34:42 -070086 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
Piotr Wilczek2d8f1e22013-11-20 10:43:49 +010087
Piotr Wilczek2d8f1e22013-11-20 10:43:49 +010088 i2c_bus->clock_frequency = speed;
89
Simon Glass37b8eb32016-11-23 06:34:43 -070090 i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
Jaehoon Chunga2987122017-01-09 14:47:51 +090091 SYS_I2C_S3C24X0_SLAVE_ADDR);
Piotr Wilczek2d8f1e22013-11-20 10:43:49 +010092
93 return 0;
94}
95
Naveen Krishna Ch296a4612013-10-15 16:02:44 +053096/*
wdenkfc3e2162003-10-08 22:33:00 +000097 * cmd_type is 0 for write, 1 for read.
98 *
99 * addr_len can take any value from 0-255, it is only limited
100 * by the char, we could make it larger if needed. If it is
101 * 0 we skip the address write cycle.
102 */
Rajeshwari Shindeab7e52b2012-07-23 21:23:53 +0000103static int i2c_transfer(struct s3c24x0_i2c *i2c,
104 unsigned char cmd_type,
105 unsigned char chip,
106 unsigned char addr[],
107 unsigned char addr_len,
108 unsigned char data[],
109 unsigned short data_len)
wdenk1cb8e982003-03-06 21:55:29 +0000110{
Naveen Krishna Che4e24022013-10-15 16:01:43 +0530111 int i = 0, result;
112 ulong start_time = get_timer(0);
wdenk1cb8e982003-03-06 21:55:29 +0000113
wdenkfc3e2162003-10-08 22:33:00 +0000114 if (data == 0 || data_len == 0) {
115 /*Don't support data transfer of no length or to address 0 */
Rajeshwari Shindeab7e52b2012-07-23 21:23:53 +0000116 debug("i2c_transfer: bad call\n");
wdenkfc3e2162003-10-08 22:33:00 +0000117 return I2C_NOK;
118 }
wdenk1cb8e982003-03-06 21:55:29 +0000119
Naveen Krishna Che4e24022013-10-15 16:01:43 +0530120 while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
121 if (get_timer(start_time) > I2C_TIMEOUT_MS)
122 return I2C_NOK_TOUT;
wdenkfc3e2162003-10-08 22:33:00 +0000123 }
wdenk1cb8e982003-03-06 21:55:29 +0000124
Rajeshwari Shindeab7e52b2012-07-23 21:23:53 +0000125 writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
Naveen Krishna Che4e24022013-10-15 16:01:43 +0530126
127 /* Get the slave chip address going */
128 writel(chip, &i2c->iicds);
129 if ((cmd_type == I2C_WRITE) || (addr && addr_len))
130 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
131 &i2c->iicstat);
132 else
133 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
134 &i2c->iicstat);
135
136 /* Wait for chip address to transmit. */
137 result = WaitForXfer(i2c);
138 if (result != I2C_OK)
139 goto bailout;
140
141 /* If register address needs to be transmitted - do it now. */
142 if (addr && addr_len) {
143 while ((i < addr_len) && (result == I2C_OK)) {
144 writel(addr[i++], &i2c->iicds);
Simon Glass26ea7682015-07-02 18:15:46 -0600145 read_write_byte(i2c);
Naveen Krishna Che4e24022013-10-15 16:01:43 +0530146 result = WaitForXfer(i2c);
147 }
148 i = 0;
149 if (result != I2C_OK)
150 goto bailout;
151 }
wdenk1cb8e982003-03-06 21:55:29 +0000152
wdenkfc3e2162003-10-08 22:33:00 +0000153 switch (cmd_type) {
wdenk48b42612003-06-19 23:01:32 +0000154 case I2C_WRITE:
Naveen Krishna Che4e24022013-10-15 16:01:43 +0530155 while ((i < data_len) && (result == I2C_OK)) {
156 writel(data[i++], &i2c->iicds);
Simon Glass26ea7682015-07-02 18:15:46 -0600157 read_write_byte(i2c);
Rajeshwari Shindeab7e52b2012-07-23 21:23:53 +0000158 result = WaitForXfer(i2c);
Naveen Krishna Che4e24022013-10-15 16:01:43 +0530159 }
wdenkfc3e2162003-10-08 22:33:00 +0000160 break;
wdenk1cb8e982003-03-06 21:55:29 +0000161
wdenk48b42612003-06-19 23:01:32 +0000162 case I2C_READ:
wdenkfc3e2162003-10-08 22:33:00 +0000163 if (addr && addr_len) {
Naveen Krishna Che4e24022013-10-15 16:01:43 +0530164 /*
165 * Register address has been sent, now send slave chip
166 * address again to start the actual read transaction.
167 */
C Naumand9abba82010-10-26 23:04:31 +0900168 writel(chip, &i2c->iicds);
wdenk1cb8e982003-03-06 21:55:29 +0000169
Naveen Krishna Che4e24022013-10-15 16:01:43 +0530170 /* Generate a re-START. */
Rajeshwari Shindecb466c02013-02-19 02:19:45 +0000171 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
172 &i2c->iicstat);
Simon Glass26ea7682015-07-02 18:15:46 -0600173 read_write_byte(i2c);
Rajeshwari Shindeab7e52b2012-07-23 21:23:53 +0000174 result = WaitForXfer(i2c);
wdenkfc3e2162003-10-08 22:33:00 +0000175
Naveen Krishna Che4e24022013-10-15 16:01:43 +0530176 if (result != I2C_OK)
177 goto bailout;
wdenk1cb8e982003-03-06 21:55:29 +0000178 }
179
Naveen Krishna Che4e24022013-10-15 16:01:43 +0530180 while ((i < data_len) && (result == I2C_OK)) {
181 /* disable ACK for final READ */
182 if (i == data_len - 1)
183 writel(readl(&i2c->iiccon)
184 & ~I2CCON_ACKGEN,
185 &i2c->iiccon);
Simon Glass26ea7682015-07-02 18:15:46 -0600186 read_write_byte(i2c);
Naveen Krishna Che4e24022013-10-15 16:01:43 +0530187 result = WaitForXfer(i2c);
188 data[i++] = readl(&i2c->iicds);
189 }
190 if (result == I2C_NACK)
191 result = I2C_OK; /* Normal terminated read. */
wdenkfc3e2162003-10-08 22:33:00 +0000192 break;
wdenk1cb8e982003-03-06 21:55:29 +0000193
194 default:
Rajeshwari Shindeab7e52b2012-07-23 21:23:53 +0000195 debug("i2c_transfer: bad call\n");
wdenkfc3e2162003-10-08 22:33:00 +0000196 result = I2C_NOK;
197 break;
198 }
wdenk1cb8e982003-03-06 21:55:29 +0000199
Naveen Krishna Che4e24022013-10-15 16:01:43 +0530200bailout:
201 /* Send STOP. */
202 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
Simon Glass26ea7682015-07-02 18:15:46 -0600203 read_write_byte(i2c);
Naveen Krishna Che4e24022013-10-15 16:01:43 +0530204
Rajeshwari Shindeab7e52b2012-07-23 21:23:53 +0000205 return result;
wdenk1cb8e982003-03-06 21:55:29 +0000206}
207
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100208static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags)
wdenk1cb8e982003-03-06 21:55:29 +0000209{
Simon Glass9a1bff62016-11-23 06:34:42 -0700210 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
wdenkfc3e2162003-10-08 22:33:00 +0000211 uchar buf[1];
Naveen Krishna Ch296a4612013-10-15 16:02:44 +0530212 int ret;
wdenk1cb8e982003-03-06 21:55:29 +0000213
wdenkfc3e2162003-10-08 22:33:00 +0000214 buf[0] = 0;
wdenk1cb8e982003-03-06 21:55:29 +0000215
wdenkfc3e2162003-10-08 22:33:00 +0000216 /*
217 * What is needed is to send the chip address and verify that the
218 * address was <ACK>ed (i.e. there was a chip at that address which
219 * drove the data line low).
220 */
Simon Glass37b8eb32016-11-23 06:34:43 -0700221 ret = i2c_transfer(i2c_bus->regs, I2C_READ, chip << 1, 0, 0, buf, 1);
Naveen Krishna Ch296a4612013-10-15 16:02:44 +0530222
Naveen Krishna Ch296a4612013-10-15 16:02:44 +0530223 return ret != I2C_OK;
wdenk1cb8e982003-03-06 21:55:29 +0000224}
225
Simon Glass45d9ae82015-07-02 18:15:47 -0600226static int s3c24x0_do_msg(struct s3c24x0_i2c_bus *i2c_bus, struct i2c_msg *msg,
227 int seq)
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100228{
Simon Glass45d9ae82015-07-02 18:15:47 -0600229 struct s3c24x0_i2c *i2c = i2c_bus->regs;
230 bool is_read = msg->flags & I2C_M_RD;
231 uint status;
232 uint addr;
233 int ret, i;
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100234
Simon Glass45d9ae82015-07-02 18:15:47 -0600235 if (!seq)
236 setbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
237
238 /* Get the slave chip address going */
239 addr = msg->addr << 1;
240 writel(addr, &i2c->iicds);
241 status = I2C_TXRX_ENA | I2C_START_STOP;
242 if (is_read)
243 status |= I2C_MODE_MR;
244 else
245 status |= I2C_MODE_MT;
246 writel(status, &i2c->iicstat);
247 if (seq)
248 read_write_byte(i2c);
249
250 /* Wait for chip address to transmit */
251 ret = WaitForXfer(i2c);
252 if (ret)
253 goto err;
254
255 if (is_read) {
256 for (i = 0; !ret && i < msg->len; i++) {
257 /* disable ACK for final READ */
258 if (i == msg->len - 1)
259 clrbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
260 read_write_byte(i2c);
261 ret = WaitForXfer(i2c);
262 msg->buf[i] = readl(&i2c->iicds);
263 }
264 if (ret == I2C_NACK)
265 ret = I2C_OK; /* Normal terminated read */
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100266 } else {
Simon Glass45d9ae82015-07-02 18:15:47 -0600267 for (i = 0; !ret && i < msg->len; i++) {
268 writel(msg->buf[i], &i2c->iicds);
269 read_write_byte(i2c);
270 ret = WaitForXfer(i2c);
271 }
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100272 }
273
Simon Glass45d9ae82015-07-02 18:15:47 -0600274err:
275 return ret;
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100276}
277
278static int s3c24x0_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
279 int nmsgs)
280{
281 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
Simon Glass45d9ae82015-07-02 18:15:47 -0600282 struct s3c24x0_i2c *i2c = i2c_bus->regs;
283 ulong start_time;
284 int ret, i;
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100285
Simon Glass45d9ae82015-07-02 18:15:47 -0600286 start_time = get_timer(0);
287 while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
288 if (get_timer(start_time) > I2C_TIMEOUT_MS) {
289 debug("Timeout\n");
290 return -ETIMEDOUT;
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100291 }
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100292 }
293
Simon Glass45d9ae82015-07-02 18:15:47 -0600294 for (ret = 0, i = 0; !ret && i < nmsgs; i++)
295 ret = s3c24x0_do_msg(i2c_bus, &msg[i], i);
296
297 /* Send STOP */
298 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
299 read_write_byte(i2c);
300
301 return ret ? -EREMOTEIO : 0;
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100302}
303
304static int s3c_i2c_ofdata_to_platdata(struct udevice *dev)
305{
306 const void *blob = gd->fdt_blob;
307 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
Simon Glass37b8eb32016-11-23 06:34:43 -0700308 int node;
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100309
Simon Glasse160f7d2017-01-17 16:52:55 -0700310 node = dev_of_offset(dev);
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100311
Simon Glassa821c4a2017-05-17 17:18:05 -0600312 i2c_bus->regs = (struct s3c24x0_i2c *)devfdt_get_addr(dev);
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100313
314 i2c_bus->id = pinmux_decode_periph_id(blob, node);
315
Simon Glassf3d46152020-01-23 11:48:22 -0700316 i2c_bus->clock_frequency =
317 dev_read_u32_default(dev, "clock-frequency",
318 I2C_SPEED_STANDARD_RATE);
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100319 i2c_bus->node = node;
320 i2c_bus->bus_num = dev->seq;
321
Simon Glass37b8eb32016-11-23 06:34:43 -0700322 exynos_pinmux_config(i2c_bus->id, 0);
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100323
324 i2c_bus->active = true;
325
326 return 0;
327}
328
329static const struct dm_i2c_ops s3c_i2c_ops = {
330 .xfer = s3c24x0_i2c_xfer,
331 .probe_chip = s3c24x0_i2c_probe,
332 .set_bus_speed = s3c24x0_i2c_set_bus_speed,
333};
334
335static const struct udevice_id s3c_i2c_ids[] = {
Simon Glass37b8eb32016-11-23 06:34:43 -0700336 { .compatible = "samsung,s3c2440-i2c" },
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100337 { }
338};
339
340U_BOOT_DRIVER(i2c_s3c) = {
341 .name = "i2c_s3c",
342 .id = UCLASS_I2C,
343 .of_match = s3c_i2c_ids,
344 .ofdata_to_platdata = s3c_i2c_ofdata_to_platdata,
Przemyslaw Marczak8dfcbaa2015-01-27 13:36:36 +0100345 .priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus),
346 .ops = &s3c_i2c_ops,
347};