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wdenk56f94be2002-11-05 16:35:14 +00001/*
wdenk0608e042004-03-25 19:29:38 +00002 * (C) Copyright 2000-2004
wdenk56f94be2002-11-05 16:35:14 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
wdenk56f94be2002-11-05 16:35:14 +00007 */
8
9#include <common.h>
Heiko Schochere604e402010-07-19 23:46:48 +020010#include <command.h>
Heiko Schocher8011ec62010-07-19 23:47:08 +020011#include <libfdt.h>
wdenk56f94be2002-11-05 16:35:14 +000012#include <mpc8xx.h>
Heiko Schochere604e402010-07-19 23:46:48 +020013#include <hwconfig.h>
14#include <i2c.h>
wdenk0608e042004-03-25 19:29:38 +000015#include "../common/kup.h"
Heiko Schochere604e402010-07-19 23:46:48 +020016#include <asm/io.h>
17
18static unsigned char swapbyte(unsigned char c);
19static int read_diag(void);
wdenk56f94be2002-11-05 16:35:14 +000020
Wolfgang Denkd87080b2006-03-31 18:32:53 +020021DECLARE_GLOBAL_DATA_PTR;
22
Heiko Schochere604e402010-07-19 23:46:48 +020023/* ----------------------------------------------------------------------- */
wdenk56f94be2002-11-05 16:35:14 +000024
25#define _NOT_USED_ 0xFFFFFFFF
26
wdenk0608e042004-03-25 19:29:38 +000027const uint sdram_table[] = {
wdenk56f94be2002-11-05 16:35:14 +000028 /*
29 * Single Read. (Offset 0 in UPMA RAM)
30 */
wdenk682011f2003-06-03 23:54:09 +000031 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
Heiko Schochere604e402010-07-19 23:46:48 +020032 0x1FF77C47, /* last */
wdenk56f94be2002-11-05 16:35:14 +000033
34 /*
35 * SDRAM Initialization (offset 5 in UPMA RAM)
36 *
37 * This is no UPM entry point. The following definition uses
38 * the remaining space to establish an initialization
39 * sequence, which is executed by a RUN command.
40 *
41 */
Heiko Schochere604e402010-07-19 23:46:48 +020042 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
wdenk56f94be2002-11-05 16:35:14 +000043
44 /*
45 * Burst Read. (Offset 8 in UPMA RAM)
46 */
wdenk682011f2003-06-03 23:54:09 +000047 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
Heiko Schochere604e402010-07-19 23:46:48 +020048 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
wdenk56f94be2002-11-05 16:35:14 +000049 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
50 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
51
52 /*
53 * Single Write. (Offset 18 in UPMA RAM)
54 */
Heiko Schochere604e402010-07-19 23:46:48 +020055 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
wdenk56f94be2002-11-05 16:35:14 +000056 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
57
58 /*
59 * Burst Write. (Offset 20 in UPMA RAM)
60 */
wdenk682011f2003-06-03 23:54:09 +000061 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
Heiko Schochere604e402010-07-19 23:46:48 +020062 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
63 _NOT_USED_,
wdenk56f94be2002-11-05 16:35:14 +000064 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
65 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
66
67 /*
68 * Refresh (Offset 30 in UPMA RAM)
69 */
wdenk682011f2003-06-03 23:54:09 +000070 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
Heiko Schochere604e402010-07-19 23:46:48 +020071 0xFFFFFC84, 0xFFFFFC07, /* last */
72 _NOT_USED_, _NOT_USED_,
wdenk56f94be2002-11-05 16:35:14 +000073 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
74
75 /*
76 * Exception. (Offset 3c in UPMA RAM)
77 */
Heiko Schochere604e402010-07-19 23:46:48 +020078 0x7FFFFC07, /* last */
79 _NOT_USED_, _NOT_USED_, _NOT_USED_,
wdenk56f94be2002-11-05 16:35:14 +000080};
81
Heiko Schochere604e402010-07-19 23:46:48 +020082/* ----------------------------------------------------------------------- */
wdenk56f94be2002-11-05 16:35:14 +000083
84/*
85 * Check Board Identity:
86 */
87
Heiko Schochere604e402010-07-19 23:46:48 +020088int checkboard(void)
wdenk56f94be2002-11-05 16:35:14 +000089{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
Heiko Schochere604e402010-07-19 23:46:48 +020091 uchar rev,mod,tmp,pcf,ak_rev,ak_mod;
wdenk56f94be2002-11-05 16:35:14 +000092
wdenk0608e042004-03-25 19:29:38 +000093 /*
94 * Init ChipSelect #4 (CAN + HW-Latch)
95 */
Heiko Schochere604e402010-07-19 23:46:48 +020096 out_be32(&immap->im_memctl.memc_or4, CONFIG_SYS_OR4);
97 out_be32(&immap->im_memctl.memc_br4, CONFIG_SYS_BR4);
98
99 /*
100 * Init ChipSelect #5 (S1D13768)
101 */
102 out_be32(&immap->im_memctl.memc_or5, CONFIG_SYS_OR5);
103 out_be32(&immap->im_memctl.memc_br5, CONFIG_SYS_BR5);
104
105 tmp = swapbyte(in_8((unsigned char*) LATCH_ADDR));
106 rev = (tmp & 0xF8) >> 3;
107 mod = (tmp & 0x07);
108
109 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
110
111 if (read_diag())
112 gd->flags &= ~GD_FLG_SILENT;
113
114 printf("Board: KUP4K Rev %d.%d AK:",rev,mod);
115 /*
116 * TI Application report: Before using the IO as an input,
117 * a high must be written to the IO first
118 */
119 pcf = 0xFF;
120 i2c_write(0x21, 0, 0 , &pcf, 1);
121 if (i2c_read(0x21, 0, 0, &pcf, 1)) {
122 puts("n/a\n");
123 } else {
124 ak_rev = (pcf & 0xF8) >> 3;
125 ak_mod = (pcf & 0x07);
126 printf("%d.%d\n", ak_rev, ak_mod);
127 }
128 return 0;
wdenk56f94be2002-11-05 16:35:14 +0000129}
130
Heiko Schochere604e402010-07-19 23:46:48 +0200131/* ----------------------------------------------------------------------- */
wdenk56f94be2002-11-05 16:35:14 +0000132
Heiko Schochere604e402010-07-19 23:46:48 +0200133
134phys_size_t initdram(int board_type)
wdenk56f94be2002-11-05 16:35:14 +0000135{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenk682011f2003-06-03 23:54:09 +0000137 volatile memctl8xx_t *memctl = &immap->im_memctl;
Heiko Schochere604e402010-07-19 23:46:48 +0200138 long int size = 0;
Wolfgang Denkb8221a32011-11-04 15:55:34 +0000139 uchar *latch, rev, tmp;
wdenk56f94be2002-11-05 16:35:14 +0000140
wdenk682011f2003-06-03 23:54:09 +0000141 /*
Heiko Schochere604e402010-07-19 23:46:48 +0200142 * Init ChipSelect #4 (CAN + HW-Latch) to determine Hardware Revision
143 * Rev 1..6 -> 48 MB RAM; Rev >= 7 -> 96 MB
wdenk682011f2003-06-03 23:54:09 +0000144 */
Heiko Schochere604e402010-07-19 23:46:48 +0200145 out_be32(&immap->im_memctl.memc_or4, CONFIG_SYS_OR4);
146 out_be32(&immap->im_memctl.memc_br4, CONFIG_SYS_BR4);
wdenk56f94be2002-11-05 16:35:14 +0000147
Heiko Schochere604e402010-07-19 23:46:48 +0200148 latch = (uchar *)0x90000200;
149 tmp = swapbyte(*latch);
150 rev = (tmp & 0xF8) >> 3;
wdenk56f94be2002-11-05 16:35:14 +0000151
Heiko Schochere604e402010-07-19 23:46:48 +0200152 upmconfig(UPMA, (uint *) sdram_table,
153 sizeof (sdram_table) / sizeof (uint));
wdenk682011f2003-06-03 23:54:09 +0000154
Heiko Schochere604e402010-07-19 23:46:48 +0200155 out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
wdenk56f94be2002-11-05 16:35:14 +0000156
Heiko Schochere604e402010-07-19 23:46:48 +0200157 out_be32(&memctl->memc_mar, 0x00000088);
158 /* no refresh yet */
159 if(rev >= 7) {
160 out_be32(&memctl->memc_mamr,
161 CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)));
162 } else {
163 out_be32(&memctl->memc_mamr,
164 CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)));
165 }
wdenk56f94be2002-11-05 16:35:14 +0000166
Heiko Schochere604e402010-07-19 23:46:48 +0200167 udelay(200);
wdenk56f94be2002-11-05 16:35:14 +0000168
wdenk682011f2003-06-03 23:54:09 +0000169 /* perform SDRAM initializsation sequence */
wdenk56f94be2002-11-05 16:35:14 +0000170
Heiko Schochere604e402010-07-19 23:46:48 +0200171 /* SDRAM bank 0 */
172 out_be32(&memctl->memc_mcr, 0x80002105);
173 udelay(1);
174 out_be32(&memctl->memc_mcr, 0x80002830); /* execute twice */
175 udelay(1);
176 out_be32(&memctl->memc_mcr, 0x80002106); /* RUN MRS Pattern from loc 6 */
177 udelay(1);
wdenk56f94be2002-11-05 16:35:14 +0000178
Heiko Schochere604e402010-07-19 23:46:48 +0200179 /* SDRAM bank 1 */
180 out_be32(&memctl->memc_mcr, 0x80004105);
181 udelay(1);
182 out_be32(&memctl->memc_mcr, 0x80004830); /* execute twice */
183 udelay(1);
184 out_be32(&memctl->memc_mcr, 0x80004106); /* RUN MRS Pattern from loc 6 */
185 udelay(1);
wdenk56f94be2002-11-05 16:35:14 +0000186
Heiko Schochere604e402010-07-19 23:46:48 +0200187 /* SDRAM bank 2 */
188 out_be32(&memctl->memc_mcr, 0x80006105);
189 udelay(1);
190 out_be32(&memctl->memc_mcr, 0x80006830); /* execute twice */
191 udelay(1);
192 out_be32(&memctl->memc_mcr, 0x80006106); /* RUN MRS Pattern from loc 6 */
193 udelay(1);
wdenk56f94be2002-11-05 16:35:14 +0000194
Heiko Schochere604e402010-07-19 23:46:48 +0200195 setbits_be32(&memctl->memc_mamr, MAMR_PTAE); /* enable refresh */
196 udelay(1000);
wdenk56f94be2002-11-05 16:35:14 +0000197
Heiko Schochere604e402010-07-19 23:46:48 +0200198 out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
199 udelay(1000);
200 if(rev >= 7) {
201 size = 32 * 3 * 1024 * 1024;
202 out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_9COL);
203 out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_9COL);
204 out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_9COL);
205 out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_9COL);
206 out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_9COL);
207 out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_9COL);
208 } else {
209 size = 16 * 3 * 1024 * 1024;
210 out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_8COL);
211 out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_8COL);
212 out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_8COL);
213 out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_8COL);
214 out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_8COL);
215 out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_8COL);
216 }
217 return (size);
wdenk56f94be2002-11-05 16:35:14 +0000218}
219
Heiko Schochere604e402010-07-19 23:46:48 +0200220/* ----------------------------------------------------------------------- */
wdenk56f94be2002-11-05 16:35:14 +0000221
Heiko Schochere604e402010-07-19 23:46:48 +0200222
223int misc_init_r(void)
wdenk56f94be2002-11-05 16:35:14 +0000224{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenk56f94be2002-11-05 16:35:14 +0000226
wdenk1f53a412002-12-04 23:39:58 +0000227#ifdef CONFIG_IDE_LED
228 /* Configure PA8 as output port */
Heiko Schochere604e402010-07-19 23:46:48 +0200229 setbits_be16(&immap->im_ioport.iop_padir, PA_8);
230 setbits_be16(&immap->im_ioport.iop_paodr, PA_8);
231 clrbits_be16(&immap->im_ioport.iop_papar, PA_8);
232 setbits_be16(&immap->im_ioport.iop_padat, PA_8); /* turn it off */
wdenk1f53a412002-12-04 23:39:58 +0000233#endif
Mike Frysinger9c150102009-02-11 20:09:52 -0500234 load_sernum_ethaddr();
wdenk0608e042004-03-25 19:29:38 +0000235 setenv("hw","4k");
236 poweron_key();
wdenk682011f2003-06-03 23:54:09 +0000237 return (0);
wdenk56f94be2002-11-05 16:35:14 +0000238}
239
wdenk56f94be2002-11-05 16:35:14 +0000240
Heiko Schochere604e402010-07-19 23:46:48 +0200241static int read_diag(void)
wdenk682011f2003-06-03 23:54:09 +0000242{
Heiko Schochere604e402010-07-19 23:46:48 +0200243 int diag;
244 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
wdenk682011f2003-06-03 23:54:09 +0000245
Heiko Schochere604e402010-07-19 23:46:48 +0200246 clrbits_be16(&immr->im_ioport.iop_pcdir, PC_4); /* input */
247 clrbits_be16(&immr->im_ioport.iop_pcpar, PC_4); /* gpio */
248 setbits_be16(&immr->im_ioport.iop_pcdir, PC_5); /* output */
249 clrbits_be16(&immr->im_ioport.iop_pcpar, PC_4); /* gpio */
250 setbits_be16(&immr->im_ioport.iop_pcdat, PC_5); /* 1 */
251 udelay(500);
252 if (in_be16(&immr->im_ioport.iop_pcdat) & PC_4) {
253 clrbits_be16(&immr->im_ioport.iop_pcdat, PC_5);/* 0 */
254 udelay(500);
255 if(in_be16(&immr->im_ioport.iop_pcdat) & PC_4)
256 diag = 0;
wdenk0608e042004-03-25 19:29:38 +0000257 else
Heiko Schochere604e402010-07-19 23:46:48 +0200258 diag = 1;
wdenk0608e042004-03-25 19:29:38 +0000259 } else {
Heiko Schochere604e402010-07-19 23:46:48 +0200260 diag = 0;
wdenk56f94be2002-11-05 16:35:14 +0000261 }
Heiko Schochere604e402010-07-19 23:46:48 +0200262 clrbits_be16(&immr->im_ioport.iop_pcdir, PC_5); /* input */
263 return (diag);
wdenk56f94be2002-11-05 16:35:14 +0000264}
Heiko Schochere604e402010-07-19 23:46:48 +0200265
266static unsigned char swapbyte(unsigned char c)
267{
268 unsigned char result = 0;
269 int i = 0;
270
271 for(i = 0; i < 8; ++i) {
272 result = result << 1;
273 result |= (c & 1);
274 c = c >> 1;
275 }
276 return result;
277}
Heiko Schocher8011ec62010-07-19 23:47:08 +0200278
279/*
280 * Device Tree Support
281 */
282#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
283void ft_board_setup(void *blob, bd_t *bd)
284{
285 ft_cpu_setup(blob, bd);
286}
287#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */