| wdenk | 983fda8 | 2004-10-28 00:09:35 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2004, Freescale Inc. |
| 3 | * TsiChung Liew, Tsi-Chung.Liew@freescale.com |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #include <common.h> |
| 25 | #include <mpc8220.h> |
| 26 | #include <asm/processor.h> |
| 27 | #include <asm/mmu.h> |
| 28 | |
| 29 | void setupBat (ulong size) |
| 30 | { |
| 31 | ulong batu, batl; |
| 32 | int blocksize = 0; |
| 33 | |
| 34 | /* Flash 0 */ |
| 35 | #if defined (CFG_AMD_BOOT) |
| 36 | batu = CFG_FLASH0_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; |
| 37 | #else |
| 38 | batu = CFG_FLASH0_BASE | (BL_16M << 2) | BPP_RW | BPP_RX; |
| 39 | #endif |
| 40 | batl = CFG_FLASH0_BASE | 0x22; |
| 41 | write_bat (IBAT0, batu, batl); |
| 42 | write_bat (DBAT0, batu, batl); |
| 43 | |
| 44 | /* Flash 1 */ |
| 45 | #if defined (CFG_AMD_BOOT) |
| 46 | batu = CFG_FLASH1_BASE | (BL_16M << 2) | BPP_RW | BPP_RX; |
| 47 | #else |
| 48 | batu = CFG_FLASH1_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; |
| 49 | #endif |
| 50 | batl = CFG_FLASH1_BASE | 0x22; |
| 51 | write_bat (IBAT1, batu, batl); |
| 52 | write_bat (DBAT1, batu, batl); |
| 53 | |
| 54 | /* CPLD */ |
| 55 | batu = CFG_CPLD_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; |
| 56 | batl = CFG_CPLD_BASE | 0x22; |
| 57 | write_bat (IBAT2, 0, 0); |
| 58 | write_bat (DBAT2, batu, batl); |
| 59 | |
| 60 | /* FPGA */ |
| 61 | batu = CFG_FPGA_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; |
| 62 | batl = CFG_FPGA_BASE | 0x22; |
| 63 | write_bat (IBAT3, 0, 0); |
| 64 | write_bat (DBAT3, batu, batl); |
| 65 | |
| 66 | /* MBAR - Data only */ |
| 67 | batu = CFG_MBAR | BPP_RW | BPP_RX; |
| 68 | batl = CFG_MBAR | 0x22; |
| 69 | mtspr (IBAT4L, 0); |
| 70 | mtspr (IBAT4U, 0); |
| 71 | mtspr (DBAT4L, batl); |
| 72 | mtspr (DBAT4U, batu); |
| 73 | |
| 74 | /* MBAR - SRAM */ |
| 75 | batu = CFG_SRAM_BASE | BPP_RW | BPP_RX; |
| 76 | batl = CFG_SRAM_BASE | 0x42; |
| 77 | mtspr (IBAT5L, batl); |
| 78 | mtspr (IBAT5U, batu); |
| 79 | mtspr (DBAT5L, batl); |
| 80 | mtspr (DBAT5U, batu); |
| 81 | |
| 82 | if (size <= 0x800000) /* 8MB */ |
| 83 | blocksize = BL_8M << 2; |
| 84 | else if (size <= 0x1000000) /* 16MB */ |
| 85 | blocksize = BL_16M << 2; |
| 86 | else if (size <= 0x2000000) /* 32MB */ |
| 87 | blocksize = BL_32M << 2; |
| 88 | else if (size <= 0x4000000) /* 64MB */ |
| 89 | blocksize = BL_64M << 2; |
| 90 | else if (size <= 0x8000000) /* 128MB */ |
| 91 | blocksize = BL_128M << 2; |
| 92 | else if (size <= 0x10000000) /* 256MB */ |
| 93 | blocksize = BL_256M << 2; |
| 94 | |
| 95 | /* Memory */ |
| 96 | batu = CFG_SDRAM_BASE | blocksize | BPP_RW | BPP_RX; |
| 97 | batl = CFG_SDRAM_BASE | 0x42; |
| 98 | mtspr (IBAT6L, batl); |
| 99 | mtspr (IBAT6U, batu); |
| 100 | mtspr (DBAT6L, batl); |
| 101 | mtspr (DBAT6U, batu); |
| 102 | |
| 103 | /* memory size is less than 256MB */ |
| 104 | if (size <= 0x10000000) { |
| 105 | /* Nothing */ |
| 106 | batu = 0; |
| 107 | batl = 0; |
| 108 | } else { |
| 109 | size -= 0x10000000; |
| 110 | if (size <= 0x800000) /* 8MB */ |
| 111 | blocksize = BL_8M << 2; |
| 112 | else if (size <= 0x1000000) /* 16MB */ |
| 113 | blocksize = BL_16M << 2; |
| 114 | else if (size <= 0x2000000) /* 32MB */ |
| 115 | blocksize = BL_32M << 2; |
| 116 | else if (size <= 0x4000000) /* 64MB */ |
| 117 | blocksize = BL_64M << 2; |
| 118 | else if (size <= 0x8000000) /* 128MB */ |
| 119 | blocksize = BL_128M << 2; |
| 120 | else if (size <= 0x10000000) /* 256MB */ |
| 121 | blocksize = BL_256M << 2; |
| 122 | |
| 123 | batu = (CFG_SDRAM_BASE + |
| 124 | 0x10000000) | blocksize | BPP_RW | BPP_RX; |
| 125 | batl = (CFG_SDRAM_BASE + 0x10000000) | 0x42; |
| 126 | } |
| 127 | |
| 128 | mtspr (IBAT7L, batl); |
| 129 | mtspr (IBAT7U, batu); |
| 130 | mtspr (DBAT7L, batl); |
| 131 | mtspr (DBAT7U, batu); |
| 132 | } |
| 133 | |
| 134 | long int initdram (int board_type) |
| 135 | { |
| 136 | ulong size; |
| 137 | |
| 138 | size = dramSetup (); |
| 139 | |
| 140 | /* if iCache ad dCache is defined */ |
| 141 | #if (CONFIG_COMMANDS & CFG_CMD_CACHE) |
| 142 | /* setupBat(size);*/ |
| 143 | #endif |
| 144 | |
| 145 | return size; |
| 146 | } |
| 147 | |
| 148 | int checkboard (void) |
| 149 | { |
| 150 | puts ("Board: Alaska MPC8220 Evaluation Board\n"); |
| 151 | |
| 152 | return 0; |
| 153 | } |