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Heiko Schocher62ddcf02010-02-18 08:08:25 +01001/*
2 * (C) Copyright 2010
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 */
10
11#ifndef __CONFIG_KM83XX_H
12#define __CONFIG_KM83XX_H
13
14/* include common defines/options for all Keymile boards */
15#include "keymile-common.h"
16#include "km-powerpc.h"
17
Andreas Hubercf736392012-05-04 10:30:16 +020018#ifndef MTDIDS_DEFAULT
19# define MTDIDS_DEFAULT "nor0=boot"
20#endif /* MTDIDS_DEFAULT */
21
22#ifndef MTDPARTS_DEFAULT
23# define MTDPARTS_DEFAULT "mtdparts=" \
Heiko Schocher62ddcf02010-02-18 08:08:25 +010024 "boot:" \
25 "768k(u-boot)," \
26 "128k(env)," \
27 "128k(envred)," \
Andreas Hubercf736392012-05-04 10:30:16 +020028 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
29#endif /* MTDPARTS_DEFAULT */
Heiko Schocher62ddcf02010-02-18 08:08:25 +010030
31#define CONFIG_MISC_INIT_R
32/*
33 * System Clock Setup
34 */
35#define CONFIG_83XX_CLKIN 66000000
36#define CONFIG_SYS_CLK_FREQ 66000000
37#define CONFIG_83XX_PCICLK 66000000
38
39/*
40 * IMMR new address
41 */
42#define CONFIG_SYS_IMMR 0xE0000000
43
44/*
45 * Bus Arbitration Configuration Register (ACR)
46 */
47#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
48#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
49#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
50#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
51
52/*
53 * DDR Setup
54 */
55#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
56#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
Holger Brunck0f2b7212012-03-21 13:42:46 +010057#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
58
Heiko Schocher62ddcf02010-02-18 08:08:25 +010059#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
60#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
61 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
62
63#define CFG_83XX_DDR_USES_CS0
64
65/*
66 * Manually set up DDR parameters
67 */
68#define CONFIG_DDR_II
69#define CONFIG_SYS_DDR_SIZE 2048 /* MB */
70
71/*
72 * The reserved memory
73 */
74#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
75#define CONFIG_SYS_FLASH_BASE 0xF0000000
76
77#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
78#define CONFIG_SYS_RAMBOOT
79#endif
80
81/* Reserve 768 kB for Mon */
82#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
83
84/*
85 * Initial RAM Base Address Setup
86 */
87#define CONFIG_SYS_INIT_RAM_LOCK
88#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
89#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
90#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
91#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
92 GENERATED_GBL_DATA_SIZE)
93
94/*
95 * Init Local Bus Memory Controller:
96 *
97 * Bank Bus Machine PortSz Size Device
98 * ---- --- ------- ------ ----- ------
99 * 0 Local GPCM 16 bit 256MB FLASH
100 * 1 Local GPCM 8 bit 128MB GPIO/PIGGY
101 *
102 */
103/*
104 * FLASH on the Local Bus
105 */
106#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
107#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
108#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
109#define CONFIG_SYS_FLASH_PROTECTION
110#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
111
112#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500113#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100114
115#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500116 BR_PS_16 | /* 16 bit port size */ \
117 BR_MS_GPCM | /* MSEL = GPCM */ \
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100118 BR_V)
119
120#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
121 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
122 OR_GPCM_SCY_5 | \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500123 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100124
125#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
126#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
127#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
128
129/*
130 * PRIO1/PIGGY on the local bus CS1
131 */
Heiko Schocher8ed74342011-03-08 10:47:39 +0100132/* Window base at flash base */
133#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500134#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100135
Heiko Schocher8ed74342011-03-08 10:47:39 +0100136#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500137 BR_PS_8 | /* 8 bit port size */ \
138 BR_MS_GPCM | /* MSEL = GPCM */ \
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100139 BR_V)
Heiko Schocher8ed74342011-03-08 10:47:39 +0100140#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100141 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
142 OR_GPCM_SCY_2 | \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500143 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100144
145/*
146 * Serial Port
147 */
148#define CONFIG_CONS_INDEX 1
149#define CONFIG_SYS_NS16550
150#define CONFIG_SYS_NS16550_SERIAL
151#define CONFIG_SYS_NS16550_REG_SIZE 1
152#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
153
154#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
155#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
156
157/* Pass open firmware flat tree */
158#define CONFIG_OF_LIBFDT
159#define CONFIG_OF_BOARD_SETUP
160#define CONFIG_OF_STDOUT_VIA_ALIAS
161
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100162/*
163 * QE UEC ethernet configuration
164 */
165#define CONFIG_UEC_ETH
166#define CONFIG_ETHPRIME "UEC0"
167
Karlheinz Jerg5bcd64c2013-01-21 03:55:18 +0000168#if !defined(CONFIG_MPC8309)
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100169#define CONFIG_UEC_ETH1 /* GETH1 */
170#define UEC_VERBOSE_DEBUG 1
Karlheinz Jerg5bcd64c2013-01-21 03:55:18 +0000171#endif
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100172
173#ifdef CONFIG_UEC_ETH1
174#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
175#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
176#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
177#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
178#define CONFIG_SYS_UEC1_PHY_ADDR 0
179#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
180#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
181#endif
182
183/*
184 * Environment
185 */
186
187#ifndef CONFIG_SYS_RAMBOOT
188#define CONFIG_ENV_IS_IN_FLASH
189#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
190 CONFIG_SYS_MONITOR_LEN)
191#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
192#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
193
194/* Address and size of Redundant Environment Sector */
195#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
196 CONFIG_ENV_SECT_SIZE)
197#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
198
199#else /* CFG_SYS_RAMBOOT */
200#define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
201#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
202#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
203#define CONFIG_ENV_SIZE 0x2000
204#endif /* CFG_SYS_RAMBOOT */
205
206/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200207#define CONFIG_SYS_I2C
208#define CONFIG_SYS_NUM_I2C_BUSES 4
209#define CONFIG_SYS_I2C_MAX_HOPS 1
210#define CONFIG_SYS_I2C_FSL
211#define CONFIG_SYS_FSL_I2C_SPEED 200000
212#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
213#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
214#define CONFIG_SYS_I2C_OFFSET 0x3000
215#define CONFIG_SYS_FSL_I2C2_SPEED 200000
216#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
217#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
218#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
219 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
220 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
221 {1, {I2C_NULL_HOP} } }
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100222
Heiko Schocherf3e93612012-10-25 11:07:00 +0200223#define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/
224
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100225/* I2C SYSMON (LM75, AD7414 is almost compatible) */
226#define CONFIG_DTT_LM75 /* ON Semi's LM75 */
227#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */
228#define CONFIG_SYS_DTT_MAX_TEMP 70
229#define CONFIG_SYS_DTT_LOW_TEMP -30
230#define CONFIG_SYS_DTT_HYSTERESIS 3
Heiko Schocher00f792e2012-10-24 13:48:22 +0200231#define CONFIG_SYS_DTT_BUS_NUM 1
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100232
233#if defined(CONFIG_CMD_NAND)
234#define CONFIG_NAND_KMETER1
235#define CONFIG_SYS_MAX_NAND_DEVICE 1
Heiko Schocher8ed74342011-03-08 10:47:39 +0100236#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100237#endif
238
239#if defined(CONFIG_PCI)
240#define CONFIG_CMD_PCI
241#endif
242
243/*
244 * For booting Linux, the board info and command line data
245 * have to be in the first 8 MB of memory, since this is
246 * the maximum mapped by the Linux kernel during initialization.
247 */
248#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
249
250/*
251 * Core HID Setup
252 */
253#define CONFIG_SYS_HID0_INIT 0x000000000
254#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
255 HID0_ENABLE_INSTRUCTION_CACHE)
256#define CONFIG_SYS_HID2 HID2_HBE
257
258/*
259 * MMU Setup
260 */
261
262#define CONFIG_HIGH_BATS 1 /* High BATs supported */
263
264/* DDR: cache cacheable */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500265#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100266 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
267#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
268 BATU_VS | BATU_VP)
269#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
270#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
271
272/* IMMRBAR & PCI IO: cache-inhibit and guarded */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500273#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100274 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
275#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
276 | BATU_VP)
277#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
278#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
279
280/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500281#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
Heiko Schocher8ed74342011-03-08 10:47:39 +0100282 BATL_MEMCOHERENCE)
283#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
284 BATU_VS | BATU_VP)
Joe Hershberger72cd4082011-10-11 23:57:28 -0500285#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100286 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
287#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
288
289/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500290#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100291 BATL_MEMCOHERENCE)
292#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
293 BATU_VS | BATU_VP)
Joe Hershberger72cd4082011-10-11 23:57:28 -0500294#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100295 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
296#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
297
298/* Stack in dcache: cacheable, no memory coherence */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500299#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100300#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
301 BATU_VS | BATU_VP)
302#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
303#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
304
305/*
306 * Internal Definitions
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100307 */
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100308#define BOOTFLASH_START 0xF0000000
309
310#define CONFIG_KM_CONSOLE_TTY "ttyS0"
311
312/*
313 * Environment Configuration
314 */
315#define CONFIG_ENV_OVERWRITE
316#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
317#define CONFIG_KM_DEF_ENV "km-common=empty\0"
318#endif
319
Holger Brunckb648bfc2011-07-04 21:52:52 +0000320#ifndef CONFIG_KM_DEF_ARCH
321#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100322#endif
323
324#define CONFIG_EXTRA_ENV_SETTINGS \
325 CONFIG_KM_DEF_ENV \
Holger Brunckb648bfc2011-07-04 21:52:52 +0000326 CONFIG_KM_DEF_ARCH \
Heiko Schocher62ddcf02010-02-18 08:08:25 +0100327 "newenv=" \
328 "prot off 0xF00C0000 +0x40000 && " \
329 "era 0xF00C0000 +0x40000\0" \
330 "unlock=yes\0" \
331 ""
332
333#if defined(CONFIG_UEC_ETH)
334#define CONFIG_HAS_ETH0
335#endif
336
337#endif /* __CONFIG_KM83XX_H */