blob: d5e147d269450af7307cf19f9c6540af767ea871 [file] [log] [blame]
Tom Warrenf4ef6662011-04-14 12:09:41 +00001/*
2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <asm/io.h>
26#include <asm/arch/tegra2.h>
Stephen Warrenae036612011-10-31 06:51:35 +000027#include <asm/arch/pinmux.h>
Thierry Reding977a39e2011-11-17 00:10:23 +000028#include <asm/arch/mmc.h>
Stephen Warren98778412011-10-31 06:51:36 +000029#include <asm/gpio.h>
Tom Warrenccf79882011-09-21 12:40:07 +000030#ifdef CONFIG_TEGRA2_MMC
31#include <mmc.h>
32#endif
Tom Warrenf4ef6662011-04-14 12:09:41 +000033
34/*
35 * Routine: gpio_config_uart
36 * Description: Does nothing on Harmony - no conflict w/SPI.
37 */
38void gpio_config_uart(void)
39{
40}
Tom Warrenccf79882011-09-21 12:40:07 +000041
42#ifdef CONFIG_TEGRA2_MMC
43/*
Stephen Warrenae036612011-10-31 06:51:35 +000044 * Routine: pin_mux_mmc
45 * Description: setup the pin muxes/tristate values for the SDMMC(s)
46 */
47static void pin_mux_mmc(void)
48{
49 /* SDMMC4: config 3, x8 on 2nd set of pins */
50 pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4);
51 pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4);
52 pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4);
53
54 pinmux_tristate_disable(PINGRP_ATB);
55 pinmux_tristate_disable(PINGRP_GMA);
56 pinmux_tristate_disable(PINGRP_GME);
57
58 /* For power GPIO PI6 */
59 pinmux_tristate_disable(PINGRP_ATA);
60 /* For CD GPIO PH2 */
61 pinmux_tristate_disable(PINGRP_ATD);
62
63 /* SDMMC2: SDIO2_CLK, SDIO2_CMD, SDIO2_DAT[7:0] */
64 pinmux_set_func(PINGRP_DTA, PMUX_FUNC_SDIO2);
65 pinmux_set_func(PINGRP_DTD, PMUX_FUNC_SDIO2);
66
67 pinmux_tristate_disable(PINGRP_DTA);
68 pinmux_tristate_disable(PINGRP_DTD);
69
70 /* For power GPIO PT3 */
71 pinmux_tristate_disable(PINGRP_DTB);
72 /* For CD GPIO PI5 */
73 pinmux_tristate_disable(PINGRP_ATC);
74}
75
Tom Warrenccf79882011-09-21 12:40:07 +000076/* this is a weak define that we are overriding */
Stephen Warrenae036612011-10-31 06:51:35 +000077int board_mmc_init(bd_t *bd)
78{
79 debug("board_mmc_init called\n");
80
81 /* Enable muxes, etc. for SDMMC controllers */
82 pin_mux_mmc();
Stephen Warrenae036612011-10-31 06:51:35 +000083
84 debug("board_mmc_init: init SD slot J26\n");
85 /* init dev 0, SD slot J26, with 4-bit bus */
86 /* The board has an 8-bit bus, but 8-bit doesn't work yet */
Stephen Warren98778412011-10-31 06:51:36 +000087 tegra2_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
Stephen Warrenae036612011-10-31 06:51:35 +000088
89 debug("board_mmc_init: init SD slot J5\n");
90 /* init dev 2, SD slot J5, with 4-bit bus */
Stephen Warren98778412011-10-31 06:51:36 +000091 tegra2_mmc_init(2, 4, GPIO_PT3, GPIO_PI5);
Stephen Warrenae036612011-10-31 06:51:35 +000092
93 return 0;
94}
Tom Warrenccf79882011-09-21 12:40:07 +000095#endif