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wdenk6f213472003-08-29 22:00:43 +00001/*
2 * armboot - Startup Code for ARM926EJS CPU-core
3 *
4 * Copyright (c) 2003 Texas Instruments
5 *
6 * ----- Adapted for OMAP1610 from ARM925t code ------
7 *
8 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
9 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
10 * Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
11 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
12 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
13 *
14 * See file CREDITS for list of people who contributed to this
15 * project.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * MA 02111-1307 USA
31 */
32
33
34
35#include <config.h>
36#include <version.h>
37
38#if defined(CONFIG_OMAP1610)
39#include <./configs/omap1510.h>
40#endif
41
42/*
43 *************************************************************************
44 *
45 * Jump vector table as in table 3.1 in [1]
46 *
47 *************************************************************************
48 */
49
50
51.globl _start
52_start:
53 b reset
54 ldr pc, _undefined_instruction
55 ldr pc, _software_interrupt
56 ldr pc, _prefetch_abort
57 ldr pc, _data_abort
58 ldr pc, _not_used
59 ldr pc, _irq
60 ldr pc, _fiq
61
62_undefined_instruction:
63 .word undefined_instruction
64_software_interrupt:
65 .word software_interrupt
66_prefetch_abort:
67 .word prefetch_abort
68_data_abort:
69 .word data_abort
70_not_used:
71 .word not_used
72_irq:
73 .word irq
74_fiq:
75 .word fiq
76
77 .balignl 16,0xdeadbeef
78
79
80/*
81 *************************************************************************
82 *
83 * Startup Code (reset vector)
84 *
85 * do important init only if we don't start from memory!
86 * setup Memory and board specific bits prior to relocation.
87 * relocate armboot to ram
88 * setup stack
89 *
90 *************************************************************************
91 */
92
93/*
94 * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
95 */
96_TEXT_BASE:
97 .word TEXT_BASE
98
99.globl _armboot_start
100_armboot_start:
101 .word _start
102
103/*
104 * Note: _armboot_end_data and _armboot_end are defined
105 * by the (board-dependent) linker script.
106 * _armboot_end_data is the first usable FLASH address after armboot
107 */
108.globl _armboot_end_data
109_armboot_end_data:
110 .word armboot_end_data
111.globl _armboot_end
112_armboot_end:
113 .word armboot_end
114
115/*
116 * _armboot_real_end is the first usable RAM address behind armboot
117 * and the various stacks
118 */
119.globl _armboot_real_end
120_armboot_real_end:
121 .word 0x0badc0de
122
123#ifdef CONFIG_USE_IRQ
124/* IRQ stack memory (calculated at run-time) */
125.globl IRQ_STACK_START
126IRQ_STACK_START:
127 .word 0x0badc0de
128
129/* IRQ stack memory (calculated at run-time) */
130.globl FIQ_STACK_START
131FIQ_STACK_START:
132 .word 0x0badc0de
133#endif
134
135
136/*
137 * the actual reset code
138 */
139
140reset:
141 /*
142 * set the cpu to SVC32 mode
143 */
144 mrs r0,cpsr
145 bic r0,r0,#0x1f
146 orr r0,r0,#0xd3
147 msr cpsr,r0
148
149
150 /*
151 * turn off the watchdog, unlock/diable sequence
152 */
153 mov r1, #0xF5
154 ldr r0, =WDTIM_MODE
155 strh r1, [r0]
156 mov r1, #0xA0
157 strh r1, [r0]
158
159
160
161
162
163 /*
164 * mask all IRQs by setting all bits in the INTMR - default
165 */
166
167 mov r1, #0xffffffff
168 ldr r0, =REG_IHL1_MIR
169 str r1, [r0]
170 ldr r0, =REG_IHL2_MIR
171 str r1, [r0]
172 bl cpu_init_crit
173
174relocate:
175 /*
176 * relocate armboot to RAM
177 */
178 adr r0, _start /* r0 <- current position of code */
179 ldr r2, _armboot_start
180 ldr r3, _armboot_end
181 sub r2, r3, r2 /* r2 <- size of armboot */
182 ldr r1, _TEXT_BASE /* r1 <- destination address */
183 add r2, r0, r2 /* r2 <- source end address */
184
185 /*
186 * r0 = source address
187 * r1 = target address
188 * r2 = source end address
189 */
190copy_loop:
191 ldmia r0!, {r3-r10}
192 stmia r1!, {r3-r10}
193 cmp r0, r2
194 ble copy_loop
195
196 /* set up the stack */
197 ldr r0, _armboot_end
198 add r0, r0, #CONFIG_STACKSIZE
199 sub sp, r0, #12 /* leave 3 words for abort-stack */
200
201 ldr pc, _start_armboot
202
203_start_armboot:
204 .word start_armboot
205
206
207/*
208 *************************************************************************
209 *
210 * CPU_init_critical registers
211 *
212 * setup important registers
213 * setup memory timing
214 *
215 *************************************************************************
216 */
217
218
219cpu_init_crit:
220 /*
221 * flush v4 I/D caches
222 */
223 mov r0, #0
224 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
225 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
226
227 /*
228 * disable MMU stuff and caches
229 */
230 mrc p15, 0, r0, c1, c0, 0
231 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
232 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
233 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
234 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
235 mcr p15, 0, r0, c1, c0, 0
236
237 /*
238 * Go setup Memory and board specific bits prior to relocation.
239 */
240 mov ip, lr /* perserve link reg across call */
241 bl platformsetup /* go setup pll,mux,memory */
242 mov lr, ip /* restore link */
243 mov pc, lr /* back to my caller */
244/*
245 *************************************************************************
246 *
247 * Interrupt handling
248 *
249 *************************************************************************
250 */
251
252@
253@ IRQ stack frame.
254@
255#define S_FRAME_SIZE 72
256
257#define S_OLD_R0 68
258#define S_PSR 64
259#define S_PC 60
260#define S_LR 56
261#define S_SP 52
262
263#define S_IP 48
264#define S_FP 44
265#define S_R10 40
266#define S_R9 36
267#define S_R8 32
268#define S_R7 28
269#define S_R6 24
270#define S_R5 20
271#define S_R4 16
272#define S_R3 12
273#define S_R2 8
274#define S_R1 4
275#define S_R0 0
276
277#define MODE_SVC 0x13
278#define I_BIT 0x80
279
280/*
281 * use bad_save_user_regs for abort/prefetch/undef/swi ...
282 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
283 */
284
285 .macro bad_save_user_regs
286 @ carve out a frame on current user stack
287 sub sp, sp, #S_FRAME_SIZE
288 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
289 ldr r2, _armboot_end @ find top of stack
290 add r2, r2, #CONFIG_STACKSIZE @ find base of normal stack
291 sub r2, r2, #8 @ set base 2 words into abort stack
292 @ get values for "aborted" pc and cpsr (into parm regs)
293 ldmia r2, {r2 - r3}
294 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
295 add r5, sp, #S_SP
296 mov r1, lr
297 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
298 mov r0, sp @ save current stack into r0 (param register)
299 .endm
300
301 .macro irq_save_user_regs
302 sub sp, sp, #S_FRAME_SIZE
303 stmia sp, {r0 - r12} @ Calling r0-r12
304 @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
305 add r8, sp, #S_PC
306 stmdb r8, {sp, lr}^ @ Calling SP, LR
307 str lr, [r8, #0] @ Save calling PC
308 mrs r6, spsr
309 str r6, [r8, #4] @ Save CPSR
310 str r0, [r8, #8] @ Save OLD_R0
311 mov r0, sp
312 .endm
313
314 .macro irq_restore_user_regs
315 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
316 mov r0, r0
317 ldr lr, [sp, #S_PC] @ Get PC
318 add sp, sp, #S_FRAME_SIZE
319 subs pc, lr, #4 @ return & move spsr_svc into cpsr
320 .endm
321
322 .macro get_bad_stack
323 @ get bottom of stack (into sp by by user stack pointer).
324 ldr r13, _armboot_end
325 @ head to reserved words at the top of the stack
326 add r13, r13, #CONFIG_STACKSIZE
327 sub r13, r13, #8 @ reserved a couple spots in abort stack
328
329 str lr, [r13] @ save caller lr in position 0 of saved stack
330 mrs lr, spsr @ get the spsr
331 str lr, [r13, #4] @ save spsr in position 1 of saved stack
332 mov r13, #MODE_SVC @ prepare SVC-Mode
333 @ msr spsr_c, r13
334 msr spsr, r13 @ switch modes, make sure moves will execute
335 mov lr, pc @ capture return pc
336 movs pc, lr @ jump to next instruction & switch modes.
337 .endm
338
339 .macro get_irq_stack @ setup IRQ stack
340 ldr sp, IRQ_STACK_START
341 .endm
342
343 .macro get_fiq_stack @ setup FIQ stack
344 ldr sp, FIQ_STACK_START
345 .endm
346
347/*
348 * exception handlers
349 */
350 .align 5
351undefined_instruction:
352 get_bad_stack
353 bad_save_user_regs
354 bl do_undefined_instruction
355
356 .align 5
357software_interrupt:
358 get_bad_stack
359 bad_save_user_regs
360 bl do_software_interrupt
361
362 .align 5
363prefetch_abort:
364 get_bad_stack
365 bad_save_user_regs
366 bl do_prefetch_abort
367
368 .align 5
369data_abort:
370 get_bad_stack
371 bad_save_user_regs
372 bl do_data_abort
373
374 .align 5
375not_used:
376 get_bad_stack
377 bad_save_user_regs
378 bl do_not_used
379
380#ifdef CONFIG_USE_IRQ
381
382 .align 5
383irq:
384 get_irq_stack
385 irq_save_user_regs
386 bl do_irq
387 irq_restore_user_regs
388
389 .align 5
390fiq:
391 get_fiq_stack
392 /* someone ought to write a more effiction fiq_save_user_regs */
393 irq_save_user_regs
394 bl do_fiq
395 irq_restore_user_regs
396
397#else
398
399 .align 5
400irq:
401 get_bad_stack
402 bad_save_user_regs
403 bl do_irq
404
405 .align 5
406fiq:
407 get_bad_stack
408 bad_save_user_regs
409 bl do_fiq
410
411#endif
412
413 .align 5
414.globl reset_cpu
415reset_cpu:
416 ldr r1, rstctl1 /* get clkm1 reset ctl */
417 mov r3, #0x0
418 strh r3, [r1] /* clear it */
419 mov r3, #0x8
420 strh r3, [r1] /* force dsp+arm reset */
421_loop_forever:
422 b _loop_forever
423
424
425rstctl1:
426 .word 0xfffece10