| Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2015-2016 Marvell International Ltd. |
| Stefan Roese | c0132f6 | 2016-08-30 16:48:20 +0200 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef _SATA_H_ |
| 7 | #define _SATA_H_ |
| 8 | |
| 9 | /* SATA3 Unit address */ |
| 10 | #define SATA3_VENDOR_ADDRESS 0xA0 |
| 11 | #define SATA3_VENDOR_ADDR_OFSSET 0 |
| 12 | #define SATA3_VENDOR_ADDR_MASK (0xFFFFFFFF << SATA3_VENDOR_ADDR_OFSSET) |
| 13 | #define SATA3_VENDOR_DATA 0xA4 |
| 14 | |
| 15 | #define SATA_CONTROL_REG 0x0 |
| 16 | #define SATA3_CTRL_SATA0_PD_OFFSET 6 |
| 17 | #define SATA3_CTRL_SATA0_PD_MASK (1 << SATA3_CTRL_SATA0_PD_OFFSET) |
| 18 | #define SATA3_CTRL_SATA1_PD_OFFSET 14 |
| 19 | #define SATA3_CTRL_SATA1_PD_MASK (1 << SATA3_CTRL_SATA1_PD_OFFSET) |
| 20 | #define SATA3_CTRL_SATA1_ENABLE_OFFSET 22 |
| 21 | #define SATA3_CTRL_SATA1_ENABLE_MASK (1 << SATA3_CTRL_SATA1_ENABLE_OFFSET) |
| 22 | #define SATA3_CTRL_SATA_SSU_OFFSET 23 |
| 23 | #define SATA3_CTRL_SATA_SSU_MASK (1 << SATA3_CTRL_SATA_SSU_OFFSET) |
| 24 | |
| 25 | #define SATA_MBUS_SIZE_SELECT_REG 0x4 |
| 26 | #define SATA_MBUS_REGRET_EN_OFFSET 7 |
| 27 | #define SATA_MBUS_REGRET_EN_MASK (0x1 << SATA_MBUS_REGRET_EN_OFFSET) |
| 28 | |
| 29 | #endif /* _SATA_H_ */ |