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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk4a9cbbe2002-08-27 09:48:53 +00002/*
3 * (C) Copyright 2000, 2001
4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
wdenk4a9cbbe2002-08-27 09:48:53 +00005 */
6
7/*
8 * FPGA support
9 */
10#include <common.h>
11#include <command.h>
wdenk8bde7f72003-06-27 21:31:46 +000012#include <fpga.h>
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +053013#include <fs.h>
wdenkc3d2b4b2005-01-22 18:13:04 +000014#include <malloc.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000015
wdenk4a9cbbe2002-08-27 09:48:53 +000016/* Local functions */
Michal Simekfc598412013-04-26 13:10:07 +020017static int fpga_get_op(char *opstr);
wdenk4a9cbbe2002-08-27 09:48:53 +000018
19/* Local defines */
Michal Simek5cf22282017-01-06 11:20:54 +010020enum {
21 FPGA_NONE = -1,
22 FPGA_INFO,
23 FPGA_LOAD,
24 FPGA_LOADB,
25 FPGA_DUMP,
26 FPGA_LOADMK,
27 FPGA_LOADP,
28 FPGA_LOADBP,
29 FPGA_LOADFS,
30};
wdenk4a9cbbe2002-08-27 09:48:53 +000031
32/* ------------------------------------------------------------------------- */
33/* command form:
34 * fpga <op> <device number> <data addr> <datasize>
35 * where op is 'load', 'dump', or 'info'
36 * If there is no device number field, the fpga environment variable is used.
37 * If there is no data addr field, the fpgadata environment variable is used.
38 * The info command requires no data address field.
39 */
Michal Simekfc598412013-04-26 13:10:07 +020040int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
wdenk4a9cbbe2002-08-27 09:48:53 +000041{
wdenkd4ca31c2004-01-02 14:00:00 +000042 int op, dev = FPGA_INVALID_DEVICE;
43 size_t data_size = 0;
44 void *fpga_data = NULL;
Simon Glass00caae62017-08-03 12:22:12 -060045 char *devstr = env_get("fpga");
46 char *datastr = env_get("fpgadata");
wdenkd4ca31c2004-01-02 14:00:00 +000047 int rc = FPGA_FAIL;
Stefano Babica790b5b2010-10-19 09:22:52 +020048 int wrong_parms = 0;
Michal Simekfc598412013-04-26 13:10:07 +020049#if defined(CONFIG_FIT)
Marian Balakowiczc28c4d12008-03-12 10:33:01 +010050 const char *fit_uname = NULL;
51 ulong fit_addr;
52#endif
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +053053#if defined(CONFIG_CMD_FPGA_LOADFS)
54 fpga_fs_info fpga_fsinfo;
55 fpga_fsinfo.fstype = FS_TYPE_ANY;
56#endif
wdenk4a9cbbe2002-08-27 09:48:53 +000057
wdenkd4ca31c2004-01-02 14:00:00 +000058 if (devstr)
Michal Simekfc598412013-04-26 13:10:07 +020059 dev = (int) simple_strtoul(devstr, NULL, 16);
wdenkd4ca31c2004-01-02 14:00:00 +000060 if (datastr)
Michal Simekfc598412013-04-26 13:10:07 +020061 fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
wdenk4a9cbbe2002-08-27 09:48:53 +000062
Siva Durga Prasad Paladuguf5953612018-05-31 15:10:21 +053063 if (argc > 9 || argc < 2) {
64 debug("%s: Too many or too few args (%d)\n", __func__, argc);
65 return CMD_RET_USAGE;
66 }
67
68 op = (int)fpga_get_op(argv[1]);
69
70 switch (op) {
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +053071#if defined(CONFIG_CMD_FPGA_LOADFS)
Siva Durga Prasad Paladuguf5953612018-05-31 15:10:21 +053072 case FPGA_LOADFS:
73 if (argc < 9)
74 return CMD_RET_USAGE;
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +053075 fpga_fsinfo.blocksize = (unsigned int)
Siva Durga Prasad Paladuguf5953612018-05-31 15:10:21 +053076 simple_strtoul(argv[5], NULL, 16);
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +053077 fpga_fsinfo.interface = argv[6];
78 fpga_fsinfo.dev_part = argv[7];
79 fpga_fsinfo.filename = argv[8];
Siva Durga Prasad Paladuguf5953612018-05-31 15:10:21 +053080 argc = 5;
81 break;
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +053082#endif
Siva Durga Prasad Paladuguf5953612018-05-31 15:10:21 +053083 default:
84 break;
85 }
86
87 switch (argc) {
wdenkd4ca31c2004-01-02 14:00:00 +000088 case 5: /* fpga <op> <dev> <data> <datasize> */
Michal Simekfc598412013-04-26 13:10:07 +020089 data_size = simple_strtoul(argv[4], NULL, 16);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +010090
wdenkd4ca31c2004-01-02 14:00:00 +000091 case 4: /* fpga <op> <dev> <data> */
Marian Balakowiczc28c4d12008-03-12 10:33:01 +010092#if defined(CONFIG_FIT)
Michal Simekfc598412013-04-26 13:10:07 +020093 if (fit_parse_subimage(argv[3], (ulong)fpga_data,
94 &fit_addr, &fit_uname)) {
Marian Balakowiczc28c4d12008-03-12 10:33:01 +010095 fpga_data = (void *)fit_addr;
Michal Simekfc598412013-04-26 13:10:07 +020096 debug("* fpga: subimage '%s' from FIT image ",
97 fit_uname);
98 debug("at 0x%08lx\n", fit_addr);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +010099 } else
100#endif
101 {
Michal Simekfc598412013-04-26 13:10:07 +0200102 fpga_data = (void *)simple_strtoul(argv[3], NULL, 16);
Stefano Babic06297db2011-12-28 06:47:01 +0000103 debug("* fpga: cmdline image address = 0x%08lx\n",
Michal Simekfc598412013-04-26 13:10:07 +0200104 (ulong)fpga_data);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100105 }
Michal Simek455ad582016-01-05 13:51:48 +0100106 debug("%s: fpga_data = 0x%lx\n", __func__, (ulong)fpga_data);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100107
wdenkd4ca31c2004-01-02 14:00:00 +0000108 case 3: /* fpga <op> <dev | data addr> */
Michal Simekfc598412013-04-26 13:10:07 +0200109 dev = (int)simple_strtoul(argv[2], NULL, 16);
Stefano Babic06297db2011-12-28 06:47:01 +0000110 debug("%s: device = %d\n", __func__, dev);
wdenkd4ca31c2004-01-02 14:00:00 +0000111 /* FIXME - this is a really weak test */
Michal Simekfc598412013-04-26 13:10:07 +0200112 if ((argc == 3) && (dev > fpga_count())) {
113 /* must be buffer ptr */
Stefano Babic06297db2011-12-28 06:47:01 +0000114 debug("%s: Assuming buffer pointer in arg 3\n",
Michal Simekfc598412013-04-26 13:10:07 +0200115 __func__);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100116
117#if defined(CONFIG_FIT)
Michal Simekfc598412013-04-26 13:10:07 +0200118 if (fit_parse_subimage(argv[2], (ulong)fpga_data,
119 &fit_addr, &fit_uname)) {
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100120 fpga_data = (void *)fit_addr;
Michal Simekfc598412013-04-26 13:10:07 +0200121 debug("* fpga: subimage '%s' from FIT image ",
122 fit_uname);
123 debug("at 0x%08lx\n", fit_addr);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100124 } else
125#endif
126 {
Michal Simek455ad582016-01-05 13:51:48 +0100127 fpga_data = (void *)(uintptr_t)dev;
Michal Simekfc598412013-04-26 13:10:07 +0200128 debug("* fpga: cmdline image addr = 0x%08lx\n",
129 (ulong)fpga_data);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100130 }
131
Michal Simek455ad582016-01-05 13:51:48 +0100132 debug("%s: fpga_data = 0x%lx\n",
133 __func__, (ulong)fpga_data);
wdenkd4ca31c2004-01-02 14:00:00 +0000134 dev = FPGA_INVALID_DEVICE; /* reset device num */
135 }
wdenkd4ca31c2004-01-02 14:00:00 +0000136 }
wdenk4a9cbbe2002-08-27 09:48:53 +0000137
Stefano Babica790b5b2010-10-19 09:22:52 +0200138 if (dev == FPGA_INVALID_DEVICE) {
139 puts("FPGA device not specified\n");
140 op = FPGA_NONE;
141 }
142
143 switch (op) {
144 case FPGA_NONE:
145 case FPGA_INFO:
146 break;
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530147#if defined(CONFIG_CMD_FPGA_LOADFS)
148 case FPGA_LOADFS:
149 /* Blocksize can be zero */
150 if (!fpga_fsinfo.interface || !fpga_fsinfo.dev_part ||
151 !fpga_fsinfo.filename)
152 wrong_parms = 1;
153#endif
Stefano Babica790b5b2010-10-19 09:22:52 +0200154 case FPGA_LOAD:
Michal Simek67193862014-05-02 13:43:39 +0200155 case FPGA_LOADP:
Stefano Babica790b5b2010-10-19 09:22:52 +0200156 case FPGA_LOADB:
Michal Simek67193862014-05-02 13:43:39 +0200157 case FPGA_LOADBP:
Stefano Babica790b5b2010-10-19 09:22:52 +0200158 case FPGA_DUMP:
159 if (!fpga_data || !data_size)
160 wrong_parms = 1;
161 break;
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530162#if defined(CONFIG_CMD_FPGA_LOADMK)
Stefano Babica790b5b2010-10-19 09:22:52 +0200163 case FPGA_LOADMK:
164 if (!fpga_data)
165 wrong_parms = 1;
166 break;
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530167#endif
Stefano Babica790b5b2010-10-19 09:22:52 +0200168 }
169
170 if (wrong_parms) {
171 puts("Wrong parameters for FPGA request\n");
172 op = FPGA_NONE;
173 }
174
wdenkd4ca31c2004-01-02 14:00:00 +0000175 switch (op) {
176 case FPGA_NONE:
Simon Glass4c12eeb2011-12-10 08:44:01 +0000177 return CMD_RET_USAGE;
wdenk4a9cbbe2002-08-27 09:48:53 +0000178
wdenkd4ca31c2004-01-02 14:00:00 +0000179 case FPGA_INFO:
Michal Simekfc598412013-04-26 13:10:07 +0200180 rc = fpga_info(dev);
wdenkd4ca31c2004-01-02 14:00:00 +0000181 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000182
wdenkd4ca31c2004-01-02 14:00:00 +0000183 case FPGA_LOAD:
Michal Simek7a78bd22014-05-02 14:09:30 +0200184 rc = fpga_load(dev, fpga_data, data_size, BIT_FULL);
wdenkd4ca31c2004-01-02 14:00:00 +0000185 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000186
Michal Simek67193862014-05-02 13:43:39 +0200187#if defined(CONFIG_CMD_FPGA_LOADP)
188 case FPGA_LOADP:
189 rc = fpga_load(dev, fpga_data, data_size, BIT_PARTIAL);
190 break;
191#endif
192
wdenk30ce5ab2005-01-09 18:12:51 +0000193 case FPGA_LOADB:
Michal Simek7a78bd22014-05-02 14:09:30 +0200194 rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_FULL);
wdenk30ce5ab2005-01-09 18:12:51 +0000195 break;
196
Michal Simek67193862014-05-02 13:43:39 +0200197#if defined(CONFIG_CMD_FPGA_LOADBP)
198 case FPGA_LOADBP:
199 rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_PARTIAL);
200 break;
201#endif
202
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530203#if defined(CONFIG_CMD_FPGA_LOADFS)
204 case FPGA_LOADFS:
205 rc = fpga_fsload(dev, fpga_data, data_size, &fpga_fsinfo);
206 break;
207#endif
208
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530209#if defined(CONFIG_CMD_FPGA_LOADMK)
Stefan Roesef0ff4692006-08-15 14:15:51 +0200210 case FPGA_LOADMK:
Michal Simekfc598412013-04-26 13:10:07 +0200211 switch (genimg_get_format(fpga_data)) {
Heiko Schocher21d29f72014-05-28 11:33:33 +0200212#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100213 case IMAGE_FORMAT_LEGACY:
214 {
Michal Simekfc598412013-04-26 13:10:07 +0200215 image_header_t *hdr =
216 (image_header_t *)fpga_data;
217 ulong data;
Michal Simek32d7cdd2013-10-04 10:51:01 +0200218 uint8_t comp;
Stefan Roesef0ff4692006-08-15 14:15:51 +0200219
Michal Simek32d7cdd2013-10-04 10:51:01 +0200220 comp = image_get_comp(hdr);
221 if (comp == IH_COMP_GZIP) {
Michal Simek1b63aaa2014-07-16 10:30:50 +0200222#if defined(CONFIG_GZIP)
Michal Simek32d7cdd2013-10-04 10:51:01 +0200223 ulong image_buf = image_get_data(hdr);
224 data = image_get_load(hdr);
225 ulong image_size = ~0UL;
226
227 if (gunzip((void *)data, ~0UL,
228 (void *)image_buf,
229 &image_size) != 0) {
230 puts("GUNZIP: error\n");
231 return 1;
232 }
233 data_size = image_size;
Michal Simek1b63aaa2014-07-16 10:30:50 +0200234#else
235 puts("Gunzip image is not supported\n");
236 return 1;
237#endif
Michal Simek32d7cdd2013-10-04 10:51:01 +0200238 } else {
239 data = (ulong)image_get_data(hdr);
240 data_size = image_get_data_size(hdr);
241 }
Michal Simek7a78bd22014-05-02 14:09:30 +0200242 rc = fpga_load(dev, (void *)data, data_size,
243 BIT_FULL);
Stefan Roesef0ff4692006-08-15 14:15:51 +0200244 }
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100245 break;
Heiko Schocher21d29f72014-05-28 11:33:33 +0200246#endif
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100247#if defined(CONFIG_FIT)
248 case IMAGE_FORMAT_FIT:
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100249 {
250 const void *fit_hdr = (const void *)fpga_data;
251 int noffset;
Wolfgang Denke6a857d2011-07-30 13:33:49 +0000252 const void *fit_data;
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100253
254 if (fit_uname == NULL) {
Michal Simekfc598412013-04-26 13:10:07 +0200255 puts("No FIT subimage unit name\n");
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100256 return 1;
257 }
258
Michal Simekfc598412013-04-26 13:10:07 +0200259 if (!fit_check_format(fit_hdr)) {
260 puts("Bad FIT image format\n");
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100261 return 1;
262 }
263
264 /* get fpga component image node offset */
Michal Simekfc598412013-04-26 13:10:07 +0200265 noffset = fit_image_get_node(fit_hdr,
266 fit_uname);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100267 if (noffset < 0) {
Michal Simekfc598412013-04-26 13:10:07 +0200268 printf("Can't find '%s' FIT subimage\n",
269 fit_uname);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100270 return 1;
271 }
272
273 /* verify integrity */
Simon Glassb8da8362013-05-07 06:11:57 +0000274 if (!fit_image_verify(fit_hdr, noffset)) {
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100275 puts ("Bad Data Hash\n");
276 return 1;
277 }
278
279 /* get fpga subimage data address and length */
Michal Simekfc598412013-04-26 13:10:07 +0200280 if (fit_image_get_data(fit_hdr, noffset,
281 &fit_data, &data_size)) {
282 puts("Fpga subimage data not found\n");
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100283 return 1;
284 }
285
Michal Simek7a78bd22014-05-02 14:09:30 +0200286 rc = fpga_load(dev, fit_data, data_size,
287 BIT_FULL);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100288 }
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100289 break;
290#endif
291 default:
Michal Simekfc598412013-04-26 13:10:07 +0200292 puts("** Unknown image type\n");
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100293 rc = FPGA_FAIL;
294 break;
Stefan Roesef0ff4692006-08-15 14:15:51 +0200295 }
296 break;
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530297#endif
Stefan Roesef0ff4692006-08-15 14:15:51 +0200298
wdenkd4ca31c2004-01-02 14:00:00 +0000299 case FPGA_DUMP:
Michal Simekfc598412013-04-26 13:10:07 +0200300 rc = fpga_dump(dev, fpga_data, data_size);
wdenkd4ca31c2004-01-02 14:00:00 +0000301 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000302
wdenkd4ca31c2004-01-02 14:00:00 +0000303 default:
Michal Simekfc598412013-04-26 13:10:07 +0200304 printf("Unknown operation\n");
Simon Glass4c12eeb2011-12-10 08:44:01 +0000305 return CMD_RET_USAGE;
wdenkd4ca31c2004-01-02 14:00:00 +0000306 }
Michal Simekfc598412013-04-26 13:10:07 +0200307 return rc;
wdenk4a9cbbe2002-08-27 09:48:53 +0000308}
309
wdenk4a9cbbe2002-08-27 09:48:53 +0000310/*
311 * Map op to supported operations. We don't use a table since we
312 * would just have to relocate it from flash anyway.
313 */
Michal Simekfc598412013-04-26 13:10:07 +0200314static int fpga_get_op(char *opstr)
wdenk4a9cbbe2002-08-27 09:48:53 +0000315{
316 int op = FPGA_NONE;
317
Michal Simekfc598412013-04-26 13:10:07 +0200318 if (!strcmp("info", opstr))
wdenk4a9cbbe2002-08-27 09:48:53 +0000319 op = FPGA_INFO;
Michal Simekfc598412013-04-26 13:10:07 +0200320 else if (!strcmp("loadb", opstr))
wdenk30ce5ab2005-01-09 18:12:51 +0000321 op = FPGA_LOADB;
Michal Simekfc598412013-04-26 13:10:07 +0200322 else if (!strcmp("load", opstr))
wdenk4a9cbbe2002-08-27 09:48:53 +0000323 op = FPGA_LOAD;
Michal Simek67193862014-05-02 13:43:39 +0200324#if defined(CONFIG_CMD_FPGA_LOADP)
325 else if (!strcmp("loadp", opstr))
326 op = FPGA_LOADP;
327#endif
328#if defined(CONFIG_CMD_FPGA_LOADBP)
329 else if (!strcmp("loadbp", opstr))
330 op = FPGA_LOADBP;
331#endif
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530332#if defined(CONFIG_CMD_FPGA_LOADFS)
333 else if (!strcmp("loadfs", opstr))
334 op = FPGA_LOADFS;
335#endif
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530336#if defined(CONFIG_CMD_FPGA_LOADMK)
Michal Simekfc598412013-04-26 13:10:07 +0200337 else if (!strcmp("loadmk", opstr))
Stefan Roesef0ff4692006-08-15 14:15:51 +0200338 op = FPGA_LOADMK;
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530339#endif
Michal Simekfc598412013-04-26 13:10:07 +0200340 else if (!strcmp("dump", opstr))
wdenk4a9cbbe2002-08-27 09:48:53 +0000341 op = FPGA_DUMP;
wdenk4a9cbbe2002-08-27 09:48:53 +0000342
Michal Simekfc598412013-04-26 13:10:07 +0200343 if (op == FPGA_NONE)
344 printf("Unknown fpga operation \"%s\"\n", opstr);
345
wdenk4a9cbbe2002-08-27 09:48:53 +0000346 return op;
347}
348
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530349#if defined(CONFIG_CMD_FPGA_LOADFS)
350U_BOOT_CMD(fpga, 9, 1, do_fpga,
351#else
Michal Simekfc598412013-04-26 13:10:07 +0200352U_BOOT_CMD(fpga, 6, 1, do_fpga,
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530353#endif
Michal Simekfc598412013-04-26 13:10:07 +0200354 "loadable FPGA image support",
355 "[operation type] [device number] [image address] [image size]\n"
356 "fpga operations:\n"
Michal Simek2d73f0d2015-01-26 08:52:27 +0100357 " dump\t[dev] [address] [size]\tLoad device to memory buffer\n"
Michal Simekfc598412013-04-26 13:10:07 +0200358 " info\t[dev]\t\t\tlist known device information\n"
359 " load\t[dev] [address] [size]\tLoad device from memory buffer\n"
Michal Simek67193862014-05-02 13:43:39 +0200360#if defined(CONFIG_CMD_FPGA_LOADP)
361 " loadp\t[dev] [address] [size]\t"
362 "Load device from memory buffer with partial bitstream\n"
363#endif
Michal Simekfc598412013-04-26 13:10:07 +0200364 " loadb\t[dev] [address] [size]\t"
365 "Load device from bitstream buffer (Xilinx only)\n"
Michal Simek67193862014-05-02 13:43:39 +0200366#if defined(CONFIG_CMD_FPGA_LOADBP)
367 " loadbp\t[dev] [address] [size]\t"
368 "Load device from bitstream buffer with partial bitstream"
369 "(Xilinx only)\n"
370#endif
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530371#if defined(CONFIG_CMD_FPGA_LOADFS)
372 "Load device from filesystem (FAT by default) (Xilinx only)\n"
373 " loadfs [dev] [address] [image size] [blocksize] <interface>\n"
374 " [<dev[:part]>] <filename>\n"
375#endif
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530376#if defined(CONFIG_CMD_FPGA_LOADMK)
Michal Simekfc598412013-04-26 13:10:07 +0200377 " loadmk [dev] [address]\tLoad device generated with mkimage"
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100378#if defined(CONFIG_FIT)
Michal Simekfc598412013-04-26 13:10:07 +0200379 "\n"
380 "\tFor loadmk operating on FIT format uImage address must include\n"
381 "\tsubimage unit name in the form of addr:<subimg_uname>"
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100382#endif
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530383#endif
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100384);