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wdenkd9fd6ff2002-10-11 08:43:32 +00001/*
2 * (C) Copyright 2002
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <asm/arch/pxa-regs.h>
29#include <common.h>
30
31/* ------------------------------------------------------------------------- */
32
33
34/* local prototypes */
35void set_led (int led, int color);
36void error_code_halt (int code);
37int init_sio (int led, unsigned long base);
38inline void cradle_outb (unsigned short val, unsigned long base,
39 unsigned long reg);
40inline unsigned char cradle_inb (unsigned long base, unsigned long reg);
41inline void sleep (int i);
42
43inline void
44/**********************************************************/
45sleep (int i)
46/**********************************************************/
47{
48 while (i--) {
49 udelay (1000000);
50 }
51}
52
53void
54/**********************************************************/
55error_code_halt (int code)
56/**********************************************************/
57{
58 while (1) {
59 led_code (code, RED);
60 sleep (1);
61 led_code (0, OFF);
62 sleep (1);
63 }
64}
65
66void
67/**********************************************************/
68led_code (int code, int color)
69/**********************************************************/
70{
71 int i;
72
73 code &= 0xf; /* only 4 leds */
74
75 for (i = 0; i < 4; i++) {
76 if (code & (1 << i)) {
77 set_led (i, color);
78 } else {
79 set_led (i, OFF);
80 }
81 }
82}
83
84void
85/**********************************************************/
86set_led (int led, int color)
87/**********************************************************/
88{
89 int shift = led * 2;
90 unsigned long mask = 0x3 << shift;
91
92 CRADLE_LED_CLR_REG = mask; /* clear bits */
93 CRADLE_LED_SET_REG = (color << shift); /* set bits */
94 udelay (5000);
95}
96
97inline void
98/**********************************************************/
99cradle_outb (unsigned short val, unsigned long base, unsigned long reg)
100/**********************************************************/
101{
102 *(volatile unsigned short *) (base + (reg * 2)) = val;
103}
104
105inline unsigned char
106/**********************************************************/
107cradle_inb (unsigned long base, unsigned long reg)
108/**********************************************************/
109{
110 unsigned short val;
111
112 val = *(volatile unsigned short *) (base + (reg * 2));
113 return (val & 0xff);
114}
115
116int
117/**********************************************************/
118init_sio (int led, unsigned long base)
119/**********************************************************/
120{
121 unsigned char val;
122
123 set_led (led, YELLOW);
124 val = cradle_inb (base, CRADLE_SIO_INDEX);
125 val = cradle_inb (base, CRADLE_SIO_INDEX);
126 if (val != 0) {
127 set_led (led, RED);
128 return -1;
129 }
130
131 /* map SCC2 to COM1 */
132 cradle_outb (0x01, base, CRADLE_SIO_INDEX);
133 cradle_outb (0x00, base, CRADLE_SIO_DATA);
134
135 /* enable SCC2 extended regs */
136 cradle_outb (0x40, base, CRADLE_SIO_INDEX);
137 cradle_outb (0xa0, base, CRADLE_SIO_DATA);
138
139 /* enable SCC2 clock multiplier */
140 cradle_outb (0x51, base, CRADLE_SIO_INDEX);
141 cradle_outb (0x04, base, CRADLE_SIO_DATA);
142
143 /* enable SCC2 */
144 cradle_outb (0x00, base, CRADLE_SIO_INDEX);
145 cradle_outb (0x04, base, CRADLE_SIO_DATA);
146
147 /* map SCC2 DMA to channel 0 */
148 cradle_outb (0x4f, base, CRADLE_SIO_INDEX);
149 cradle_outb (0x09, base, CRADLE_SIO_DATA);
150
151 /* read ID from SIO to check operation */
152 cradle_outb (0xe4, base, 0x3f8 + 0x3);
153 val = cradle_inb (base, 0x3f8 + 0x0);
154 if ((val & 0xf0) != 0x20) {
155 set_led (led, RED);
156 /* disable SCC2 */
157 cradle_outb (0, base, CRADLE_SIO_INDEX);
158 cradle_outb (0, base, CRADLE_SIO_DATA);
159 return -1;
160 }
161 /* set back to bank 0 */
162 cradle_outb (0, base, 0x3f8 + 0x3);
163 set_led (led, GREEN);
164 return 0;
165}
166
167/*
168 * Miscelaneous platform dependent initialisations
169 */
170
171int
172/**********************************************************/
wdenkc837dcb2004-01-20 23:12:12 +0000173board_late_init (void)
wdenkd9fd6ff2002-10-11 08:43:32 +0000174/**********************************************************/
175{
176 return (0);
177}
178
179int
180/**********************************************************/
181board_init (void)
182/**********************************************************/
183{
184 DECLARE_GLOBAL_DATA_PTR;
185
186 led_code (0xf, YELLOW);
187
188 /* arch number of HHP Cradle */
wdenk731215e2004-10-10 18:41:04 +0000189 gd->bd->bi_arch_number = MACH_TYPE_HHP_CRADLE;
wdenkd9fd6ff2002-10-11 08:43:32 +0000190
191 /* adress of boot parameters */
192 gd->bd->bi_boot_params = 0xa0000100;
193
194 /* Init SIOs to enable SCC2 */
195 udelay (100000); /* delay makes it look neat */
196 init_sio (0, CRADLE_SIO1_PHYS);
197 udelay (100000);
198 init_sio (1, CRADLE_SIO2_PHYS);
199 udelay (100000);
200 init_sio (2, CRADLE_SIO3_PHYS);
201 udelay (100000);
202 set_led (3, GREEN);
203
204 return 1;
205}
206
207int
208/**********************************************************/
209dram_init (void)
210/**********************************************************/
211{
212 DECLARE_GLOBAL_DATA_PTR;
213
214 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
215 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
216 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
217 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
218 gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
219 gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
220 gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
221 gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
222
223 return (PHYS_SDRAM_1_SIZE +
224 PHYS_SDRAM_2_SIZE +
225 PHYS_SDRAM_3_SIZE +
226 PHYS_SDRAM_4_SIZE );
227}