| Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| Siva Durga Prasad Paladugu | 6b24501 | 2016-01-13 16:25:37 +0530 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2015 Xilinx, Inc, |
| Michal Simek | 174d7284 | 2023-07-10 14:35:49 +0200 | [diff] [blame] | 4 | * Michal Simek <michal.simek@amd.com> |
| Siva Durga Prasad Paladugu | 6b24501 | 2016-01-13 16:25:37 +0530 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef _ZYNQMPPL_H_ |
| 8 | #define _ZYNQMPPL_H_ |
| 9 | |
| 10 | #include <xilinx.h> |
| Simon Glass | cd93d62 | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 11 | #include <linux/bitops.h> |
| Siva Durga Prasad Paladugu | 6b24501 | 2016-01-13 16:25:37 +0530 | [diff] [blame] | 12 | |
| Siva Durga Prasad Paladugu | 6b24501 | 2016-01-13 16:25:37 +0530 | [diff] [blame] | 13 | #define ZYNQMP_FPGA_OP_INIT (1 << 0) |
| 14 | #define ZYNQMP_FPGA_OP_LOAD (1 << 1) |
| 15 | #define ZYNQMP_FPGA_OP_DONE (1 << 2) |
| 16 | |
| Siva Durga Prasad Paladugu | a18d09e | 2018-05-31 15:10:23 +0530 | [diff] [blame] | 17 | #define ZYNQMP_FPGA_FLAG_AUTHENTICATED BIT(2) |
| 18 | #define ZYNQMP_FPGA_FLAG_ENCRYPTED BIT(3) |
| 19 | |
| Soren Brinkmann | 0cba6ab | 2016-09-29 11:44:41 -0700 | [diff] [blame] | 20 | #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15 |
| 21 | #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xf << \ |
| 22 | ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT) |
| 23 | #define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12 |
| Michal Simek | 9268704 | 2017-06-28 15:40:32 +0200 | [diff] [blame] | 24 | #define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7 << ZYNQMP_CSU_IDCODE_SVD_SHIFT) |
| Soren Brinkmann | 0cba6ab | 2016-09-29 11:44:41 -0700 | [diff] [blame] | 25 | |
| Siva Durga Prasad Paladugu | 6b24501 | 2016-01-13 16:25:37 +0530 | [diff] [blame] | 26 | extern struct xilinx_fpga_op zynqmp_op; |
| 27 | |
| Oleksandr Suvorov | a3a1afb | 2022-07-22 17:16:13 +0300 | [diff] [blame] | 28 | #if CONFIG_IS_ENABLED(FPGA_LOAD_SECURE) |
| Adrian Fiergolski | b524f8f | 2022-07-22 17:16:14 +0300 | [diff] [blame] | 29 | #define ZYNQMP_FPGA_FLAGS (FPGA_LEGACY | \ |
| 30 | FPGA_XILINX_ZYNQMP_DDRAUTH | \ |
| 31 | FPGA_XILINX_ZYNQMP_ENC) |
| Oleksandr Suvorov | a3a1afb | 2022-07-22 17:16:13 +0300 | [diff] [blame] | 32 | #else |
| Oleksandr Suvorov | d7fcbfc | 2022-07-22 17:16:04 +0300 | [diff] [blame] | 33 | #define ZYNQMP_FPGA_FLAGS (FPGA_LEGACY) |
| Oleksandr Suvorov | a3a1afb | 2022-07-22 17:16:13 +0300 | [diff] [blame] | 34 | #endif |
| Siva Durga Prasad Paladugu | 6b24501 | 2016-01-13 16:25:37 +0530 | [diff] [blame] | 35 | |
| 36 | #endif /* _ZYNQMPPL_H_ */ |